library: Fix indentation issues

Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>

Author: PIoandan

library/util_sigma_delta_spi/util_sigma_delta_spi.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are

library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl

@@ -4,9 +4,8 @@
 #################################################################################
 
 # ip
-package require qsys 14.0
-#package require quartus::device
 
+package require qsys 14.0
 source ../../scripts/adi_env.tcl
 source ../scripts/adi_ip_intel.tcl
 
@@ -34,13 +33,13 @@ proc p_elaboration {} {
   ad_interface signal spi_active input 1 active
   ad_interface signal data_ready output 1 if_pwm
 
-  ad_interface clock s_sclk  input 1 sclk
+  ad_interface clock s_sclk   input 1 sclk
   ad_interface signal s_sdo   input 1 sdo
   ad_interface signal s_sdo_t input 1 sdo_t
   ad_interface signal s_sdi   output 1 sdi
   ad_interface signal s_cs    input $num_cs cs
 
-  ad_interface clock m_sclk  output 1
+  ad_interface clock m_sclk   output 1
   ad_interface signal m_sdo   output 1
   ad_interface signal m_sdo_t output 1
   ad_interface signal m_sdi   input 1