From 3a980c0280eb2c875f63201c5ee03ead38f48ccb Mon Sep 17 00:00:00 2001
From: Iulia Moldovan <Iulia.Moldovan@analog.com>
Date: Tue, 24 Oct 2023 13:55:01 +0300
Subject: [PATCH] docs/projects/ad9783: Add AD9783 project doc

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
---
 docs/projects/ad9783_ebz/index.rst | 96 +++++++++++++++++++-----------
 1 file changed, 62 insertions(+), 34 deletions(-)

diff --git a/docs/projects/ad9783_ebz/index.rst b/docs/projects/ad9783_ebz/index.rst
index e515261d695..ab108fbf4e2 100644
--- a/docs/projects/ad9783_ebz/index.rst
+++ b/docs/projects/ad9783_ebz/index.rst
@@ -25,6 +25,8 @@ Supported boards
 Supported devices
 -------------------------------------------------------------------------------
 
+-  :part:`AD9780`
+-  :part:`AD9781`
 -  :part:`AD9783`
 
 Supported carriers
@@ -51,14 +53,24 @@ Clock scheme
 -  External clock source connected to J1 (CLOCK IN)
 -  For maximum performance, give a 500 MHz clock
 
-Description of components
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
 To make the connection between the :part:`EVAL-AD9783` evaluation board and
 the carrier using SPI, some hardware changes must be done to the evaluation
 board. These are presented in detail in the **Connections and hardware changes**
 section.
 
+CPU/Memory interconnects addresses
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The addresses are dependent on the architecture of the FPGA, having an offset
+added to the base address from HDL (see more at :ref:`architecture`).
+
+============== =============== ===========
+Instance       Zynq/Microblaze ZynqMP
+============== =============== ===========
+axi_ad9783     0x7420_0000     0x9420_0000
+axi_ad9783_dma 0x7C42_0000     0x9C42_0000
+============== =============== ===========
+
 SPI connections
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -67,32 +79,18 @@ hardware changes must be done, which are explained in the system level
 documentation.
 
 .. list-table::
-   :widths: 10 20 20 20 20 10
+   :widths: 25 25 25 25
    :header-rows: 1
 
    * - SPI type
      - SPI manager instance
-     - Alias
-     - Address
      - SPI subordinate
      - CS nb
    * - PS
      - SPI 0
-     - spi_fpga
-     - 0xFF040000
      - AD9783
      - 0
 
-CPU/Memory interconnects addresses
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-============== ==========
-Instance       Address
-============== ==========
-axi_ad9783     0x74200000
-axi_ad9783_dma 0x7C420000
-============== ==========
-
 Interrupts
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -134,11 +132,35 @@ connection looks like this:
 Resources
 -------------------------------------------------------------------------------
 
+Systems related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Here you can find the quick start guides available for these evaluation boards:
+
+.. list-table::
+   :widths: 20 10 20 20 20 10
+   :header-rows: 1
+
+   * - Evaluation board
+     - Zynq-7000
+     - Zynq UltraScale+ MP
+     - Microblaze
+     - Versal
+     - Arria 10
+   * - AD9783-EBZ
+     - ---
+     - :dokuwiki:`[Wiki] ZCU102 <resources/fpga/xilinx/interposer/ad9783>`
+     - ---
+     - ---
+     - ---
+
 Hardware related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 -  Product datasheets:
 
+   -  :part:`AD9780`
+   -  :part:`AD9781`
    -  :part:`AD9783`
    -  :part:`EVAL-AD9783`
    -  :part:`AD-DAC-FMC`-ADP
@@ -146,19 +168,30 @@ Hardware related
 HDL related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
--  :git-hdl:`AXI_AD9783 <master:library/axi_ad9783>`
--  :git-hdl:`AD9783_EBZ HDL project <master:projects/ad9783_ebz>`
-
--  :git-hdl:`AXI_DMAC <master:library/axi_dmac>`
--  :git-hdl:`AXI_SYSID <master:library/axi_sysid>`
--  :git-hdl:`SYSID_ROM <master:library/sysid_rom>`
--  :git-hdl:`UTIL_UPACK2 <master:library/util_pack/util_upack2>`
+-  :git-hdl:`AD9783_EBZ HDL project source code <master:projects/ad9783_ebz>`
 
--  :dokuwiki:`[Wiki] AD9783-EBZ Quick Start Guide <resources/fpga/xilinx/interposer/ad9783>`
+.. list-table::
+   :widths: 30 35 35
+   :header-rows: 1
 
--  :ref:`AXI_DMAC <axi_dmac>`
--  :dokuwiki:`AXI_SYSID and SYSID_ROM <resources/fpga/docs/axi_sysid>`
--  :dokuwiki:`[Wiki] UTIL_CPACK2 (Channel CPACK Utility Core) <resources/fpga/docs/util_cpack>`
+   * - IP name
+     - Source code link
+     - Documentation link
+   * - AXI_AD9783
+     - :git-hdl:`library/axi_ad9783 <master:library/axi_ad9783>`
+     - :dokuwiki:`[Wiki] <resources/fpga/docs/axi_ad9783>`
+   * - AXI_DMAC
+     - :git-hdl:`library/axi_dmac <master:library/axi_dmac>`
+     - :ref:`here <axi_dmac>`
+   * - AXI_SYSID
+     - :git-hdl:`library/axi_sysid <master:library/axi_sysid>`
+     - :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
+   * - SYSID_ROM
+     - :git-hdl:`library/sysid_rom <master:library/sysid_rom>`
+     - :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
+   * - UTIL_UPACK2
+     - :git-hdl:`library/util_pack/util_upack2 <master:library/util_pack/util_upack2>`
+     - :dokuwiki:`[Wiki] <resources/fpga/docs/util_upack>`
 
 Software related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -166,11 +199,6 @@ Software related
 -  :git-linux:`Linux device tree zynqmp-zcu102-rev10-ad9783.dts <master:arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9783.dts>`
 -  :git-linux:`Linux driver ad9783.c <master:drivers/iio/frequency>`
 
-Systems related
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
--  :dokuwiki:`[Wiki] AD9783-EBZ Quick Start Guide <resources/fpga/xilinx/interposer/ad9783>`
-
 .. include:: ../common/more_information.rst
 
 .. include:: ../common/support.rst