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            y="-105.21566"
-           x="558.31366"
+           x="612.60858"
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-           y="281.9234"
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+           y="289.13641"
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            id="tspan331"
            style="stroke-width:1"
-           y="295.25674"
-           x="28.828726"
+           y="302.46979"
+           x="32.222134"
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diff --git a/docs/projects/ad469x_evb/index.rst b/docs/projects/ad469x_evb/index.rst
index 2154c04bf6..2e54e0e740 100644
--- a/docs/projects/ad469x_evb/index.rst
+++ b/docs/projects/ad469x_evb/index.rst
@@ -7,8 +7,7 @@ Overview
 -------------------------------------------------------------------------------
 
 The AD469X HDL reference design provides all the interfaces that are
-necessary to interact with the devices on the :adi:`EVAL-AD4696 <EVAL-AD4696>`
-board.
+necessary to interact with the devices on the :adi:`EVAL-AD4696` board.
 
 The design has a SPI Engine instance to control and acquire data from the
 :adi:`AD4696` 16-bit precisions ADC, providing support to capture continuous
@@ -17,27 +16,27 @@ samples at maximum sampling rate. Currently the design supports the Zedboard.
 Supported boards
 -------------------------------------------------------------------------------
 
--  `EVAL-AD4692 <EVAL-AD4692>`
--  :adi:`EVAL-AD4696 <EVAL-AD4696>`
+- EVAL-AD4692
+- :adi:`EVAL-AD4696`
 
 Supported devices
 -------------------------------------------------------------------------------
 
--  `AD4691`
--  `AD4692`
--  `AD4693`
--  `AD4694`
--  :adi:`AD4695`
--  :adi:`AD4696`
--  :adi:`AD4697`
--  :adi:`AD4698`
+- AD4691
+- AD4692
+- AD4693
+- AD4694
+- :adi:`AD4695`
+- :adi:`AD4696`
+- :adi:`AD4697`
+- :adi:`AD4698`
 
 Supported carriers
 -------------------------------------------------------------------------------
 
--  :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot
--  :xilinx:`Cora Z7-07S <products/boards-and-kits/1-1qlaz7n.html>` Arduino shield connector
--  :intel:`DE10-Nano <content/www/us/en/developer/topic-technology/edge-5g/hardware/fpga-de10-nano.html>` Arduino shield connector
+- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot
+- :xilinx:`Cora Z7S <products/boards-and-kits/1-1qlaz7n.html>` on Arduino shield connector
+- :intel:`DE10-Nano <content/www/us/en/developer/topic-technology/edge-5g/hardware/fpga-de10-nano.html>` on Arduino shield connector
 
 Block design
 -------------------------------------------------------------------------------
@@ -51,14 +50,14 @@ signal of the device.
 CNV signal gating
 -------------------------------------------------------------------------------
 
-The AXI PWM GEN IP core is used to drive CNV when the SPI Engine is operating in
-Offload mode along with logic gates and a few extra signals to ensure proper
-control of the signal.
+The :git-hdl:`AXI PWM GEN <library/axi_pwm_gen>` IP core is used to drive CNV
+when the SPI Engine is operating in Offload mode along with logic gates and a
+few extra signals to ensure proper control of the signal.
 
-The AND gate has the DMA s_axis_xfer_req signal and the PWM signal as inputs.
+The AND gate has the DMA ``s_axis_xfer_req`` signal and the PWM signal as inputs.
 Since the PWM is free running, this gate is necessary to prevent the sequencer
 on the ADC from getting out of sync. When the DMA is unable to receive more
-data, the s_axis_xfer_req signal is driven low, blocking the PWM signal.
+data, the ``s_axis_xfer_req`` signal is driven low, blocking the PWM signal.
 
 Also, to exit conversion mode on the device, one extra pulse on the CNV pin is
 needed before sending the exit command, otherwise this command is ignored by the
@@ -77,30 +76,33 @@ Zedboard
 .. image:: ad469x_hdl_zed.svg
    :width: 800
    :align: center
-   :alt: AD469X_FMC block diagram
+   :alt: AD469X_EVB/Zedboard block diagram
 
-Coraz7s
+Cora Z7S
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 .. image:: ad469x_hdl_coraz7s.svg
    :width: 800
    :align: center
-   :alt: AD469X_FMC block diagram
+   :alt: AD469X_EVB/Cora block diagram
 
-De-10Nano
+DE10-Nano
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 .. image:: ad469x_hdl_de10nano.svg
    :width: 800
    :align: center
-   :alt: AD469X_FMC block diagram
+   :alt: AD469X_EVB/DE10-Nano block diagram
 
 Configuration modes
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-The SPI_4WIRE configuration parameter defines if CNV signal is linked to PWM or
-to SPI_CS to enable interfacing with a single 4-wire SPI port. By default it is
-set to 0. Depending on the required pin functionality, some hardware
+The ``SPI_4WIRE`` configuration parameter defines if CNV signal is linked to
+PWM or to SPI_CS to enable interfacing with a single 4-wire SPI port.
+
+By default, it is set to 0.
+
+Depending on the required pin functionality, some hardware
 modifications need to be done on the board and/or ``make`` command:
 
 In case we link CNV signal to PWM:
@@ -121,9 +123,9 @@ CPU/Memory interconnects addresses
 The addresses are dependent on the architecture of the FPGA, having an offset
 added to the base address from HDL(see more at :ref:`architecture`).
 
-======================  ===========
-Instance                Address
-======================  ===========
+======================  =================
+Instance                Zynq*/DE10-Nano**
+======================  =================
 axi_ad469x_dma*         0x44A3_0000
 spi_clkgen*             0x44A7_0000
 spi_ad469x_axi_regmap*  0x44A0_0000
@@ -131,13 +133,13 @@ ad469x_trigger_gen*     0x44B0_0000
 axi_dmac_0**            0x0002_0000
 axi_spi_engine_0**      0x0003_0000
 ad469x_trigger_gen **   0x0004_0000
-======================  ===========
+======================  =================
 
 .. admonition:: Legend
    :class: note
 
-   -   ``*`` instantiated only for Cora Z7S and Zed
-   -   ``**`` instantiated only for DE10-Nano
+   - ``*`` instantiated only for Cora Z7S and Zed
+   - ``**`` instantiated only for DE10-Nano
 
 I2C connections
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -170,9 +172,9 @@ I2C connections
 .. admonition:: Legend
    :class: note
 
-   -   ``*`` instantiated only for Zed
-   -   ``**`` instantiated only for Cora Z7S
-   -   ``***`` instantiated only for DE10-Nano
+   - ``*`` instantiated only for Zed
+   - ``**`` instantiated only for Cora Z7S
+   - ``***`` instantiated only for DE10-Nano
 
 SPI connections
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -195,7 +197,7 @@ GPIOs
 
 The Software GPIO number is calculated as follows:
 
--  Zynq-7000: if PS7 is used, then offset is 54
+- Zynq-7000: if PS7 is used, then offset is 54
 
 .. list-table::
    :widths: 25 25 25 25
@@ -222,7 +224,7 @@ The Software GPIO number is calculated as follows:
      - 34
      - 88
 
--  DE10-Nano: the offset is 32
+- DE10-Nano: the offset is 32
 
 .. list-table::
    :widths: 25 25 25 25
@@ -245,8 +247,8 @@ The Software GPIO number is calculated as follows:
      - 32
      - 0
 
-BSY_ALT_GP0 pin can be configured to function as a general-purpose input/output
-(GPIO), the threshold detection alert indicator, the busy indicator, or the
+``BSY_ALT_GP0`` pin can be configured to function as a GPIO pin,
+the threshold detection alert indicator, the busy indicator, or the
 second serial data output in dual-sdo MODE
 
 Interrupts
@@ -281,7 +283,6 @@ the HDL repository, and then build the project as follows:
 **Linux/Cygwin/WSL**
 
 .. code-block::
-   :linenos:
 
    user@analog:~$ cd hdl/projects/ad469x_evb/zed
    user@analog:~/hdl/projects/ad469x_evb/zed$ make SPI_4WIRE=0
@@ -305,17 +306,17 @@ Resources
 Hardware related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
--  Product datasheet:
+- Product datasheet:
 
-   -  :adi:`AD4695`/:adi:`AD4696`
-   -  :adi:`AD4697`/:adi:`AD4698`
+  - :adi:`AD4695`/:adi:`AD4696`
+  - :adi:`AD4697`/:adi:`AD4698`
 
--  `UG-1882, EVAL-AD4694FMCZ User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad4696fmcz-ug-1882.pdf>`__
+- `UG-1882, EVAL-AD4694FMCZ User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad4696fmcz-ug-1882.pdf>`__
 
 HDL related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
--  :git-hdl:`AD469X_FMC HDL project source code <projects/ad469x_fmc>`
+- :git-hdl:`AD469X_EVB HDL project source code <projects/ad469x_evb>`
 
 .. list-table::
    :widths: 30 35 35
@@ -325,53 +326,52 @@ HDL related
      - Source code link
      - Documentation link
    * - AXI_CLKGEN
-     - :git-hdl:`library/axi_dmac <library/axi_clkgen>`
-     - :ref:`here <axi_clkgen>`
+     - :git-hdl:`library/axi_dmac`
+     - :ref:`axi_clkgen`
    * - AXI_DMAC
-     - :git-hdl:`library/axi_dmac <library/axi_dmac>`
-     - :ref:`here <axi_dmac>`
+     - :git-hdl:`library/axi_dmac`
+     - :ref:`axi_dmac`
    * - AXI_HDMI_TX
-     - :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
-     - :ref:`here <axi_hdmi_tx>`
+     - :git-hdl:`library/axi_hdmi_tx`
+     - :ref:`axi_hdmi_tx`
    * - AXI_I2S_ADI
-     - :git-hdl:`library/axi_i2s_adi <library/axi_i2s_adi>`
+     - :git-hdl:`library/axi_i2s_adi`
      - ---
    * - AXI_PWM_GEN
-     - :git-hdl:`library/axi_pwm_gen <library/axi_pwm_gen>`
-     - :ref:`here <axi_pwm_gen>`
+     - :git-hdl:`library/axi_pwm_gen`
+     - :ref:`axi_pwm_gen`
    * - AXI_SPDIF_TX
-     - :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
+     - :git-hdl:`library/axi_spdif_tx`
      - ---
    * - AXI_SPI_ENGINE
-     - :git-hdl:`library/spi_engine/axi_spi_engine <library/spi_engine/axi_spi_engine>`
-     - :ref:`here <spi_engine axi>`
+     - :git-hdl:`library/spi_engine/axi_spi_engine`
+     - :ref:`spi_engine axi`
    * - AXI_SYSID
-     - :git-hdl:`library/axi_sysid <library/axi_sysid>`
-     - :ref:`here <axi_sysid>`
+     - :git-hdl:`library/axi_sysid`
+     - :ref:`axi_sysid`
    * - SPI_ENGINE_EXECUTION
-     - :git-hdl:`library/spi_engine/spi_engine_execution <library/spi_engine/spi_engine_execution>`
-     - :ref:`here <spi_engine execution>`
+     - :git-hdl:`library/spi_engine/spi_engine_execution`
+     - :ref:`spi_engine execution`
    * - SPI_ENGINE_INTERCONNECT
-     - :git-hdl:`library/spi_engine/spi_engine_interconnect <library/spi_engine/spi_engine_interconnect>`
-     - :ref:`here <spi_engine interconnect>`
+     - :git-hdl:`library/spi_engine/spi_engine_interconnect`
+     - :ref:`spi_engine interconnect`
    * - SPI_ENGINE_OFFLOAD
-     - :git-hdl:`library/spi_engine/spi_engine_offload <library/spi_engine/spi_engine_offload>`
-     - :ref:`here <spi_engine offload>`
+     - :git-hdl:`library/spi_engine/spi_engine_offload`
+     - :ref:`spi_engine offload`
    * - SYSID_ROM
-     - :git-hdl:`library/sysid_rom <library/sysid_rom>`
-     - :ref:`here <axi_sysid>`
+     - :git-hdl:`library/sysid_rom`
+     - :ref:`axi_sysid`
    * - UTIL_I2C_MIXER
-     - :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
-     - :ref:`here <spi_engine offload>`
+     - :git-hdl:`library/util_i2c_mixer`
+     - ---
 
--  :ref:`SPI Engine Framework documentation <spi_engine>`
+- :ref:`SPI Engine Framework documentation <spi_engine>`
 
 Software related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
--  :git-no-os:`AD469X_FMCZ No-OS project source code  <projects/ad469x_fmcz>`
-
--  :dokuwiki:`How to build No-OS <resources/no-os/build>`
+- :git-no-os:`AD469X_FMCZ no-OS driver source code <drivers/adc/ad469x>`
+- :git-no-os:`AD469X_FMCZ no-OS project source code <projects/ad469x_fmcz>`
 
 .. include:: ../common/more_information.rst