From 427768c063bbc1520e075bfe74aa04a04be393d4 Mon Sep 17 00:00:00 2001 From: Liviu Adace Date: Thu, 7 Dec 2023 14:39:07 +0200 Subject: [PATCH] ad4630: Fefactoring for AD463x, AD403x and ADAQ4224 Reduced the number of xdc files. Reduced the number of system_top files. Fixed *_fmc.txt files. Signed-off-by: Liviu Adace --- projects/ad4630_fmc/common/ad4630_fmc.txt | 20 -- projects/ad4630_fmc/common/ad463x_fmc.txt | 32 +-- .../{ad463x_adaq42xx_bd.tcl => ad4x3x_bd.tcl} | 89 ++++--- projects/ad4630_fmc/common/adaq42xx_fmc.txt | 24 +- projects/ad4630_fmc/zed/Makefile | 10 +- projects/ad4630_fmc/zed/system_bd.tcl | 4 +- projects/ad4630_fmc/zed/system_constr.tcl | 89 +++++++ ..._constr_adaq42xx.xdc => system_constr.xdc} | 43 ++-- .../ad4630_fmc/zed/system_constr_1sdi.xdc | 15 -- .../ad4630_fmc/zed/system_constr_2sdi.xdc | 18 -- .../ad4630_fmc/zed/system_constr_4sdi.xdc | 24 -- .../ad4630_fmc/zed/system_constr_8sdi.xdc | 36 --- .../ad4630_fmc/zed/system_constr_ad463x.xdc | 41 --- projects/ad4630_fmc/zed/system_project.tcl | 92 ++----- .../{system_top_adaq42xx.v => system_top.v} | 65 ++--- projects/ad4630_fmc/zed/system_top_ad463x.v | 241 ------------------ 16 files changed, 249 insertions(+), 594 deletions(-) delete mode 100644 projects/ad4630_fmc/common/ad4630_fmc.txt rename projects/ad4630_fmc/common/{ad463x_adaq42xx_bd.tcl => ad4x3x_bd.tcl} (73%) create mode 100644 projects/ad4630_fmc/zed/system_constr.tcl rename projects/ad4630_fmc/zed/{system_constr_adaq42xx.xdc => system_constr.xdc} (64%) delete mode 100644 projects/ad4630_fmc/zed/system_constr_1sdi.xdc delete mode 100644 projects/ad4630_fmc/zed/system_constr_2sdi.xdc delete mode 100644 projects/ad4630_fmc/zed/system_constr_4sdi.xdc delete mode 100644 projects/ad4630_fmc/zed/system_constr_8sdi.xdc delete mode 100644 projects/ad4630_fmc/zed/system_constr_ad463x.xdc rename projects/ad4630_fmc/zed/{system_top_adaq42xx.v => system_top.v} (82%) delete mode 100644 projects/ad4630_fmc/zed/system_top_ad463x.v diff --git a/projects/ad4630_fmc/common/ad4630_fmc.txt b/projects/ad4630_fmc/common/ad4630_fmc.txt deleted file mode 100644 index 20ff30789ca..00000000000 --- a/projects/ad4630_fmc/common/ad4630_fmc.txt +++ /dev/null @@ -1,20 +0,0 @@ -# ad4630 - -FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination - -G6 LA00_P_CC SCK_FMC ad463x_spi_sclk LVCMOS25 #N/A -G7 LA00_N_CC CS_FMC ad463x_spi_cs LVCMOS25 #N/A -G9 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A -G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A -H4 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A -H7 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A -H8 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A -H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A -H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A -D8 LA01_P_CC CNV_FMC ad463x_cnv LVCMOS25 #N/A -D9 LA01_N_CC RESET_FMC ad463x_resetn LVCMOS25 #N/A -D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A -D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A -D20 LA17_P_CC SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A -C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A -C22 LA18_P_CC BUSY_FMC ad463x_busy LVCMOS25 #N/A diff --git a/projects/ad4630_fmc/common/ad463x_fmc.txt b/projects/ad4630_fmc/common/ad463x_fmc.txt index 7a041348f5a..6a3227efe8f 100644 --- a/projects/ad4630_fmc/common/ad463x_fmc.txt +++ b/projects/ad4630_fmc/common/ad463x_fmc.txt @@ -1,21 +1,21 @@ FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination # ad463x -G06 LA00_CC_P SCLK_FMC ad463x_spi_sclk LVCMOS25 #N/A -G07 LA00_CC_N CS_FMC ad463x_spi_cs LVCMOS25 #N/A -C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A -H07 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A -H08 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A -G09 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A -G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A -H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A -H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A -D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A -D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A +G06 LA00_CC_P SCLK_FMC ad4x3x_spi_sclk LVCMOS25 #N/A +G07 LA00_CC_N CS_FMC ad4x3x_spi_cs LVCMOS25 #N/A +C11 LA06_N SDI_FMC ad4x3x_spi_sdo LVCMOS25 #N/A +H07 LA02_P SDO0_FMC ad4x3x_spi_sdi[0] LVCMOS25 #N/A +H08 LA02_N SDO1_FMC ad4x3x_spi_sdi[1] LVCMOS25 #N/A +G09 LA03_P SDO2_FMC ad4x3x_spi_sdi[2] LVCMOS25 #N/A +G10 LA03_N SDO3_FMC ad4x3x_spi_sdi[3] LVCMOS25 #N/A +H10 LA04_P SDO4_FMC ad4x3x_spi_sdi[4] LVCMOS25 #N/A +H11 LA04_N SDO5_FMC ad4x3x_spi_sdi[5] LVCMOS25 #N/A +D11 LA05_P SDO6_FMC ad4x3x_spi_sdi[6] LVCMOS25 #N/A +D12 LA05_N SDO7_FMC ad4x3x_spi_sdi[7] LVCMOS25 #N/A -D20 LA17_CC_p SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A -D09 LA01_CC_N RESET_FMC ad463x_resetn LVCMOS25 #N/A -D08 LA01_CC_P CNV_FMC ad463x_cnv LVCMOS25 #N/A -C22 LA18_CC_P BUSY_FMC ad463x_busy LVCMOS25 #N/A -H04 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A +D20 LA17_CC_p SCK_OUT_FMC ad4x3x_echo_sclk LVCMOS25 #N/A +D09 LA01_CC_N RESET_FMC ad4x3x_resetn LVCMOS25 #N/A +D08 LA01_CC_P CNV_FMC ad4x3x_cnv LVCMOS25 #N/A +C22 LA18_CC_P BUSY_FMC ad4x3x_busy LVCMOS25 #N/A +H04 CLK0_M2C_P CLK ad4x3x_ext_clk LVCMOS25 #N/A diff --git a/projects/ad4630_fmc/common/ad463x_adaq42xx_bd.tcl b/projects/ad4630_fmc/common/ad4x3x_bd.tcl similarity index 73% rename from projects/ad4630_fmc/common/ad463x_adaq42xx_bd.tcl rename to projects/ad4630_fmc/common/ad4x3x_bd.tcl index 29d378c65c4..ee317865811 100644 --- a/projects/ad4630_fmc/common/ad463x_adaq42xx_bd.tcl +++ b/projects/ad4630_fmc/common/ad4x3x_bd.tcl @@ -5,13 +5,13 @@ source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl # system level parameters -set AD463X_ADAQ42XX_N $ad_project_params(AD463X_ADAQ42XX_N) +set AD463X_AD403X_N $ad_project_params(AD463X_AD403X_N) set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE) set CLK_MODE $ad_project_params(CLK_MODE) set DDR_EN $ad_project_params(DDR_EN) -puts "build parameters: AD463X_ADAQ42XX_N: $AD463X_ADAQ42XX_N ; NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ;DDR_EN: $DDR_EN" +puts "build parameters: AD463X_AD403X_N: $AD463X_AD403X_N ; NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ;DDR_EN: $DDR_EN" # block design ports and interfaces # specify the CNV generator's reference clock frequency in MHz @@ -25,17 +25,17 @@ set adc_sampling_rate 1000000 # specify the MAX17687 and LT8608 SYNC signal frequency (400KHz) set max17687_sync_freq 400000 -#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad463x_adaq42xx_spi +#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad4x3x_spi -create_bd_port -dir O ad463x_adaq42xx_spi_sclk -create_bd_port -dir O ad463x_adaq42xx_spi_cs -create_bd_port -dir O ad463x_adaq42xx_spi_sdo -create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad463x_adaq42xx_spi_sdi +create_bd_port -dir O ad4x3x_spi_sclk +create_bd_port -dir O ad4x3x_spi_cs +create_bd_port -dir O ad4x3x_spi_sdo +create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad4x3x_spi_sdi -create_bd_port -dir I ad463x_adaq42xx_echo_sclk -create_bd_port -dir I ad463x_adaq42xx_busy -create_bd_port -dir O ad463x_adaq42xx_cnv -create_bd_port -dir I ad463x_adaq42xx_ext_clk +create_bd_port -dir I ad4x3x_echo_sclk +create_bd_port -dir I ad4x3x_busy +create_bd_port -dir O ad4x3x_cnv +create_bd_port -dir I ad4x3x_ext_clk create_bd_port -dir O max17687_sync_clk @@ -50,7 +50,7 @@ ad_connect spi_clk spi_clkgen/clk_0 # create a SPI Engine architecture -#spi_engine_create "spi_ad463x_adaq42xx" 32 1 1 $NUM_OF_SDI 0 1 +#spi_engine_create "spi_ad4x3x" 32 1 1 $NUM_OF_SDI 0 1 set data_width 32 set async_spi_clk 1 @@ -60,7 +60,7 @@ set num_sdo 1 set sdi_delay 1 set echo_sclk 1 -set hier_spi_engine spi_ad463x_adaq42xx +set hier_spi_engine spi_ad4x3x spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk @@ -92,18 +92,25 @@ ad_ip_parameter sync_generator CONFIG.PULSE_0_PERIOD $max17687_cycle ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17687_cycle) / 2))] ad_ip_instance spi_axis_reorder data_reorder -ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI +switch $AD463X_AD403X_N { + 0 { + ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES [expr $NUM_OF_SDI *2] + } + 1 { + ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI + } +} # dma to receive data stream -ad_ip_instance axi_dmac axi_ad463x_adaq42xx_dma -ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.DMA_TYPE_SRC 1 -ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.DMA_TYPE_DEST 0 -ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.CYCLIC 0 -ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.AXI_SLICE_DEST 1 -ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.AXI_SLICE_SRC 1 -ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.DMA_DATA_WIDTH_SRC 64 -ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +ad_ip_instance axi_dmac axi_ad4x3x_dma +ad_ip_parameter axi_ad4x3x_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_ad4x3x_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad4x3x_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad4x3x_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_ad4x3x_dma CONFIG.AXI_SLICE_SRC 1 +ad_ip_parameter axi_ad4x3x_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_ip_parameter axi_ad4x3x_dma CONFIG.DMA_DATA_WIDTH_DEST 64 # Trigger for SPI offload if {$CAPTURE_ZONE == 1} { @@ -112,7 +119,7 @@ if {$CAPTURE_ZONE == 1} { # is used for SDI latching switch $CLK_MODE { 0 { - ad_connect $hier_spi_engine/echo_sclk ad463x_adaq42xx_echo_sclk + ad_connect $hier_spi_engine/echo_sclk ad4x3x_echo_sclk } 1 - 2 { @@ -135,7 +142,7 @@ if {$CAPTURE_ZONE == 1} { ad_connect busy_capture/rst GND ad_connect $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn busy_sync/out_resetn - ad_connect ad463x_adaq42xx_busy busy_sync/in_bits + ad_connect ad4x3x_busy busy_sync/in_bits ad_connect busy_sync/out_bits busy_capture/signal_in ad_connect $hier_spi_engine/trigger busy_capture/signal_out ## SDI is latched by the SPIE execution module @@ -150,7 +157,7 @@ if {$CAPTURE_ZONE == 1} { ## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY # is used for SDI latching - ad_connect $hier_spi_engine/echo_sclk ad463x_adaq42xx_echo_sclk + ad_connect $hier_spi_engine/echo_sclk ad4x3x_echo_sclk switch $CLK_MODE { 0 { ## SDI is latched by the SPIE execution module @@ -164,9 +171,9 @@ if {$CAPTURE_ZONE == 1} { ad_ip_parameter data_capture CONFIG.NUM_OF_LANES $NUM_OF_SDI ad_connect spi_clk data_capture/clk - ad_connect ad463x_adaq42xx_spi_cs data_capture/csn - ad_connect ad463x_adaq42xx_busy data_capture/echo_sclk - ad_connect ad463x_adaq42xx_spi_sdi data_capture/data_in + ad_connect ad4x3x_spi_cs data_capture/csn + ad_connect ad4x3x_busy data_capture/echo_sclk + ad_connect ad4x3x_spi_sdi data_capture/data_in ad_connect data_capture/m_axis data_reorder/s_axis @@ -183,7 +190,7 @@ if {$CAPTURE_ZONE == 1} { exit 2 } -ad_connect ad463x_adaq42xx_cnv cnv_generator/pwm_1 +ad_connect ad4x3x_cnv cnv_generator/pwm_1 ad_connect max17687_sync_clk sync_generator/pwm_0 # clocks @@ -193,40 +200,40 @@ ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk ad_connect $sys_cpu_clk sync_generator/s_axi_aclk ad_connect spi_clk $hier_spi_engine/spi_clk ad_connect spi_clk data_reorder/axis_aclk -ad_connect spi_clk axi_ad463x_adaq42xx_dma/s_axis_aclk -ad_connect ad463x_adaq42xx_ext_clk cnv_generator/ext_clk -ad_connect ad463x_adaq42xx_ext_clk sync_generator/ext_clk +ad_connect spi_clk axi_ad4x3x_dma/s_axis_aclk +ad_connect ad4x3x_ext_clk cnv_generator/ext_clk +ad_connect ad4x3x_ext_clk sync_generator/ext_clk # resets ad_connect $sys_cpu_resetn cnv_generator/s_axi_aresetn ad_connect data_reorder/axis_aresetn VCC ad_connect $sys_cpu_resetn $hier_spi_engine/resetn -ad_connect $sys_cpu_resetn axi_ad463x_adaq42xx_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad4x3x_dma/m_dest_axi_aresetn # data path -ad_connect $hier_spi_engine/${hier_spi_engine}_execution/cs ad463x_adaq42xx_spi_cs -ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sclk ad463x_adaq42xx_spi_sclk -ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sdo ad463x_adaq42xx_spi_sdo -ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sdi ad463x_adaq42xx_spi_sdi +ad_connect $hier_spi_engine/${hier_spi_engine}_execution/cs ad4x3x_spi_cs +ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sclk ad4x3x_spi_sclk +ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sdo ad4x3x_spi_sdo +ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sdi ad4x3x_spi_sdi -ad_connect axi_ad463x_adaq42xx_dma/s_axis data_reorder/m_axis +ad_connect axi_ad4x3x_dma/s_axis data_reorder/m_axis # AXI memory mapped address space ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap ad_cpu_interconnect 0x44b00000 cnv_generator ad_cpu_interconnect 0x44c00000 sync_generator -ad_cpu_interconnect 0x44a30000 axi_ad463x_adaq42xx_dma +ad_cpu_interconnect 0x44a30000 axi_ad4x3x_dma ad_cpu_interconnect 0x44a70000 spi_clkgen # interrupts -ad_cpu_interrupt "ps-13" "mb-13" axi_ad463x_adaq42xx_dma/irq +ad_cpu_interrupt "ps-13" "mb-13" axi_ad4x3x_dma/irq ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq # interconnect to memory interface ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect sys_cpu_clk axi_ad463x_adaq42xx_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk axi_ad4x3x_dma/m_dest_axi diff --git a/projects/ad4630_fmc/common/adaq42xx_fmc.txt b/projects/ad4630_fmc/common/adaq42xx_fmc.txt index 40c764c109b..5e5d0128728 100644 --- a/projects/ad4630_fmc/common/adaq42xx_fmc.txt +++ b/projects/ad4630_fmc/common/adaq42xx_fmc.txt @@ -1,19 +1,19 @@ FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination # adaq42xx -G06 LA00_CC_P SCLK_FMC adaq42xx_spi_sclk LVCMOS25 #N/A -G07 LA00_CC_N CS_FMC adaq42xx_spi_cs LVCMOS25 #N/A -C11 LA06_N SDI_FMC adaq42xx_spi_sdo LVCMOS25 #N/A -H07 LA02_P SDO0_FMC adaq42xx_spi_sdi[0] LVCMOS25 #N/A -H08 LA02_N SDO1_FMC adaq42xx_spi_sdi[1] LVCMOS25 #N/A -G09 LA03_P SDO2_FMC adaq42xx_spi_sdi[2] LVCMOS25 #N/A -G10 LA03_N SDO3_FMC adaq42xx_spi_sdi[3] LVCMOS25 #N/A +G06 LA00_CC_P SCLK_FMC ad4x3x_spi_sclk LVCMOS25 #N/A +G07 LA00_CC_N CS_FMC ad4x3x_spi_cs LVCMOS25 #N/A +C11 LA06_N SDI_FMC ad4x3x_spi_sdo LVCMOS25 #N/A +H07 LA02_P SDO0_FMC ad4x3x_spi_sdi[0] LVCMOS25 #N/A +H08 LA02_N SDO1_FMC ad4x3x_spi_sdi[1] LVCMOS25 #N/A +G09 LA03_P SDO2_FMC ad4x3x_spi_sdi[2] LVCMOS25 #N/A +G10 LA03_N SDO3_FMC ad4x3x_spi_sdi[3] LVCMOS25 #N/A -D20 LA17_CC_p SCK_OUT_FMC adaq42xx_echo_sclk LVCMOS25 #N/A -D09 LA01_CC_N RESET_FMC adaq42xx_resetn LVCMOS25 #N/A -D08 LA01_CC_P CNV_FMC adaq42xx_cnv LVCMOS25 #N/A -C22 LA18_CC_P BUSY_FMC adaq42xx_busy LVCMOS25 #N/A -H04 CLK0_M2C_P CLK adaq42xx_ext_clk LVCMOS25 #N/A +D20 LA17_CC_p SCK_OUT_FMC ad4x3x_echo_sclk LVCMOS25 #N/A +D09 LA01_CC_N RESET_FMC ad4x3x_resetn LVCMOS25 #N/A +D08 LA01_CC_P CNV_FMC ad4x3x_cnv LVCMOS25 #N/A +C22 LA18_CC_P BUSY_FMC ad4x3x_busy LVCMOS25 #N/A +H04 CLK0_M2C_P CLK ad4x3x_ext_clk LVCMOS25 #N/A G12 LA08_P MUX_A0 adaq42xx_pgia_mux[0] LVCMOS25 #N/A G13 LA08_N MUX_A1 adaq42xx_pgia_mux[1] LVCMOS25 #N/A diff --git a/projects/ad4630_fmc/zed/Makefile b/projects/ad4630_fmc/zed/Makefile index 015cd959c86..03b0923a3eb 100644 --- a/projects/ad4630_fmc/zed/Makefile +++ b/projects/ad4630_fmc/zed/Makefile @@ -4,13 +4,11 @@ ## Auto-generated, do not modify! #################################################################################### -PROJECT_NAME := ad463x_adaq42xx_fmc_zed +PROJECT_NAME := ad4x3x_fmc_zed -M_DEPS += system_constr_8sdi.xdc -M_DEPS += system_constr_4sdi.xdc -M_DEPS += system_constr_2sdi.xdc -M_DEPS += system_constr_1sdi.xdc -M_DEPS += ../common/ad463x_adaq42xx_bd.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_constr.tcl +M_DEPS += ../common/ad4x3x_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl diff --git a/projects/ad4630_fmc/zed/system_bd.tcl b/projects/ad4630_fmc/zed/system_bd.tcl index 1caebb3d30e..4fae53e3477 100644 --- a/projects/ad4630_fmc/zed/system_bd.tcl +++ b/projects/ad4630_fmc/zed/system_bd.tcl @@ -7,12 +7,12 @@ source $ad_hdl_dir/projects/scripts/adi_pd.tcl source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl # add RTL source that will be instantiated in system_bd directly -adi_project_files ad463x_adaq42xx_fmc_zed [list \ +adi_project_files ad4x3x_fmc_zed [list \ "$ad_hdl_dir/library/common/ad_edge_detect.v" \ "$ad_hdl_dir/library/util_cdc/sync_bits.v" ] # block design -source ../common/ad463x_adaq42xx_bd.tcl +source ../common/ad4x3x_bd.tcl set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; diff --git a/projects/ad4630_fmc/zed/system_constr.tcl b/projects/ad4630_fmc/zed/system_constr.tcl new file mode 100644 index 00000000000..d8aa046b0fd --- /dev/null +++ b/projects/ad4630_fmc/zed/system_constr.tcl @@ -0,0 +1,89 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +if {![info exists AD463X_AD403X_N]} { + set AD463X_AD403X_N $::env(AD463X_AD403X_N) +} + +if {![info exists NUM_OF_SDI]} { + set NUM_OF_SDI $::env(NUM_OF_SDI) +} + +switch $AD463X_AD403X_N { + 1 { + + switch $NUM_OF_SDI { + 1 { + set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[0]}] ; ## H07 FMC-LA02_P + } + + 2 { + set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[0]}] ; ## H07 FMC-LA02_P + set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[1]}] ; ## G09 FMC-LA04_P + } + + 4 { + set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[0]}] ; ## H07 FMC-LA02_P + set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[1]}] ; ## H10 FMC-LA02_N + set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[2]}] ; ## G09 FMC-LA04_P + set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[3]}] ; ## G10 FMC-LA04_N + } + + 8 { + set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[0]}] ; ## H07 FMC-LA02_P + set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[1]}] ; ## H08 FMC-LA02_N + set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[2]}] ; ## G09 FMC-LA03_P + set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[3]}] ; ## G10 FMC-LA03_N + set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[4]}] ; ## H10 FMC-LA04_P + set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[5]}] ; ## H11 FMC-LA04_N + set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[6]}] ; ## D11 FMC-LA05_P + set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[7]}] ; ## D12 FMC-LA05_N + } + } + } + + 0 { + switch $NUM_OF_SDI { + 1 { + set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[0]}] ; ## H07 FMC-LA02_P + } + + 2 { + set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[0]}] ; ## H07 FMC-LA02_P + set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[1]}] ; ## H08 FMC-LA02_N + } + + 4 { + set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[0]}] ; ## H07 FMC-LA02_P + set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[1]}] ; ## H08 FMC-LA02_N + set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[2]}] ; ## G09 FMC-LA03_P + set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {ad4x3x_spi_sdi[3]}] ; ## G10 FMC-LA03_N + } + } + } +} + +# input delays for MISO lines (SDO for the device) +# data is latched on negative edge + +set tsetup 5.6 +set thold 1.6 + +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad4x3x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad4x3x_spi_sdi[0]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad4x3x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad4x3x_spi_sdi[1]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad4x3x_spi_sdi[2]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad4x3x_spi_sdi[2]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad4x3x_spi_sdi[3]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad4x3x_spi_sdi[3]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad4x3x_spi_sdi[4]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad4x3x_spi_sdi[4]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad4x3x_spi_sdi[5]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad4x3x_spi_sdi[5]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad4x3x_spi_sdi[6]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad4x3x_spi_sdi[6]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad4x3x_spi_sdi[7]] +set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad4x3x_spi_sdi[7]] diff --git a/projects/ad4630_fmc/zed/system_constr_adaq42xx.xdc b/projects/ad4630_fmc/zed/system_constr.xdc similarity index 64% rename from projects/ad4630_fmc/zed/system_constr_adaq42xx.xdc rename to projects/ad4630_fmc/zed/system_constr.xdc index 8c02fcb60dd..b9957287ebe 100644 --- a/projects/ad4630_fmc/zed/system_constr_adaq42xx.xdc +++ b/projects/ad4630_fmc/zed/system_constr.xdc @@ -3,46 +3,47 @@ ### SPDX short identifier: ADIBSD ############################################################################### -# adaq42xx_fmc SPI interface -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_adaq42xx_spi_sdo] ; ## C11 FMC-LA06_N -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_adaq42xx_spi_sclk] ; ## G06 FMC-LA00_CC_P -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_cs] ; ## G07 FMC-LA00_CC_N +# ad4x3x_fmc SPI interface +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad4x3x_spi_sdo] ; ## C11 FMC-LA06_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad4x3x_spi_sclk] ; ## G06 FMC-LA00_CC_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad4x3x_spi_cs] ; ## G07 FMC-LA00_CC_N -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_echo_sclk] ; ## D20 FMC-LA17_CC_P -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_resetn] ; ## D09 FMC-LA01_CC_N -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_busy] ; ## C22 FMC-LA18_CC_P -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_cnv] ; ## D08 FMC-LA01_CC_P -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_ext_clk] ; ## H04 FMC-CLK0_P +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad4x3x_echo_sclk] ; ## D20 FMC-LA17_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad4x3x_resetn] ; ## D09 FMC-LA01_CC_N +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad4x3x_busy] ; ## C22 FMC-LA18_CC_P +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad4x3x_cnv] ; ## D08 FMC-LA01_CC_P +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad4x3x_ext_clk] ; ## H04 FMC-CLK0_P -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports adaq42xx_pgia_mux[0]] ; ## G12 FMC-LA08_P -set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports adaq42xx_pgia_mux[1]] ; ## G13 FMC-LA08_N +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC-LA08_P +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC-LA08_N -set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P -set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC # external clock, that drives the CNV generator, must have a maximum 100 MHz frequency -create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_adaq42xx_ext_clk] +create_clock -period 10.000 -name cnv_ext_clk [get_ports ad4x3x_ext_clk] # SCLK echod clock, tuned to 80 MHz //, phase shifted with 30% (aprox. 4ns) -create_clock -period 12.500 -name ECHOSCLK_clk [get_ports ad463x_adaq42xx_echo_sclk] +create_clock -period 12.500 -name ECHOSCLK_clk [get_ports ad4x3x_echo_sclk] # rename auto-generated clock for SPIEngine to spi_clk - 160MHz # NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] # create a generated clock for SCLK - fSCLK=spi_clk/2 - 80MHz -create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports ad463x_adaq42xx_spi_sclk] +create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports ad4x3x_spi_sclk] # output delay for MOSI line (SDI for the device) # # tHSDI and tSSDI is 1.5ns -set_output_delay -clock [get_clocks SCLK_clk] -max 1.500 [get_ports ad463x_adaq42xx_spi_sdo] -set_output_delay -clock [get_clocks SCLK_clk] -min 1.500 [get_ports ad463x_adaq42xx_spi_sdo] +set_output_delay -clock [get_clocks SCLK_clk] -max 1.500 [get_ports ad4x3x_spi_sdo] +set_output_delay -clock [get_clocks SCLK_clk] -min 1.500 [get_ports ad4x3x_spi_sdo] # relax the SDO path to help closing timing at high frequencies set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 8 set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 7 -set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_adaq42xx_execution/inst/left_aligned_reg*] 8 -set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_adaq42xx_execution/inst/left_aligned_reg*] 7 +set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad4x3x_execution/inst/left_aligned_reg*] 8 +set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad4x3x_execution/inst/left_aligned_reg*] 7 + diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi.xdc deleted file mode 100644 index 626d3912dac..00000000000 --- a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc +++ /dev/null @@ -1,15 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi] ; ## H07 FMC-LA02_P - -# input delays for MISO lines (SDO for the device) -# data is latched on negative edge - -set tsetup 5.6 -set thold 1.4 - -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi] diff --git a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi.xdc deleted file mode 100644 index a263a636440..00000000000 --- a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc +++ /dev/null @@ -1,18 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[0]] ; ## H07 FMC-LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[1]] ; ## H08 FMC-LA02_N - -# input delays for MISO lines (SDO for the device) -# data is latched on negative edge - -set tsetup 5.6 -set thold 1.4 - -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[0]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[0]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[1]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[1]] diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi.xdc deleted file mode 100644 index cdcfe3bafd7..00000000000 --- a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc +++ /dev/null @@ -1,24 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_adaq42xx_spi_sdi[0]}] ; ## H07 FMC-LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_adaq42xx_spi_sdi[1]}] ; ## H10 FMC-LA02_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_adaq42xx_spi_sdi[2]}] ; ## G09 FMC-LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_adaq42xx_spi_sdi[3]}] ; ## G10 FMC-LA04_N - -# input delays for MISO lines (SDO for the device) -# data is latched on negative edge - -set tsetup 5.6 -set thold 1.4 - -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_adaq42xx_spi_sdi[0]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_adaq42xx_spi_sdi[0]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_adaq42xx_spi_sdi[1]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_adaq42xx_spi_sdi[1]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_adaq42xx_spi_sdi[2]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_adaq42xx_spi_sdi[2]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_adaq42xx_spi_sdi[3]}] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_adaq42xx_spi_sdi[3]}] diff --git a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc b/projects/ad4630_fmc/zed/system_constr_8sdi.xdc deleted file mode 100644 index 9633c102500..00000000000 --- a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc +++ /dev/null @@ -1,36 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[0]] ; ## H07 FMC-LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[1]] ; ## H08 FMC-LA02_N -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[2]] ; ## G09 FMC-LA03_P -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[3]] ; ## G10 FMC-LA03_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[4]] ; ## H10 FMC-LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[5]] ; ## H11 FMC-LA04_N -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[6]] ; ## D11 FMC-LA05_P -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_sdi[7]] ; ## D12 FMC-LA05_N - -# input delays for MISO lines (SDO for the device) -# data is latched on negative edge - -set tsetup 5.6 -set thold 1.6 - -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[0]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[0]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[1]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[1]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[2]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[2]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[3]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[3]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[4]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[4]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[5]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[5]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[6]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[6]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_adaq42xx_spi_sdi[7]] -set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_adaq42xx_spi_sdi[7]] diff --git a/projects/ad4630_fmc/zed/system_constr_ad463x.xdc b/projects/ad4630_fmc/zed/system_constr_ad463x.xdc deleted file mode 100644 index 599cae06276..00000000000 --- a/projects/ad4630_fmc/zed/system_constr_ad463x.xdc +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# ad463x_fmc SPI interface -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_adaq42xx_spi_sdo] ; ## C11 FMC-LA06_N -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_adaq42xx_spi_sclk] ; ## G06 FMC-LA00_CC_P -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_spi_cs] ; ## G07 FMC-LA00_CC_N - -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_echo_sclk] ; ## D20 FMC-LA17_CC_P -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_resetn] ; ## D09 FMC-LA01_CC_N -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_busy] ; ## C22 FMC-LA18_CC_P -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_cnv] ; ## D08 FMC-LA01_CC_P -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_adaq42xx_ext_clk] ; ## H04 FMC-CLK0_P - -# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency -create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_adaq42xx_ext_clk] - -# SCLK echod clock, tuned to 80 MHz //, phase shifted with 30% (aprox. 4ns) -create_clock -period 12.500 -name ECHOSCLK_clk [get_ports ad463x_adaq42xx_echo_sclk] - -# rename auto-generated clock for SPIEngine to spi_clk - 160MHz -# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk -create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] - -# create a generated clock for SCLK - fSCLK=spi_clk/2 - 80MHz -create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports ad463x_adaq42xx_spi_sclk] - -# output delay for MOSI line (SDI for the device) -# -# tHSDI and tSSDI is 1.5ns -set_output_delay -clock [get_clocks SCLK_clk] -max 1.500 [get_ports ad463x_adaq42xx_spi_sdo] -set_output_delay -clock [get_clocks SCLK_clk] -min 1.500 [get_ports ad463x_adaq42xx_spi_sdo] - -# relax the SDO path to help closing timing at high frequencies -set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 8 -set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] 7 - -set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_adaq42xx_execution/inst/left_aligned_reg*] 8 -set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_adaq42xx_execution/inst/left_aligned_reg*] 7 diff --git a/projects/ad4630_fmc/zed/system_project.tcl b/projects/ad4630_fmc/zed/system_project.tcl index eff1416ac46..a1790bb10bf 100644 --- a/projects/ad4630_fmc/zed/system_project.tcl +++ b/projects/ad4630_fmc/zed/system_project.tcl @@ -13,11 +13,16 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # How to use over-writable parameters from the environment: # # e.g. -# make AD463X_ADAQ42XX_N=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 +# make AD463X_AD403X_N=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 # # # Parameter description: # +# AD463X_AD403X_N: Chip identifier +# +# 0 - AD403x or ADAQ42xx +# 1 - AD463x +# # CLK_MODE : Clocking mode of the device's digital interface # # 0 - SPI Mode @@ -45,77 +50,24 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # # Example: # -# make AD463X_ADAQ42XX_N=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 CLK_MODE=0 DR_EN=0 +# make AD463X_AD403X_N=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 CLK_MODE=0 DDR_EN=0 # -set AD463X_ADAQ42XX_N [get_env_param AD463X_ADAQ42XX_N 1] - -adi_project ad463x_adaq42xx_fmc_zed 0 [list \ - AD463X_ADAQ42XX_N [get_env_param AD463X_ADAQ42XX_N 1] \ - CLK_MODE [get_env_param CLK_MODE 0] \ - NUM_OF_SDI [get_env_param NUM_OF_SDI 4] \ - CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \ - DDR_EN [get_env_param DDR_EN 0] ] - - -if {$AD463X_ADAQ42XX_N == 1} { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ - "system_constr_ad463x.xdc" \ - "system_top_ad463x.v" ] +set AD463X_AD403X_N [get_env_param AD463X_AD403X_N 1] - switch [get_env_param NUM_OF_SDI 4] { - 1 { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_1sdi.xdc" ] - } - 2 { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_2sdi.xdc" ] - } - 4 { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_4sdi.xdc" ] - } - 8 { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_8sdi.xdc" ] - } - default { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_2sdi.xdc" ] - } - } -} elseif {$AD463X_ADAQ42XX_N == 0} { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ - "system_constr_adaq42xx.xdc" \ - "system_top_adaq42xx.v" ] +adi_project ad4x3x_fmc_zed 0 [list \ + AD463X_AD403X_N [get_env_param AD463X_AD403X_N 1] \ + CLK_MODE [get_env_param CLK_MODE 0] \ + NUM_OF_SDI [get_env_param NUM_OF_SDI 4] \ + CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \ + DDR_EN [get_env_param DDR_EN 0] ] - switch [get_env_param NUM_OF_SDI 4] { - 1 { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_1sdi.xdc" ] - } - 2 { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_2sdi.xdc" ] - } - 4 { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_4sdi.xdc" ] - } - default { - adi_project_files ad463x_adaq42xx_fmc_zed [list \ - "system_constr_4sdi.xdc" ] - } - } -} else { - return -code error [format "ERROR: Invalid eval board type! ..."] -} +adi_project_files ad4x3x_fmc_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "system_constr.xdc" \ + "system_constr.tcl" \ + "system_top.v" ] -adi_project_run ad463x_adaq42xx_fmc_zed +adi_project_run ad4x3x_fmc_zed diff --git a/projects/ad4630_fmc/zed/system_top_adaq42xx.v b/projects/ad4630_fmc/zed/system_top.v similarity index 82% rename from projects/ad4630_fmc/zed/system_top_adaq42xx.v rename to projects/ad4630_fmc/zed/system_top.v index 315e308db95..13989768db8 100644 --- a/projects/ad4630_fmc/zed/system_top_adaq42xx.v +++ b/projects/ad4630_fmc/zed/system_top.v @@ -84,21 +84,21 @@ module system_top #( input otg_vbusoc, - // adaq42xx SPI configuration interface + // ad4x3x SPI configuration interface - input [NUM_OF_SDI-1:0] ad463x_adaq42xx_spi_sdi, - output ad463x_adaq42xx_spi_sdo, - output ad463x_adaq42xx_spi_sclk, - output ad463x_adaq42xx_spi_cs, + input [7:0] ad4x3x_spi_sdi, + output ad4x3x_spi_sdo, + output ad4x3x_spi_sclk, + output ad4x3x_spi_cs, - input ad463x_adaq42xx_echo_sclk, - input ad463x_adaq42xx_ext_clk, - output ad463x_adaq42xx_cnv, - input ad463x_adaq42xx_busy, - inout ad463x_adaq42xx_resetn, + input ad4x3x_echo_sclk, + input ad4x3x_ext_clk, + output ad4x3x_cnv, + input ad4x3x_busy, + inout ad4x3x_resetn, inout [ 1:0] adaq42xx_pgia_mux, - + inout max17687_rst, output max17687_en, output max17687_sync_clk @@ -116,7 +116,10 @@ module system_top #( wire [ 1:0] iic_mux_sda_i_s; wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; - wire ad463x_adaq42xx_echo_sclk_s; + wire [ 7-NUM_OF_SDI:0] sdi_nc; + wire ad4x3x_echo_sclk_s; + + assign sni_nc = 0; // instantiations @@ -128,7 +131,7 @@ module system_top #( ) i_ext_clk ( .rst (1'b0), .locked (), - .clk_in_p (ad463x_adaq42xx_ext_clk), + .clk_in_p (ad4x3x_ext_clk), .clk_in_n (1'b0), .clk (ext_clk_s)); @@ -137,19 +140,19 @@ module system_top #( ) i_echo_sclk ( .rst (1'b0), .locked (), - .clk_in_p (ad463x_adaq42xx_echo_sclk), + .clk_in_p (ad4x3x_echo_sclk), .clk_in_n (1'b0), - .clk (ad463x_adaq42xx_echo_sclk_s)); + .clk (ad4x3x_echo_sclk_s)); ad_iobuf #( - .DATA_WIDTH(3) - ) i_ad463x_adaq42xx_gpio_iobuf ( - .dio_t(gpio_t[34:32]), - .dio_i(gpio_o[34:32]), - .dio_o(gpio_i[34:32]), - .dio_p ({max17687_rst, // 35 - adaq42xx_pgia_mux, // 34:33 - ad463x_adaq42xx_resetn})); // 32 + .DATA_WIDTH(4) + ) i_ad4x3x_gpio_iobuf ( + .dio_t(gpio_t[35:32]), + .dio_i(gpio_o[35:32]), + .dio_o(gpio_i[35:32]), + .dio_p ({max17687_rst, // 35 + adaq42xx_pgia_mux, // 34:33 + ad4x3x_resetn})); // 32 ad_iobuf #( .DATA_WIDTH(32) @@ -236,14 +239,14 @@ module system_top #( .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), - .ad463x_adaq42xx_spi_sdo (ad463x_adaq42xx_spi_sdo), - .ad463x_adaq42xx_spi_sdi (ad463x_adaq42xx_spi_sdi), - .ad463x_adaq42xx_spi_cs (ad463x_adaq42xx_spi_cs), - .ad463x_adaq42xx_spi_sclk (ad463x_adaq42xx_spi_sclk), - .ad463x_adaq42xx_echo_sclk (ad463x_adaq42xx_echo_sclk_s), - .ad463x_adaq42xx_busy (ad463x_adaq42xx_busy), - .ad463x_adaq42xx_cnv (ad463x_adaq42xx_cnv), - .ad463x_adaq42xx_ext_clk (ext_clk_s), + .ad4x3x_spi_sdo (ad4x3x_spi_sdo), + .ad4x3x_spi_sdi ({sdi_nc,ad4x3x_spi_sdi}), + .ad4x3x_spi_cs (ad4x3x_spi_cs), + .ad4x3x_spi_sclk (ad4x3x_spi_sclk), + .ad4x3x_echo_sclk (ad4x3x_echo_sclk_s), + .ad4x3x_busy (ad4x3x_busy), + .ad4x3x_cnv (ad4x3x_cnv), + .ad4x3x_ext_clk (ext_clk_s), .max17687_sync_clk (max17687_sync_clk), .otg_vbusoc (otg_vbusoc), .spdif (spdif)); diff --git a/projects/ad4630_fmc/zed/system_top_ad463x.v b/projects/ad4630_fmc/zed/system_top_ad463x.v deleted file mode 100644 index 57be2140f0f..00000000000 --- a/projects/ad4630_fmc/zed/system_top_ad463x.v +++ /dev/null @@ -1,241 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top #( - parameter NUM_OF_SDI = 2 -) ( - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [31:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [15:0] hdmi_data, - - output spdif, - - output i2s_mclk, - output i2s_bclk, - output i2s_lrclk, - output i2s_sdata_out, - input i2s_sdata_in, - - inout iic_scl, - inout iic_sda, - inout [ 1:0] iic_mux_scl, - inout [ 1:0] iic_mux_sda, - - input otg_vbusoc, - - // ad463x_adaq42xx SPI configuration interface - - input [NUM_OF_SDI-1:0] ad463x_adaq42xx_spi_sdi, - output ad463x_adaq42xx_spi_sdo, - output ad463x_adaq42xx_spi_sclk, - output ad463x_adaq42xx_spi_cs, - - input ad463x_adaq42xx_echo_sclk, - input ad463x_adaq42xx_ext_clk, - output ad463x_adaq42xx_cnv, - input ad463x_adaq42xx_busy, - inout ad463x_adaq42xx_resetn -); - - // internal signals - - wire ext_clk_s; - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 1:0] iic_mux_scl_i_s; - wire [ 1:0] iic_mux_scl_o_s; - wire iic_mux_scl_t_s; - wire [ 1:0] iic_mux_sda_i_s; - wire [ 1:0] iic_mux_sda_o_s; - wire iic_mux_sda_t_s; - wire ad463x_adaq42xx_echo_sclk_s; - - // instantiations - - assign gpio_i[63:33] = 31'b0; - - ad_data_clk #( - .SINGLE_ENDED (1) - ) i_ext_clk ( - .rst (1'b0), - .locked (), - .clk_in_p (ad463x_adaq42xx_ext_clk), - .clk_in_n (1'b0), - .clk (ext_clk_s)); - - ad_data_clk #( - .SINGLE_ENDED (1) - ) i_echo_sclk ( - .rst (1'b0), - .locked (), - .clk_in_p (ad463x_adaq42xx_echo_sclk), - .clk_in_n (1'b0), - .clk (ad463x_adaq42xx_echo_sclk_s)); - - ad_iobuf #( - .DATA_WIDTH(1) - ) i_ad463x_adaq42xx_gpio_iobuf ( - .dio_t(gpio_t[32]), - .dio_i(gpio_o[32]), - .dio_o(gpio_i[32]), - .dio_p(ad463x_adaq42xx_resetn)); - - ad_iobuf #( - .DATA_WIDTH(32) - ) i_iobuf ( - .dio_t(gpio_t[31:0]), - .dio_i(gpio_o[31:0]), - .dio_o(gpio_i[31:0]), - .dio_p(gpio_bd)); - - ad_iobuf #( - .DATA_WIDTH(2) - ) i_iic_mux_scl ( - .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), - .dio_i(iic_mux_scl_o_s), - .dio_o(iic_mux_scl_i_s), - .dio_p(iic_mux_scl)); - - ad_iobuf #( - .DATA_WIDTH(2) - ) i_iic_mux_sda ( - .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), - .dio_i(iic_mux_sda_o_s), - .dio_o(iic_mux_sda_i_s), - .dio_p(iic_mux_sda)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_fmc_scl_io (iic_scl), - .iic_fmc_sda_io (iic_sda), - .iic_mux_scl_i (iic_mux_scl_i_s), - .iic_mux_scl_o (iic_mux_scl_o_s), - .iic_mux_scl_t (iic_mux_scl_t_s), - .iic_mux_sda_i (iic_mux_sda_i_s), - .iic_mux_sda_o (iic_mux_sda_o_s), - .iic_mux_sda_t (iic_mux_sda_t_s), - .spi0_clk_i (1'b0), - .spi0_clk_o (), - .spi0_csn_0_o (), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (1'b0), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (1'b0), - .spi1_sdo_o (), - .ad463x_adaq42xx_spi_sdo (ad463x_adaq42xx_spi_sdo), - .ad463x_adaq42xx_spi_sdi (ad463x_adaq42xx_spi_sdi), - .ad463x_adaq42xx_spi_cs (ad463x_adaq42xx_spi_cs), - .ad463x_adaq42xx_spi_sclk (ad463x_adaq42xx_spi_sclk), - .ad463x_adaq42xx_echo_sclk (ad463x_adaq42xx_echo_sclk_s), - .ad463x_adaq42xx_busy (ad463x_adaq42xx_busy), - .ad463x_adaq42xx_cnv (ad463x_adaq42xx_cnv), - .ad463x_adaq42xx_ext_clk (ext_clk_s), - .otg_vbusoc (otg_vbusoc), - .spdif (spdif)); - -endmodule