ad9081_fmca_ebz: common: versal_transceiver: Force progdiv_clk to float

The [rx/tx]_progdiv_clock was truncated if the lane rate was an integer.
So for a lane rate of '10', the ref clock calculated was 151.000
instead of 151.515.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>

Author: bluncan

projects/ad9081_fmca_ebz/common/versal_transceiver.tcl

@@ -215,8 +215,8 @@ proc create_versal_phy {
   puts "intf_cfg: ${intf_cfg}"
   puts "assymmetric_mode: ${asymmetric_mode}"
 
-  set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / ${clk_divider}]]
-  set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / ${clk_divider}]]
+  set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000.0 / ${clk_divider}]]
+  set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000.0 / ${clk_divider}]]
   set preset ${transceiver}-JESD204_64B66B
 
   if {$intf_cfg == "RX"} {