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jemfgeronimojemfgeronimo
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dc2677a: add initial design
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
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15 files changed

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‎library/Makefile

Lines changed: 5 additions & 5 deletions
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####################################################################################
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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################################################################################
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################################################################################
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## Copyright (C) 2018-2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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################################################################################
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################################################################################
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include ../quiet.mk
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‎library/axi_ltc235x/Makefile

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@@ -1,8 +1,8 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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###############################################################################
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## Copyright (C) 2018-2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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###############################################################################
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LIBRARY_NAME := axi_ltc235x
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‎library/axi_ltc235x/axi_ltc235x.v

Lines changed: 2 additions & 2 deletions
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@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
3-
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -43,7 +43,7 @@ module axi_ltc235x #(
4343
parameter FPGA_FAMILY = 0,
4444
parameter SPEED_GRADE = 0,
4545
parameter DEV_PACKAGE = 0,
46-
parameter [0:0] LVDS_CMOS_N = 0,
46+
parameter LVDS_CMOS_N = 0,
4747
parameter LANE_0_ENABLE = 1,
4848
parameter LANE_1_ENABLE = 1,
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parameter LANE_2_ENABLE = 1,

‎library/axi_ltc235x/axi_ltc235x_cmos.v

Lines changed: 76 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -92,83 +92,83 @@ module axi_ltc235x_cmos #(
9292

9393
// internal registers
9494

95-
reg busy_m1;
96-
reg busy_m2;
97-
reg busy_m3;
98-
99-
reg [ 4:0] scki_counter = 5'h0;
100-
reg [ 4:0] data_counter = 5'h0;
101-
102-
reg scki_i;
103-
reg scki_d;
104-
105-
reg [BW:0] adc_lane_0;
106-
reg [BW:0] adc_lane_1;
107-
reg [BW:0] adc_lane_2;
108-
reg [BW:0] adc_lane_3;
109-
reg [BW:0] adc_lane_4;
110-
reg [BW:0] adc_lane_5;
111-
reg [BW:0] adc_lane_6;
112-
reg [BW:0] adc_lane_7;
113-
114-
reg [BW:0] adc_data_init[7:0];
115-
reg [BW:0] adc_data_store[7:0];
116-
117-
reg [ 2:0] lane_0_ch = 3'd0;
118-
reg [ 2:0] lane_1_ch = 3'd0;
119-
reg [ 2:0] lane_2_ch = 3'd0;
120-
reg [ 2:0] lane_3_ch = 3'd0;
121-
reg [ 2:0] lane_4_ch = 3'd0;
122-
reg [ 2:0] lane_5_ch = 3'd0;
123-
reg [ 2:0] lane_6_ch = 3'd0;
124-
reg [ 2:0] lane_7_ch = 3'd0;
125-
126-
reg [ 3:0] adc_lane0_shift;
127-
reg [ 3:0] adc_lane1_shift;
128-
reg [ 3:0] adc_lane2_shift;
129-
reg [ 3:0] adc_lane3_shift;
130-
reg [ 3:0] adc_lane4_shift;
131-
reg [ 3:0] adc_lane5_shift;
132-
reg [ 3:0] adc_lane6_shift;
133-
reg [ 3:0] adc_lane7_shift;
134-
135-
reg [ 3:0] adc_lane0_shift_d;
136-
reg [ 3:0] adc_lane1_shift_d;
137-
reg [ 3:0] adc_lane2_shift_d;
138-
reg [ 3:0] adc_lane3_shift_d;
139-
reg [ 3:0] adc_lane4_shift_d;
140-
reg [ 3:0] adc_lane5_shift_d;
141-
reg [ 3:0] adc_lane6_shift_d;
142-
reg [ 3:0] adc_lane7_shift_d;
143-
144-
reg adc_valid_init;
145-
reg adc_valid_init_d;
146-
147-
reg [ 7:0] ch_data_lock = 8'hff;
148-
reg [ 7:0] ch_capture;
149-
reg [ 7:0] ch_captured;
150-
151-
reg scko_d;
152-
reg [7:0] sdo_d;
153-
154-
reg [ 4:0] sdi_index = 5'd23;
155-
156-
reg [23:0] softspan_next_int;
95+
reg busy_m1;
96+
reg busy_m2;
97+
reg busy_m3;
98+
99+
reg [ 4:0] scki_counter = 5'h0;
100+
reg [ 4:0] data_counter = 5'h0;
101+
102+
reg scki_i;
103+
reg scki_d;
104+
105+
reg [BW:0] adc_lane_0;
106+
reg [BW:0] adc_lane_1;
107+
reg [BW:0] adc_lane_2;
108+
reg [BW:0] adc_lane_3;
109+
reg [BW:0] adc_lane_4;
110+
reg [BW:0] adc_lane_5;
111+
reg [BW:0] adc_lane_6;
112+
reg [BW:0] adc_lane_7;
113+
114+
reg [BW:0] adc_data_init[7:0];
115+
reg [BW:0] adc_data_store[7:0];
116+
117+
reg [ 2:0] lane_0_ch = 3'd0;
118+
reg [ 2:0] lane_1_ch = 3'd0;
119+
reg [ 2:0] lane_2_ch = 3'd0;
120+
reg [ 2:0] lane_3_ch = 3'd0;
121+
reg [ 2:0] lane_4_ch = 3'd0;
122+
reg [ 2:0] lane_5_ch = 3'd0;
123+
reg [ 2:0] lane_6_ch = 3'd0;
124+
reg [ 2:0] lane_7_ch = 3'd0;
125+
126+
reg [ 3:0] adc_lane0_shift;
127+
reg [ 3:0] adc_lane1_shift;
128+
reg [ 3:0] adc_lane2_shift;
129+
reg [ 3:0] adc_lane3_shift;
130+
reg [ 3:0] adc_lane4_shift;
131+
reg [ 3:0] adc_lane5_shift;
132+
reg [ 3:0] adc_lane6_shift;
133+
reg [ 3:0] adc_lane7_shift;
134+
135+
reg [ 3:0] adc_lane0_shift_d;
136+
reg [ 3:0] adc_lane1_shift_d;
137+
reg [ 3:0] adc_lane2_shift_d;
138+
reg [ 3:0] adc_lane3_shift_d;
139+
reg [ 3:0] adc_lane4_shift_d;
140+
reg [ 3:0] adc_lane5_shift_d;
141+
reg [ 3:0] adc_lane6_shift_d;
142+
reg [ 3:0] adc_lane7_shift_d;
143+
144+
reg adc_valid_init;
145+
reg adc_valid_init_d;
146+
147+
reg [ 7:0] ch_data_lock = 8'hff;
148+
reg [ 7:0] ch_capture;
149+
reg [ 7:0] ch_captured;
150+
151+
reg scko_d;
152+
reg [ 7:0] sdo_d;
153+
154+
reg [ 4:0] sdi_index = 5'd23;
155+
156+
reg [23:0] softspan_next_int;
157157

158158
// internal wires
159159

160-
wire start_transfer_s;
160+
wire start_transfer_s;
161161

162-
wire scki_cnt_rst;
162+
wire scki_cnt_rst;
163163

164-
wire acquire_data;
164+
wire acquire_data;
165165

166-
wire [17:0] adc_data_raw_s [7:0];
167-
wire [31:0] adc_data_sign_s [7:0];
168-
wire [31:0] adc_data_zero_s [7:0];
169-
wire [31:0] adc_data_s [7:0];
170-
wire [ 2:0] adc_ch_id_s [7:0];
171-
wire [ 2:0] adc_softspan_s [7:0];
166+
wire [17:0] adc_data_raw_s [7:0];
167+
wire [31:0] adc_data_sign_s [7:0];
168+
wire [31:0] adc_data_zero_s [7:0];
169+
wire [31:0] adc_data_s [7:0];
170+
wire [ 2:0] adc_ch_id_s [7:0];
171+
wire [ 2:0] adc_softspan_s [7:0];
172172

173173
always @(posedge clk) begin
174174
if (rst == 1'b1) begin
@@ -188,7 +188,7 @@ module axi_ltc235x_cmos #(
188188
if (rst) begin
189189
scki_counter <= 5'h0;
190190
scki_i <= 1'b1;
191-
scki_d <= 1'b0;
191+
scki_d <= 1'b0;
192192
end else begin
193193
scki_d <= scki_i;
194194
if (acquire_data == 1'b0) begin
@@ -287,14 +287,9 @@ module axi_ltc235x_cmos #(
287287
end
288288
end
289289

290-
/*
291-
lane_X_ch - channel number that lane X has
292-
e.g., lane_0_ch = 2, means lane 0 has channel 2
293-
ch_data_lock[i] - locks channel i
294-
e.g., ch_data_lock[7] = 1, means data from channel 7 has already been
295-
sent to an active lane, channel 7 should now be locked.
296-
Don't acquire data if all channels are all already locked.
297-
*/
290+
// lane_x_ch - channel corresponds to which lane, e.g. lane_0_ch stores the current channel lane 0 has
291+
// ch_data_lock[i] - locks ch i, e.g. ch_data_lock[7] = 1 means data from channel 7 has already been sent to an active lane, channel 7 should now be locked
292+
// dont acquire data if all channels are all already locked
298293
always @(posedge clk) begin
299294
if (start_transfer_s) begin
300295
lane_0_ch <= 3'd0;

‎library/axi_ltc235x/axi_ltc235x_hw.tcl

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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ip
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package require qsys 14.0

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