Replace other master branch references to main

* README.md
* adi_regmap_xcvr.txt
* build_hdl.rst
* hdl_coding_guideline.rst
* data_offload/README.md

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

Author: IuliaCMoldovan

README.md

@@ -43,7 +43,7 @@ There is no free replacement for consulting services. If you have questions that
 
 ## Getting started
 
-This repository supports reference designs for different [Analog Devices boards](../master/projects) based on [Intel and Xilinx FPGA development boards](../master/projects/common) or standalone.
+This repository supports reference designs for different [Analog Devices boards](../main/projects) based on [Intel and Xilinx FPGA development boards](../main/projects/common) or standalone.
 
 ### Building documentation
 
@@ -95,12 +95,14 @@ more information.
 
   * If you want to use the most stable code base, always use the [latest release branch](https://github.com/analogdevicesinc/hdl/releases).
 
-  * If you want to use the greatest and latest, check out the [master branch](https://github.com/analogdevicesinc/hdl/tree/master).
+  * If you want to use the greatest and latest, check out the [main branch](https://github.com/analogdevicesinc/hdl/tree/main).
 
 ## Use already built files
 
-You can download already built files and use them as they are. They are available on [this link]( https://swdownloads.analog.com/cse/hdl_builds/master/latest_boot_partition.tar.gz).  
-The files are built from [master branch](https://github.com/analogdevicesinc/hdl/tree/master) whenever there are new commits in HDL or Linux repositories.  
+You can download already built files and use them as they are.
+For the main branch, they are available at the link inside [this document](https://swdownloads.analog.com/cse/boot_partition_files/main/latest_boot.txt). Keep in mind that the ones from the main branch are not stable all the time.
+We suggest using the latest release branch [2022_r2, here](https://swdownloads.analog.com/cse/boot_partition_files/2022_r2/latest_boot.txt).  
+The files are built from [main branch](https://github.com/analogdevicesinc/hdl/tree/main) whenever there are new commits in HDL or Linux repositories.  
 
 > :warning: Pay attention when using already built files, since they are not tested in HW!
 
@@ -114,14 +116,14 @@ terms.
 The user should read each of these license terms, and understand the
 freedoms and responsibilities that he or she has by using this source/core.
 
-See [LICENSE](../master/LICENSE) for more details. The separate license files
+See [LICENSE](../main/LICENSE) for more details. The separate license files
 cab be found here:
 
- * [LICENSE_ADIBSD](../master/LICENSE_ADIBSD)
+ * [LICENSE_ADIBSD](../main/LICENSE_ADIBSD)
 
- * [LICENSE_GPL2](../master/LICENSE_GPL2)
+ * [LICENSE_GPL2](../main/LICENSE_GPL2)
 
- * [LICENSE_LGPL](../master/LICENSE_LGPL)
+ * [LICENSE_LGPL](../main/LICENSE_LGPL)
 
 ## Comprehensive user guide
 

docs/regmap/adi_regmap_xcvr.txt

@@ -110,7 +110,7 @@ ENDFIELD
 REG
 0x0007
 FPGA_INFO
-FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
+FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
 ENDREG
 
 FIELD
@@ -198,7 +198,7 @@ FIELD
 [19:16]
 XCVR_TYPE[3:0]
 RO
-[[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl | Xilinx encoded values.]]
+[[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl | Xilinx encoded values.]]
 ENDFIELD
 
 FIELD

docs/user_guide/build_hdl.rst

@@ -31,8 +31,8 @@ HDL project from the repository:
    -  Starting with ``hdl_2021_r1`` release branch:
       :git-hdl:`scripts/adi_env.tcl`
    -  For ``hdl_2019_r2`` and older:
-      :git-hdl:`hdl/projects/scripts/adi_project_xilinx.tcl <projects/scripts/adi_project_xilinx.tcl>` for Vivado, and
-      :git-hdl:`hdl/projects/scripts/adi_project_intel.tcl <projects/scripts/adi_project_intel.tcl>` for Quartus.
+      :git-hdl:`hdl/projects/scripts/adi_project_xilinx.tcl <hdl_2019_r2:projects/scripts/adi_project_xilinx.tcl>` for Vivado, and
+      :git-hdl:`hdl/projects/scripts/adi_project_intel.tcl <hdl_2019_r2:projects/scripts/adi_project_intel.tcl>` for Quartus.
 
 #. Download the tools from the following links:
 
@@ -95,7 +95,7 @@ Setup the HDL repository
 -------------------------------------------------------------------------------
 These designs are built upon ADI's generic HDL reference designs framework.
 ADI does not distribute the bit/elf files of these projects so they
-must be built from the sources available :git-hdl:`here <master:/>`. To get
+must be built from the sources available :git-hdl:`here </>`. To get
 the source you must
 `clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
 the repository. This is the best method to get the sources. Here, we are
@@ -668,10 +668,10 @@ to use an unsupported version of tools.
    The easiest way is to check the `release
    notes <https://github.com/analogdevicesinc/hdl/releases>`__. You may
    also check out or browse the desired branch, and verify the tool version
-   in the base Tcl script
-   (`./hdl/projects/scripts/adi_project_xilinx.tcl <https://github.com/analogdevicesinc/hdl/blob/master/projects/scripts/adi_project_xilinx.tcl#L4>`__)
+   in the base Tcl script ./hdl/scripts/adi_env.tcl
+   (:git-hdl:`for Vivado version <scripts/adi_env.tcl#L18>`)
    or
-   (`./hdl/projects/scripts/adi_project_intel.tcl <https://github.com/analogdevicesinc/hdl/blob/master/projects/scripts/adi_project_intel.tcl#L5>`__),
+   (:git-hdl:`or for Quartus version <scripts/adi_env.tcl#L34>`),
    which build the projects.
 
 Environment

docs/user_guide/hdl_coding_guideline.rst

@@ -686,7 +686,7 @@ Annex 1 Verilog file format
    //
    //   2. An ADI specific BSD license, which can be found in the top level directory
    //      of this repository (LICENSE_ADIBSD), and also on-line at:
-   //      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+   //      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
    //      This will allow to generate bit files and not release the source code,
    //      as long as it attaches to an ADI device.
    //
@@ -783,7 +783,7 @@ Annex 2 VHDL file format
    --
    --   2. An ADI specific BSD license, which can be found in the top level directory
    --      of this repository (LICENSE_ADIBSD), and also on-line at:
-   --      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+   --      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
    --      This will allow to generate bit files and not release the source code,
    --      as long as it attaches to an ADI device.
    --

library/data_offload/README.md

@@ -256,7 +256,7 @@ A general frequency relationship of the above clocks are:
   CLKdma <= CLKddr <= CLKconverter
 ```
 
-The clock domain crossing should be handled by the [util_axis_fifo](https://github.com/analogdevicesinc/hdl/tree/master/library/util_axis_fifo) module.
+The clock domain crossing should be handled by the [util_axis_fifo](https://github.com/analogdevicesinc/hdl/tree/main/library/util_axis_fifo) module.
   * **TODO** : Make sure that we support both AXIS and FIFO
   * **TODO** : Add support for asymmetric aspect ratio.