From 642def504e9ed2fd8c9f4fd4e652e156b5bf0d43 Mon Sep 17 00:00:00 2001 From: Alexis Czezar Torreno Date: Thu, 12 Dec 2024 11:37:00 +0800 Subject: [PATCH] Edited files due to guideline check. Attempt 1 Signed-off-by: Alexis Czezar Torreno --- projects/ad353xr/coraz7s/system_constr.xdc | 2 +- projects/ad353xr/coraz7s/system_top.v | 7 +++---- projects/ad353xr/de10nano/system_constr.sdc | 2 +- projects/ad353xr/de10nano/system_project.tcl | 2 +- projects/ad353xr/de10nano/system_qsys.tcl | 2 +- projects/ad353xr/de10nano/system_top.v | 5 +---- projects/ad353xr/zed/system_constr.xdc | 2 +- projects/ad353xr/zed/system_top.v | 6 +++--- 8 files changed, 12 insertions(+), 16 deletions(-) diff --git a/projects/ad353xr/coraz7s/system_constr.xdc b/projects/ad353xr/coraz7s/system_constr.xdc index c021b9f3c2..2e6ef76530 100644 --- a/projects/ad353xr/coraz7s/system_constr.xdc +++ b/projects/ad353xr/coraz7s/system_constr.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad353xr/coraz7s/system_top.v b/projects/ad353xr/coraz7s/system_top.v index c0f78cc9f5..387ccd8c8d 100644 --- a/projects/ad353xr/coraz7s/system_top.v +++ b/projects/ad353xr/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -62,7 +62,7 @@ module system_top ( inout [ 1:0] btn, inout [ 5:0] led, - + inout iic_ard_scl, inout iic_ard_sda, @@ -152,6 +152,5 @@ module system_top ( .spi1_sdo_o(), .iic_ard_scl_io (iic_ard_scl), .iic_ard_sda_io (iic_ard_sda)); - -endmodule +endmodule diff --git a/projects/ad353xr/de10nano/system_constr.sdc b/projects/ad353xr/de10nano/system_constr.sdc index 49bde7f81f..7e13342108 100644 --- a/projects/ad353xr/de10nano/system_constr.sdc +++ b/projects/ad353xr/de10nano/system_constr.sdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad353xr/de10nano/system_project.tcl b/projects/ad353xr/de10nano/system_project.tcl index 48f6ef3028..9fe818dd6c 100644 --- a/projects/ad353xr/de10nano/system_project.tcl +++ b/projects/ad353xr/de10nano/system_project.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad353xr/de10nano/system_qsys.tcl b/projects/ad353xr/de10nano/system_qsys.tcl index f0c57de8df..0245f9377b 100644 --- a/projects/ad353xr/de10nano/system_qsys.tcl +++ b/projects/ad353xr/de10nano/system_qsys.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad353xr/de10nano/system_top.v b/projects/ad353xr/de10nano/system_top.v index 394152831d..c0c5e3d152 100644 --- a/projects/ad353xr/de10nano/system_top.v +++ b/projects/ad353xr/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -107,7 +107,6 @@ module system_top ( // additional control signals output dac_reset_n, output dac_ldac_n - ); // internal signals @@ -131,7 +130,6 @@ module system_top ( assign dac_reset_n = gpio_o[33]; assign dac_ldac_n = gpio_o[34]; - ALT_IOBUF scl_iobuf ( .i (1'b0), .oe (i2c0_out_clk), @@ -235,4 +233,3 @@ module system_top ( .axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data)); endmodule - diff --git a/projects/ad353xr/zed/system_constr.xdc b/projects/ad353xr/zed/system_constr.xdc index dcb73bf522..df212a1731 100644 --- a/projects/ad353xr/zed/system_constr.xdc +++ b/projects/ad353xr/zed/system_constr.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad353xr/zed/system_top.v b/projects/ad353xr/zed/system_top.v index d857477735..1b39d7456a 100644 --- a/projects/ad353xr/zed/system_top.v +++ b/projects/ad353xr/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -82,7 +82,7 @@ module system_top ( inout [ 1:0] iic_mux_sda, input otg_vbusoc, - + output dac_reset_n, output dac_ldac_n, @@ -105,7 +105,7 @@ module system_top ( wire iic_mux_sda_t_s; assign gpio_i[63:32] = gpio_o[63:32]; - + assign dac_reset_n = gpio_o[33]; assign dac_ldac_n = gpio_o[34];