diff --git a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt b/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt
index 9d7886eabe..38994e5ce3 100644
--- a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt
+++ b/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt
@@ -2,8 +2,8 @@ Pin            Port               Schematic_name     System_top_name        IOST
 
 # pulsar_adc_pmdz
 
-PMOD J5 [8]    PMOD JA [4]        SCK                pulsar_adc_spi_sclk    LVCMOS33    #N/A
-PMOD J5 [6]    PMOD JA [3]        SDO                pulsar_adc_spi_sdi     LVCMOS33    #N/A
-PMOD J5 [4]    PMOD JA [2]        SDI                pulsar_adc_spi_sdo     LVCMOS33    #N/A
-PMOD J5 [2]    PMOD JA [1]        CS                 pulsar_adc_spi_cs      LVCMOS33    #N/A
-PMOD J5 [1]    PMOD JA [7]        INT                pulsar_adc_spi_pd      LVCMOS33    #N/A
+4              PMOD_4             SCK                pulsar_adc_spi_sclk    LVCMOS33    #N/A
+3              PMOD_3             SDO                pulsar_adc_spi_sdi     LVCMOS33    #N/A
+2              PMOD_2             SDI                pulsar_adc_spi_sdo     LVCMOS33    #N/A
+1              PMOD_1             CS                 pulsar_adc_spi_cs      LVCMOS33    #N/A
+7              PMOD_7             INT                pulsar_adc_spi_pd      LVCMOS33    #N/A
diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc b/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc
index 14477eb84e..296ae97335 100644
--- a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc
+++ b/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc
@@ -4,12 +4,12 @@
 ###############################################################################
 
 # ad40xx_fmc SPI interface
-set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo]       ; ##  PMOD JA [2]
-set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdi]       ; ##  PMOD JA [3]
-set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sclk]      ; ##  PMOD JA [4]
-set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_cs]        ; ##  PMOD JA [1]
+set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo]       ; ##  PMOD JA_2
+set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdi]       ; ##  PMOD JA_3
+set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sclk]      ; ##  PMOD JA_4
+set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_cs]        ; ##  PMOD JA_1
 
-set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports pulsar_adc_spi_pd]                 ; ##  PMOD JA [7]
+set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports pulsar_adc_spi_pd]                 ; ##  PMOD JA_7
 
 # rename auto-generated clock for SPIEngine to spi_clk - 160MHz
 # NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk