From 67a92260966f4a1808329108042e94aba6334fbf Mon Sep 17 00:00:00 2001 From: Pop Ioan Daniel Date: Thu, 28 Nov 2024 16:22:54 +0200 Subject: [PATCH] docs: Update ad7616 documentation Signed-off-by: Pop Ioan Daniel --- docs/library/axi_ad7616/axi_ad7616.svg | 1139 +++++++++++++++++ docs/library/axi_ad7616/block_diagram.svg | 487 ------- docs/library/axi_ad7616/index.rst | 96 +- .../ad7616_sdz/ad7616_parallel_hdl.svg | 963 +++++++++----- .../projects/ad7616_sdz/ad7616_serial_hdl.svg | 108 +- docs/projects/ad7616_sdz/index.rst | 47 +- 6 files changed, 1895 insertions(+), 945 deletions(-) create mode 100644 docs/library/axi_ad7616/axi_ad7616.svg delete mode 100644 docs/library/axi_ad7616/block_diagram.svg diff --git a/docs/library/axi_ad7616/axi_ad7616.svg b/docs/library/axi_ad7616/axi_ad7616.svg new file mode 100644 index 00000000000..56ed59f84da --- /dev/null +++ b/docs/library/axi_ad7616/axi_ad7616.svg @@ -0,0 +1,1139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + DFMT + + Channel 0 + Channel 1 + ... + Channel 15 + + + + + + PARALLELINTERFACE + AXI_AD7616 + + + uP CHANNEL + + + + uP COMMON + + + + uP (AXI) + + + + ... + + + + DB_O + + BUSY + + + WR_N + + RD_N + + CS_N + DATA + + ADC_CONFIG + + + DB_I + DB_T + DATA_F + + TRIGGER + + + diff --git a/docs/library/axi_ad7616/block_diagram.svg b/docs/library/axi_ad7616/block_diagram.svg deleted file mode 100644 index b73c3a3951c..00000000000 --- a/docs/library/axi_ad7616/block_diagram.svg +++ /dev/null @@ -1,487 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - DB[15:0]WRn/RDn - - - - - INPUT - OUTPUT - - - - - - - - S_AXI_LITE - WR_FIFO - - REGISTERMAP - - - CONTROL  - PARALLEL INTERFACE - - BUSY - - burst_length - - - - - - - - 15:0 - adc_data - adc_valid - adc_sync - - diff --git a/docs/library/axi_ad7616/index.rst b/docs/library/axi_ad7616/index.rst index fc75470daee..6426cbc934c 100644 --- a/docs/library/axi_ad7616/index.rst +++ b/docs/library/axi_ad7616/index.rst @@ -11,6 +11,9 @@ FPGA. The core has a AXI Memory Map interface for configuration, supports the parallel data interface of the device, and has a simple FIFO interface for the DMAC. +More about the generic framework interfacing ADCs, that contains the +``up_adc_channel`` and ``up_adc_common modules``, can be read in :ref:`axi_adc`. + Files -------------------------------------------------------------------------------- @@ -21,15 +24,17 @@ Files - Description * - :git-hdl:`library/axi_ad7616/axi_ad7616.v` - Verilog source for the AXI AD7616. - * - :git-hdl:`library/axi_ad7616/axi_ad7616_control.v` - - Verilog source for the AXI AD7616 control. * - :git-hdl:`library/axi_ad7616/axi_ad7616_pif.v` - Verilog source for the AXI AD7616 parallel interface. + * - :git-hdl:`library/common/up_adc_common.v` + - Verilog source for the ADC Common regmap. + * - :git-hdl:`library/common/up_adc_channel.v` + - Verilog source for the ADC Channel regmap. Block Diagram -------------------------------------------------------------------------------- -.. image:: block_diagram.svg +.. image:: axi_ad7616.svg :alt: AXI AD7616 block diagram Configuration Parameters @@ -61,18 +66,93 @@ Interface - End of conversion signal * - adc_valid - Shows when a valid data is available on the bus - * - adc_data - - Data bus - * - adc_sync - - Shows the first valid beat on a sequence + * - adc_data_* + - Channel ADC data + * - adc_enable_* + - ADC enable signal for each channel + * - adc_clk + - ADC clock + * - adc_reset + - ADC reset + * - adc_dovf + - ADC data overflow signaling * - s_axi - Standard AXI Slave Memory Map interface Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel or PWM Generator. The following table presents the +base addresses of each instance, after that can be found the detailed +description of each generic register map. + +.. hdl-regmap:: + :name: COMMON + :no-type-info: + +.. hdl-regmap:: + :name: ADC_COMMON + :no-type-info: + .. hdl-regmap:: - :name: AXI_AD7616 + :name: ADC_CHANNEL + :no-type-info: + +Theory of operation +-------------------------------------------------------------------------------- + +The axi_ad7616 IP can be configured in various operation modes, this feature +being integrated in the device register map. Thus, to be able to configure the +operation mode and any other features available through the mentioned register +map, **adc_config_ctrl** signal, that is available in the *up_adc_common* +module, is used in this way: bit 1 - RD request to the device register map('b1), +bit 0 - WR request to the device register map('b1). Also, **adc_custom_control** +signal, that is available in the *up_adc_common* module, controls burst_length. + +Software Parallel Mode Channel Conversion Setting +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. wavedrom:: + + {signal: [ + {name: 'RESET_N', wave:'101................'}, + {name: 'CNVST', wave:'0....10..........1.'}, + {name: 'BUSY', wave:'0....1.0.........1.'}, + {name: 'CS_N', wave:'1.....01..........010101..............', "period" :0.5}, + {name: 'WR_N', wave:'1.....01..............01..............', "period" :0.5}, + {name: 'RD_N', wave:'1.................0101................', "period" :0.5}, + {name: 'DB[0:15]', wave:'z.....=.z.........=.=.=.z.........|.....', data: ['CHx',"A0","B0","CHy"], "period" :0.45} + ], + foot: {text: + ['tspan', 'CHx CONVERSION START'] + } + } + +Parallel Read Timing Diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. wavedrom:: + + {signal: [ + {name: 'CNVST', wave:'010..........10....'}, + {name: 'BUSY', wave:'0..1......0................1......0...', "period" :0.5}, + {name: 'CS_N', wave:'1..........0..1..0..1..............0..', "period" :0.5}, + {name: 'RD_N', wave:'1......................01........01................................01.', "period" :0.25}, + {name: 'DB[0:15]', wave:'z.....=.z=.z.......', data: ['CONVA',"CONVB","B0","CHy"], "period" :1,"phase":-0.1} + ] + } + +Parallel Write Timing Diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. wavedrom:: + + {signal: [ + {name: 'CNVST', wave:'0..........................1..0', "period" :0.5}, + {name: 'CS_N', wave:'1......0.....1.....0.....1.....', "period" :0.5}, + {name: 'WR_N', wave:'1......0...1.......0...1......', "period" :0.5,"phase":-0.5}, + {name: 'DB[0:15]', wave:'z..=.z.=.z.', data: ['WRITE REG 1',"WRITE REG 2","B0","CHy"], "period" :1.3,"phase":0.7} + ] + } + Software Support -------------------------------------------------------------------------------- diff --git a/docs/projects/ad7616_sdz/ad7616_parallel_hdl.svg b/docs/projects/ad7616_sdz/ad7616_parallel_hdl.svg index a1e53bcd12c..9ca134c8046 100644 --- a/docs/projects/ad7616_sdz/ad7616_parallel_hdl.svg +++ b/docs/projects/ad7616_sdz/ad7616_parallel_hdl.svg @@ -1,13 +1,13 @@ @@ -45,7 +45,7 @@ inkscape:connector-curvature="0" id="path2456" d="M 5.77,0 -2.88,5 V -5 Z" - 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- - AXI CLKGEN - spi_clk = 100MHz - - - - + style="display:inline;fill:none;fill-opacity:1;stroke:#3f4b55;stroke-width:1.98857;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:1.98857, 5.96574;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> AD7616_DMA + + + AD7616_PACK + sys_clk = 100MHz + id="tspan673-8-9"> sys_clk = 100MHz + + ... + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.8;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.67501;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:0.673913" /> + style="opacity:1;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.67501;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:0.673913" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:0.5506;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> @@ -1965,9 +2045,9 @@ inkscape:connector-curvature="0" id="path8426" d="M 406.04958,433.33004 H 404.6091" - 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+ style="display:inline;opacity:1;fill:none;fill-opacity:1;stroke:#3f4b55;stroke-width:1.90762;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:1.90762, 5.72286;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> sys_clk = 100MHz + id="tspan673"> sys_clk = 100MHz AXI PWM GEN - - AXI CLKGEN - spi_clk = 100MHz - - - - ` IP core +- the serial interface is controlled by the :ref:`SPI_Engine ` + Framework +- data is written into memory by a DMA (:ref:`axi_dmac core `) +- all the control pins of the device are driven by GPIOs Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -78,7 +80,7 @@ AD7616_SDZ parallel interface Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The SER_PAR_N configuration parameter defines the interface type (Serial or +The INTF configuration parameter defines the interface type (Serial or Parallel). By default it is set to 1. Depending on the required interface mode, some hardware modifications need to be done on the board and/or make command: @@ -86,13 +88,13 @@ In case of the **PARALLEL** interface: .. shell:: bash - $make SER_PAR_N=0 + $make INTF=0 In case of the **SERIAL** interface: .. shell:: bash - $make SER_PAR_N=1 + $make INTF=1 .. note:: @@ -129,7 +131,6 @@ added to the base address from HDL(see more at :ref:`architecture cpu-intercon-a Instance Zynq ======================== =========== axi_ad7616_dma 0x44A3_0000 -spi_clkgen 0x44A7_0000 ad7616_pwm_gen 0x44B0_0000 spi_ad7616_axi_regmap ** 0x44A0_0000 axi_ad7616 * 0x44A8_0000 @@ -138,8 +139,8 @@ axi_ad7616 * 0x44A8_0000 .. admonition:: Legend :class: note - - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) - - ``**`` instantiated only for SER_PAR_N=1 (serial interface) + - ``*`` instantiated only for INTF=0 (parallel interface) + - ``**`` instantiated only for INTF=1 (serial interface) I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -231,7 +232,7 @@ The Software GPIO number is calculated as follows: .. admonition:: Legend :class: note - - ``**`` instantiated only for SER_PAR_N=1 (serial interface) + - ``**`` instantiated only for INTF=1 (serial interface) Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -249,8 +250,8 @@ axi_ad7616 * 10 54 87 .. admonition:: Legend :class: note - - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) - - ``**`` instantiated only for SER_PAR_N=1 (serial interface) + - ``*`` instantiated only for INTF=0 (parallel interface) + - ``**`` instantiated only for INTF=1 (serial interface) Building the HDL project ------------------------------------------------------------------------------- @@ -268,18 +269,18 @@ the HDL repository, and then build the project as follows:. .. shell:: $cd hdl/projects/ad7616_sdz/zed - $make SER_PAR_N=0 + $make INTF=0 The result of the build, if parameters were used, will be in a folder named by the configuration used: if the following command was run -``make SER_PAR_N=0`` +``make INTF=0`` then the folder name will be: -``SERPARN0`` +``INTF0`` A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -291,7 +292,7 @@ Connections and hardware changes **The following hardware changes are required:** (**Please note:** Because of the **SDP-I-FMC** the level of the **VADJ** in - the carrier board needs to be set to **3.3V**. + the carrier board needs to be set to **3.3V**.) Depending on the required interface mode, some hardware modifications need to be done. @@ -326,9 +327,6 @@ HDL related * - AXI_AD7616 - :git-hdl:`library/axi_ad7616` * - :ref:`axi_ad7616` - * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen` - - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - :ref:`axi_dmac` @@ -364,13 +362,16 @@ HDL related - --- * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`axi_sysid` + - :ref:`here ` + * - UTIL_CPACK2 + - :git-hdl:`library/util_pack/util_cpack2` * + - :ref:`here ` .. admonition:: Legend :class: note - - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) - - ``**`` instantiated only for SER_PAR_N=1 (serial interface) + - ``*`` instantiated only for INTF=0 (parallel interface) + - ``**`` instantiated only for INTF=1 (serial interface) - :ref:`SPI Engine Framework documentation `