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ADD adaq42xx (#1209)
* ad4630_fmc: Initial version of ADAQ4224 w/ and w/o fully isolated power supply Signed-off-by: Liviu Adace <liviu.adace@analog.com> * docs:ad4630_fmc: Add documentation for ADAQ4224 Signed-off-by: Liviu Adace <liviu.adace@analog.com> --------- Signed-off-by: Liviu Adace <liviu.adace@analog.com>
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‎docs/projects/ad4630_fmc/adaq42xx_hdl_cm0_cz2_1.svg

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‎docs/projects/ad4630_fmc/adaq42xx_hdl_cm1_cz2_1.svg

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‎docs/projects/ad4630_fmc/index.rst

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@@ -37,6 +37,13 @@ integrates all critical power supply and reference bypass capacitors, reducing
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the footprint and system component count, and lessening sensitivity to board
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layout.
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The ADAQ4224 is a μModule® precision data acquisition (DAQ) signal chain
41+
solution that reduces the development cycle of a precision measurement system
42+
by transferring the signal chain design challenge of component selection,
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optimization, and layout from the designer to the device. With a guaranteed
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maximum ±TBD ppm INL and no missing codes at 24 bits, the ADAQ4224 achieves
45+
unparalleled precision from −40°C to +85°C.
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The HDL reference design for the :adi:`EVAL-AD4630_FMCZ` and
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:adi:`EVAL-AD4030_FMCZ` provides all the interfaces that are necessary to
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interact with the device using a Xilinx FPGA development board. The design has
@@ -61,13 +68,16 @@ Supported boards
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- :adi:`EVAL-AD4030-24FMCZ <EVAL-AD4030-24FMCZ>`
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- :adi:`EVAL-AD4630-16FMCZ <EVAL-AD4630-16FMCZ>`
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- :adi:`EVAL-AD4630-24FMCZ <EVAL-AD4630-24FMCZ>`
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- EVAL-ADAQ4224-FMCZ <EVAL-ADAQ4224>
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- EVAL-ISO-4224-FMCZ <EVAL-ISO-ADAQ4224>
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD4030-24`
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- :adi:`AD4630-16`
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- :adi:`AD4630-24`
80+
- ADAQ4224
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Supported carriers
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-------------------------------------------------------------------------------
@@ -121,6 +131,11 @@ where the two signals will have different frequencies.
121131
:align: center
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:alt: AD4630_FMC SPI mode - transfer zone 2 block diagram
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.. image:: adaq42xx_hdl_cm0_cz2_1.svg
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:width: 800
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:align: center
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:alt: ADAQ4224_FMC SPI mode - transfer zone 2 block diagram
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124139
Echo clock mode - transfer zone 2
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@@ -135,6 +150,11 @@ mode.
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:align: center
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:alt: AD4630_FMC Echo clock mode - transfer zone 2 block diagram
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.. image:: adaq42xx_hdl_cm1_cz2_1.svg
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:width: 800
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:align: center
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:alt: ADAQ4224_FMC Echo clock mode - transfer zone 2 block diagram
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138158
The design supports the following interface and clock modes both in SDR and DDR:
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================== ================== ================== ==================
@@ -176,8 +196,14 @@ spi_ad463x_axi_regmap 0x44A0_0000
176196
axi_ad463x_dma 0x44A3_0000
177197
spi_clkgen 0x44A7_0000
178198
cnv_generator 0x44B0_0000
199+
sync_generator* 0x44C0_0000
179200
======================== ===========
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202+
.. admonition:: Legend
203+
:class: note
204+
205+
- ``*`` instantiated, but only used for ADAQ4224 with isolated power supply
206+
181207
I2C connections
182208
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@@ -195,11 +221,21 @@ I2C connections
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- axi_iic_fmc
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- 0x4162_0000
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- ---
198-
* - PL
199-
- iic_main
200-
- axi_iic_main
201-
- 0x4160_0000
202-
- ---
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* -
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-
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-
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- 0x50
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- eeprom
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* -
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-
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-
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- 0x5F
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- temperature sensor *
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.. admonition:: Legend
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:class: note
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238+
- ``*`` Temperature Sensor HW Monitor is present only in ADAQ4224
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -240,7 +276,25 @@ The Software GPIO number is calculated as follows:
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- INOUT
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- 32
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- 86
243-
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* - adaq42xx_pgia_mux[0]*
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- INOUT
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- 33
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- 87
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* - adaq42xx_pgia_mux[1]*
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- INOUT
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- 34
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- 88
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* - max17687_rst**
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- INOUT
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- 35
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- 89
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.. admonition:: Legend
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:class: note
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295+
- ``*`` instantiated, but used for ADAQ4224 only
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- ``**`` instantiated, but used for ADAQ4224 with isolated power supply
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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‎docs/projects/index.rst

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@@ -19,7 +19,7 @@ Contents
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:maxdepth: 1
2020

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AD4134-FMC <ad4134_fmc/index>
22-
AD4630-FMC <ad4630_fmc/index>
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AD4630-FMC/AD4030-FMC/ADAQ4224-FMC <ad4630_fmc/index>
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AD469X-FMC <ad469x_fmc/index>
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AD5766-SDZ <ad5766_sdz/index>
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AD7134-FMC <ad7134_fmc/index>

‎projects/ad4630_fmc/common/ad4030_fmc.txt

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# ad4030
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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
4+
5+
G6 LA00_P_CC SCK_FMC ad463x_spi_sclk LVCMOS25 #N/A
6+
G7 LA00_N_CC CS_FMC ad463x_spi_cs LVCMOS25 #N/A
7+
G9 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A
8+
G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A
9+
H4 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A
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H7 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A
11+
H8 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A
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H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A
13+
H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A
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D8 LA01_P_CC CNV_FMC ad463x_cnv LVCMOS25 #N/A
15+
D9 LA01_N_CC RESET_FMC ad463x_resetn LVCMOS25 #N/A
16+
D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A
17+
D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A
18+
D20 LA17_P_CC SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A
19+
C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A
20+
C22 LA18_P_CC BUSY_FMC ad463x_busy LVCMOS25 #N/A

‎projects/ad4630_fmc/common/ad463x_bd.tcl

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@@ -21,6 +21,9 @@ set cnv_ref_clk 100
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# NOTE: this is a default value, software may or may not change this
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set adc_sampling_rate 1000000
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24+
# specify the MAX17687 and LT8608 SYNC signal frequency (400KHz)
25+
set max17687_sync_freq 400000
26+
2427
#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad463x_spi
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2629
create_bd_port -dir O ad463x_spi_sclk
@@ -34,6 +37,8 @@ create_bd_port -dir I ad463x_busy
3437
create_bd_port -dir O ad463x_cnv
3538
create_bd_port -dir I ad463x_ext_clk
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40+
create_bd_port -dir O max17687_sync_clk
41+
3742
## To support the 2MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz
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3944
ad_ip_instance axi_clkgen spi_clkgen
@@ -70,6 +75,9 @@ ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_3
7075
## CNV generator; the actual sample rate will be PULSE_PERIOD * (1/cnv_ref_clk)
7176
set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))]
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78+
## setup the pulse period for the MAX17687 and LT8608 SYNC signal
79+
set max17687_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $max17687_sync_freq))]
80+
7381
ad_ip_instance axi_pwm_gen cnv_generator
7482
ad_ip_parameter cnv_generator CONFIG.N_PWMS 2
7583
ad_ip_parameter cnv_generator CONFIG.PULSE_0_PERIOD $sampling_cycle
@@ -78,6 +86,11 @@ ad_ip_parameter cnv_generator CONFIG.PULSE_1_PERIOD $sampling_cycle
7886
ad_ip_parameter cnv_generator CONFIG.PULSE_1_WIDTH 1
7987
ad_ip_parameter cnv_generator CONFIG.PULSE_1_OFFSET 1
8088

89+
ad_ip_instance axi_pwm_gen sync_generator
90+
ad_ip_parameter sync_generator CONFIG.N_PWMS 1
91+
ad_ip_parameter sync_generator CONFIG.PULSE_0_PERIOD $max17687_cycle
92+
ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17687_cycle) / 2))]
93+
8194
ad_ip_instance spi_axis_reorder data_reorder
8295
ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI
8396

@@ -171,15 +184,18 @@ if {$CAPTURE_ZONE == 1} {
171184

172185
}
173186
ad_connect ad463x_cnv cnv_generator/pwm_1
187+
ad_connect max17687_sync_clk sync_generator/pwm_0
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175189
# clocks
176190

177191
ad_connect $sys_cpu_clk $hier_spi_engine/clk
178192
ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk
193+
ad_connect $sys_cpu_clk sync_generator/s_axi_aclk
179194
ad_connect spi_clk $hier_spi_engine/spi_clk
180195
ad_connect spi_clk data_reorder/axis_aclk
181196
ad_connect spi_clk axi_ad463x_dma/s_axis_aclk
182197
ad_connect ad463x_ext_clk cnv_generator/ext_clk
198+
ad_connect ad463x_ext_clk sync_generator/ext_clk
183199

184200
# resets
185201

@@ -201,6 +217,7 @@ ad_connect axi_ad463x_dma/s_axis data_reorder/m_axis
201217

202218
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
203219
ad_cpu_interconnect 0x44b00000 cnv_generator
220+
ad_cpu_interconnect 0x44c00000 sync_generator
204221
ad_cpu_interconnect 0x44a30000 axi_ad463x_dma
205222
ad_cpu_interconnect 0x44a70000 spi_clkgen
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‎projects/ad4630_fmc/common/adaq42xx_fmc.txt

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# adaq42xx
2+
3+
FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
4+
5+
G6 LA00_P_CC SCK_FMC ad463x_spi_sclk LVCMOS25 #N/A
6+
G7 LA00_N_CC CS_FMC ad463x_spi_cs LVCMOS25 #N/A
7+
G9 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A
8+
G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A
9+
H4 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A
10+
H7 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A
11+
H8 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A
12+
H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A
13+
H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A
14+
D8 LA01_P_CC CNV_FMC ad463x_cnv LVCMOS25 #N/A
15+
D9 LA01_N_CC RESET_FMC ad463x_resetn LVCMOS25 #N/A
16+
D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A
17+
D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A
18+
D20 LA17_P_CC SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A
19+
C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A
20+
C22 LA18_P_CC BUSY_FMC ad463x_busy LVCMOS25 #N/A
21+
22+
G12 LA08_P MUX_A0 adaq42xx_pgia_mux[0] LVCMOS25 #N/A
23+
G13 LA08_N MUX_A1 adaq42xx_pgia_mux[1] LVCMOS25 #N/A
24+
25+
H13 LA07_P RST max17687_rst LVCMOS25 #N/A
26+
H14 LA07_N EN max17687_en LVCMOS25 #N/A
27+
D21 LA17_CC_N SYNCFMC max17687_sync_clk LVCMOS25 #N/A

‎projects/ad4630_fmc/zed/README.md

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33

44
## Building the design
55

6-
The design supports almost all the digital interface modes of AD4630-24, a new
7-
bit stream should be generated each time when the targeted configuration changes.
6+
The design supports almost all the digital interface modes of AD463x, AD403x
7+
and adaq42xx a new bit stream should be generated each time when the targeted
8+
configuration changes.
89

910
Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR
1011
data capture and capture zone 2.
@@ -18,7 +19,16 @@ data capture and capture zone 2.
1819
| CAPTURE_ZONE | 1 - negedge of BUSY / 2 - next posedge of CNV |
1920
| DDR_EN | 0 - MISO runs on SDR / 1 - MISO runs on DDR |
2021

21-
**Example:** make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
22+
**Example:**
23+
make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
24+
make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
25+
make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
26+
make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
27+
make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
28+
make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
29+
make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1
30+
make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1
31+
make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1
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2333
## Documentation
2434

‎projects/ad4630_fmc/zed/system_constr.xdc

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@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -14,6 +14,13 @@ set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy]
1414
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LA01_CC_P
1515
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_CLK0_P
1616

17+
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC-LA08_P
18+
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC-LA08_N
19+
20+
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P
21+
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N
22+
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC
23+
1724
# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
1825
create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk]
1926

‎projects/ad4630_fmc/zed/system_top.v

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11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -95,7 +95,13 @@ module system_top #(
9595
input ad463x_ext_clk,
9696
output ad463x_cnv,
9797
input ad463x_busy,
98-
inout ad463x_resetn
98+
inout ad463x_resetn,
99+
100+
inout [ 1:0] adaq42xx_pgia_mux,
101+
102+
inout max17687_rst,
103+
output max17687_en,
104+
output max17687_sync_clk
99105
);
100106

101107
// internal signals
@@ -114,7 +120,8 @@ module system_top #(
114120

115121
// instantiations
116122

117-
assign gpio_i[63:33] = 31'b0;
123+
assign gpio_i[63:36] = 27'b0;
124+
assign max17687_en = 1'b1;
118125

119126
ad_data_clk #(
120127
.SINGLE_ENDED (1)
@@ -135,12 +142,14 @@ module system_top #(
135142
.clk (ad463x_echo_sclk_s));
136143

137144
ad_iobuf #(
138-
.DATA_WIDTH(1)
145+
.DATA_WIDTH(4)
139146
) i_ad463x_gpio_iobuf (
140-
.dio_t(gpio_t[32]),
141-
.dio_i(gpio_o[32]),
142-
.dio_o(gpio_i[32]),
143-
.dio_p(ad463x_resetn));
147+
.dio_t(gpio_t[35:32]),
148+
.dio_i(gpio_o[35:32]),
149+
.dio_o(gpio_i[35:32]),
150+
.dio_p ({max17687_rst, // 35
151+
adaq42xx_pgia_mux, // 34:33
152+
ad463x_resetn})); // 32
144153

145154
ad_iobuf #(
146155
.DATA_WIDTH(32)
@@ -235,6 +244,7 @@ module system_top #(
235244
.ad463x_busy (ad463x_busy),
236245
.ad463x_cnv (ad463x_cnv),
237246
.ad463x_ext_clk (ext_clk_s),
247+
.max17687_sync_clk (max17687_sync_clk),
238248
.otg_vbusoc (otg_vbusoc),
239249
.spdif (spdif));
240250

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