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projects/ad9265_fmc: Solved the requested changes
Updated the HDL project and the documentation. Reverted the changes used for debugging. Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
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‎docs/projects/ad9265_fmc/index.rst

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Clock scheme
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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There are 3 ways to configure the clock source for :adi:`AD9265` (some
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modification maybe necessary).
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There are 3 ways to configure the clock source for :adi:`AD9265`:
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- External passive clock (default)
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- Optional active clock path using the :adi:`AD9517`
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- Optional oscillator
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For more details, check :adi:`AD9265` schematic.
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref:`architecture`).
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Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT,
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some IPs are instatiated and some are not.
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Check-out the table below to find out the conditions.
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==================== ===============
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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THESE ARE JUST EXAMPLES!!!
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USE WHICHEVER FITS BEST YOUR CASE
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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- SPI 0
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- AD9517
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- 1
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* - PS
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- SPI 1
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- AD0000
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- 0
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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You have many ways of writing this table: as a list-table or really to draw
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it. Take a look in the .rst of this page to see how they're written and
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which suits best your case.
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.. list-table::
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:widths: 30 10 15 15
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:header-rows: 1
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository.
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Then go to the project location(**projects/ad9265_fmc/carrier**) and run the make command by
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typing in your command prompt(this example :adi:`ZC706``):
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Then go to the project location (**projects/ad9265_fmc/carrier**) and run the make command by
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typing in your command prompt(this example :xilinx:`ZC706`):
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**Linux/Cygwin/WSL**
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheets: :adi:`AD9265`
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- :dokuwiki:`Evaluating AD9434, user guide <resources/eval/ad9265-fmc-125ebz>`
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- :dokuwiki:`Evaluating AD9265, user guide <resources/eval/ad9265-fmc-125ebz>`
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Source code link
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- Documentation link
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* - AXI_AD9265
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- :git-hdl:`library/axi_ad9434 <library/axi_ad9265>`
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- :git-hdl:`library/axi_ad9265 <library/axi_ad9265>`
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- ---
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac <library/axi_dmac>`
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- :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_HDMI_TX
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- :git-hdl:`library/axi_hdmi_tx <library/axi_ad9434>`
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- :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_SPDIF_TX
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- :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`

‎projects/ad9265_fmc/common/ad9265_fmc.txt

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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
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# ad9265
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H4 CLK0_M2C_P DCO+_GLOBAL adc_clk_in_p LVDS_25 DIFF_TERM TRUE
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H5 CLK0_M2C_N DCO-_GLOBAL adc_clk_in_n LVDS_25 DIFF_TERM TRUE
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D14 LA09_P D0/1+ adc_data_in_p[0] LVDS_25 DIFF_TERM TRUE
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D15 LA09_N D0/1- adc_data_in_n[0] LVDS_25 DIFF_TERM TRUE
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C10 LA06_P D2/3+ adc_data_in_p[1] LVDS_25 DIFF_TERM TRUE
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C11 LA06_N D2/3- adc_data_in_n[1] LVDS_25 DIFF_TERM TRUE
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H13 LA07_P D4/5+ adc_data_in_p[2] LVDS_25 DIFF_TERM TRUE
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H14 LA07_N D4/5- adc_data_in_n[2] LVDS_25 DIFF_TERM TRUE
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G12 LA08_P D6/7+ adc_data_in_p[3] LVDS_25 DIFF_TERM TRUE
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G13 LA08_N D6/7- adc_data_in_n[3] LVDS_25 DIFF_TERM TRUE
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H10 LA04_P D8/9+ adc_data_in_p[4] LVDS_25 DIFF_TERM TRUE
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H11 LA04_N D8/9- adc_data_in_n[4] LVDS_25 DIFF_TERM TRUE
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D11 LA05_P D10/11+ adc_data_in_p[5] LVDS_25 DIFF_TERM TRUE
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D12 LA05_N D10/11- adc_data_in_n[5] LVDS_25 DIFF_TERM TRUE
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H7 LA02_P D12/13+ adc_data_in_p[6] LVDS_25 DIFF_TERM TRUE
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H8 LA02_N D12/13- adc_data_in_n[6] LVDS_25 DIFF_TERM TRUE
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G9 LA03_P D14/15+ adc_data_in_p[7] LVDS_25 DIFF_TERM TRUE
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G10 LA03_N D14/15- adc_data_in_n[7] LVDS_25 DIFF_TERM TRUE
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D8 LA01_CC_P OR+ adc_data_or_p LVDS_25 DIFF_TERM TRUE
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D9 LA01_CC_N OR- adc_data_or_n LVDS_25 DIFF_TERM TRUE
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# spi
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G36 LA33_P AD9517_CSB spi_csn_clk LVCMOS25 #N/A
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G37 LA33_N CSB spi_csn_adc LVCMOS25 #N/A
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H37 LA32_P SDIO spi_sdio LVCMOS25 #N/A
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H38 LA32_N SCLK spi_clk LVCMOS25 #N/A

‎projects/ad9265_fmc/zed/Makefile

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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################

‎projects/ad9265_fmc/zed/system_bd.tcl

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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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‎projects/ad9265_fmc/zed/system_constr.xdc

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###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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@@ -36,4 +36,4 @@ set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_clk]
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# clocks
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create_clock -name adc_clk -period 3.33 [get_ports adc_clk_in_p]
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create_clock -name adc_clk -period 3.33 [get_ports adc_clk_in_p] ;

‎projects/ad9265_fmc/zed/system_project.tcl

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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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‎projects/ad9265_fmc/zed/system_top.v

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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// internal signals
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wire [ 1:0] spi_csn; // not sure if it's necessearry
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wire spi_miso;
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wire spi_mosi;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire [ 2:0] spi0_csn;
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wire spi0_clk;
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wire spi0_mosi;

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