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projects: Update addr/irq with coraz7s axi_iic_ard
The axi_iic_ard is generally used to read the EVB EEPROM with Arduino uno form factor. IIC Changes: Project Old New IIC Subordinate ad4170_asdz ps-12, 44a4 ps-11, 4416 24AA32A ad57xx_ardz PS7 IIC ps-11, 4416 24AA32A pulsar_adc none ps-11, 4416 - ad719x_asdz none ps-11, 4416 - cn0579 ps-12, 44a4 ps-11, 4416 AD5696 cn0540 ps-12, 44a4 ps-11, 4416 LTC2606 cn0561 PS7 IIC ps-11, 4416 M24C02 IRQ index changes: ad4170_asdz * $hier_spi_engine 11 -> 12 ad57xx_ardz * ad57xx_dma 12 -> 13 * $hier_spi_engine 11 -> 12 cn0579 * cn0579_dma 13 -> 12 * axi_iic_ard 12 -> 11 cn0540 * $hier_spi_engine 11 -> 12 Signed-off-by: Jorge Marques <jorge.marques@analog.com>
1 parent e865b47 commit 8fdfd0f

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18 files changed

+43
-83
lines changed

18 files changed

+43
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lines changed

‎projects/ad4170_asdz/common/ad4170_asdz_bd.tcl

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
###############################################################################
55

66
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
7-
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ad4170
87

98
create_bd_port -dir I adc_data_ready
109

@@ -22,9 +21,6 @@ set hier_spi_engine spi_ad4170
2221

2322
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
2423

25-
ad_ip_instance axi_iic axi_ad4170_iic
26-
ad_connect iic_ad4170 axi_ad4170_iic/iic
27-
2824
# Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz)
2925

3026
ad_ip_instance axi_clkgen spi_clkgen
@@ -76,14 +72,12 @@ ad_connect sys_cpu_resetn axi_ad4170_dma/m_dest_axi_aresetn
7672

7773
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
7874
ad_cpu_interconnect 0x44a30000 axi_ad4170_dma
79-
ad_cpu_interconnect 0x44a40000 axi_ad4170_iic
8075
ad_cpu_interconnect 0x44a70000 spi_clkgen
8176

8277
# interrupts
8378

8479
ad_cpu_interrupt "ps-13" "mb-13" axi_ad4170_dma/irq
85-
ad_cpu_interrupt "ps-12" "mb-12" axi_ad4170_iic/iic2intc_irpt
86-
ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq
80+
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
8781

8882
# memory interconnects
8983

‎projects/ad4170_asdz/coraz7s/system_constr.xdc

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,9 +15,6 @@ set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33}
1515
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports ad4170_dig_aux[1]] ; ## CK_IO7
1616
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports ad4170_dig_aux[0]] ; ## CK_IO2
1717

18-
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_scl] ; ## CK_SCL
19-
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_sda] ; ## CK_SDA
20-
2118
# rename auto-generated clock for SPI Engine to spi_clk - 40MHz
2219
create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
2320

‎projects/ad4170_asdz/coraz7s/system_top.v

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,8 @@ module system_top (
6363
inout [1:0] btn,
6464
inout [5:0] led,
6565

66-
inout iic_eeprom_scl,
67-
inout iic_eeprom_sda,
66+
inout iic_ard_scl,
67+
inout iic_ard_sda,
6868

6969
// ad4170
7070
input ad4170_spi_miso,
@@ -141,8 +141,6 @@ module system_top (
141141
.adc_spi_cs (ad4170_spi_csn),
142142
.adc_spi_sclk (ad4170_spi_sclk),
143143
.adc_data_ready (ad4170_dig_aux[0]),
144-
.iic_ad4170_scl_io (iic_eeprom_scl),
145-
.iic_ad4170_sda_io (iic_eeprom_sda),
146144
.spi0_clk_i (1'b0),
147145
.spi0_clk_o (),
148146
.spi0_csn_0_o (),
@@ -160,6 +158,8 @@ module system_top (
160158
.spi1_csn_i (1'b1),
161159
.spi1_sdi_i (1'b0),
162160
.spi1_sdo_i (1'b0),
163-
.spi1_sdo_o());
161+
.spi1_sdo_o (),
162+
.iic_ard_scl_io (iic_ard_scl),
163+
.iic_ard_sda_io (iic_ard_sda));
164164

165165
endmodule

‎projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -71,8 +71,8 @@ ad_cpu_interconnect 0x44b10000 axi_ad57xx_clkgen
7171

7272
# interrupts
7373

74-
ad_cpu_interrupt "ps-12" "mb-12" ad57xx_dma/irq
75-
ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq
74+
ad_cpu_interrupt "ps-13" "mb-13" ad57xx_dma/irq
75+
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
7676

7777
# memory interconnects
7878

‎projects/ad57xx_ardz/coraz7s/system_bd.tcl

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
1313

1414
sysid_gen_sys_init_file
1515

16-
#the eval board requires an extra i2c channel for the coraz7s project
17-
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0_io
18-
19-
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 1
20-
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_I2C0_IO EMIO
21-
22-
ad_connect iic_0_io sys_ps7/IIC_0
23-
2416
source ../common/ad57xx_ardz_bd.tcl

‎projects/ad57xx_ardz/coraz7s/system_constr.xdc

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,6 @@
55

66
# ad57xx interface
77

8-
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_scl]
9-
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_sda]
10-
118
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_mosi]
129
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_miso]
1310
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_sclk]

‎projects/ad57xx_ardz/coraz7s/system_top.v

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -63,9 +63,10 @@ module system_top (
6363
inout [1:0] btn,
6464
inout [5:0] led,
6565

66+
inout iic_ard_scl,
67+
inout iic_ard_sda,
68+
6669
// ad57xx ardz
67-
inout ad57xx_ardz_scl,
68-
inout ad57xx_ardz_sda,
6970
input ad57xx_ardz_spi_miso,
7071
output ad57xx_ardz_spi_mosi,
7172
output ad57xx_ardz_spi_sclk,
@@ -137,8 +138,6 @@ module system_top (
137138
.gpio_i (gpio_i),
138139
.gpio_o (gpio_o),
139140
.gpio_t (gpio_t),
140-
.iic_0_io_scl_io (ad57xx_ardz_scl),
141-
.iic_0_io_sda_io (ad57xx_ardz_sda),
142141
.spi0_clk_i (1'b0),
143142
.spi0_clk_o (),
144143
.spi0_csn_0_o (),
@@ -157,6 +156,8 @@ module system_top (
157156
.spi1_sdi_i (1'b0),
158157
.spi1_sdo_i (1'b0),
159158
.spi1_sdo_o (),
159+
.iic_ard_scl_io (iic_ard_scl),
160+
.iic_ard_sda_io (iic_ard_sda),
160161
.ad57xx_spi_sdo (ad57xx_ardz_spi_mosi),
161162
.ad57xx_spi_sdo_t (),
162163
.ad57xx_spi_sdi (ad57xx_ardz_spi_miso),

‎projects/ad719x_asdz/coraz7s/system_top_pmod.v

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,9 @@ module system_top (
6060
inout fixed_io_ps_porb,
6161
inout fixed_io_ps_srstb,
6262

63+
inout iic_ard_scl,
64+
inout iic_ard_sda,
65+
6366
inout [ 1:0] btn,
6467
inout [ 5:0] led,
6568

@@ -142,6 +145,9 @@ module system_top (
142145
.spi0_sdo_i (1'b0),
143146
.spi0_sdo_o (adc_spi_mosi),
144147

148+
.iic_ard_scl_io (iic_ard_scl),
149+
.iic_ard_sda_io (iic_ard_sda),
150+
145151
.spi1_clk_i (1'b0),
146152
.spi1_clk_o (),
147153
.spi1_csn_0_o (),

‎projects/cn0540/common/cn0540_bd.tcl

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
###############################################################################
55

66
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
7-
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cn0540
87
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_mux
98
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux1
109
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux9
@@ -29,9 +28,6 @@ set hier_spi_engine spi_cn0540
2928

3029
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
3130

32-
ad_ip_instance axi_iic axi_iic_cn0540
33-
ad_connect iic_cn0540 axi_iic_cn0540/iic
34-
3531
# Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz)
3632

3733
ad_ip_instance axi_clkgen spi_clkgen
@@ -100,15 +96,13 @@ ad_connect xadc_in/Vaux15 xadc_vaux15
10096

10197
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
10298
ad_cpu_interconnect 0x44a30000 axi_cn0540_dma
103-
ad_cpu_interconnect 0x44a40000 axi_iic_cn0540
10499
ad_cpu_interconnect 0x44a50000 xadc_in
105100
ad_cpu_interconnect 0x44a70000 spi_clkgen
106101

107102
# interrupts
108103

109104
ad_cpu_interrupt "ps-13" "mb-13" axi_cn0540_dma/irq
110-
ad_cpu_interrupt "ps-12" "mb-12" axi_iic_cn0540/iic2intc_irpt
111-
ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq
105+
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
112106

113107
# memory interconnects
114108

‎projects/cn0540/coraz7s/system_constr.xdc

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,6 @@ set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33}
2525
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports cn0540_sync_in] ; ## CK_IO6
2626
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports cn0540_drdy] ; ## CK_IO2
2727

28-
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports cn0540_scl] ; ## CK_SCL
29-
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports cn0540_sda] ; ## CK_SDA
30-
3128
# rename auto-generated clock for SPI Engine to spi_clk - 80MHz
3229
create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
3330

‎projects/cn0540/coraz7s/system_top.v

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,9 @@ module system_top (
6363
inout [1:0] btn,
6464
inout [5:0] led,
6565

66+
inout iic_ard_scl,
67+
inout iic_ard_sda,
68+
6669
input cn0540_xadc_mux_p,
6770
input cn0540_xadc_mux_n,
6871
input cn0540_ck_an0_p,
@@ -78,9 +81,6 @@ module system_top (
7881
input cn0540_ck_an5_p,
7982
input cn0540_ck_an5_n,
8083

81-
inout cn0540_scl,
82-
inout cn0540_sda,
83-
8484
inout cn0540_shutdown,
8585
inout cn0540_reset_adc,
8686
inout cn0540_csb_aux,
@@ -173,8 +173,6 @@ module system_top (
173173
.adc_spi_cs (cn0540_spi_cs),
174174
.adc_spi_sclk (cn0540_spi_sclk),
175175
.adc_data_ready (cn0540_drdy),
176-
.iic_cn0540_scl_io (cn0540_scl),
177-
.iic_cn0540_sda_io (cn0540_sda),
178176
.spi0_clk_i (1'b0),
179177
.spi0_clk_o (),
180178
.spi0_csn_0_o (),
@@ -193,6 +191,8 @@ module system_top (
193191
.spi1_sdi_i (1'b0),
194192
.spi1_sdo_i (1'b0),
195193
.spi1_sdo_o(),
194+
.iic_ard_scl_io (iic_ard_scl),
195+
.iic_ard_sda_io (iic_ard_sda),
196196
.xadc_mux_v_p (cn0540_xadc_mux_p),
197197
.xadc_mux_v_n (cn0540_xadc_mux_n),
198198
.xadc_vaux1_v_p (cn0540_ck_an0_p),

‎projects/cn0561/coraz7s/system_bd.tcl

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -18,12 +18,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
1818

1919
sysid_gen_sys_init_file
2020

21-
#the eval board requires an extra i2c channel for the coraz7s project
22-
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0_io
23-
24-
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 1
25-
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_I2C0_IO EMIO
26-
27-
ad_connect iic_0_io sys_ps7/IIC_0
28-
2921
source ../common/cn0561_bd.tcl

‎projects/cn0561/coraz7s/system_constr.xdc

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,6 @@
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_scl]
7-
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_sda]
8-
96
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports cn0561_spi_sdi] ; ## FMC_LPC_LA03_P
107
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports cn0561_spi_sdo] ; ## FMC_LPC_LA04_N
118
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports cn0561_spi_sclk] ; ## FMC_LPC_LA01_P_CC

‎projects/cn0561/coraz7s/system_top.v

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,8 @@ module system_top (
6363
inout [1:0] btn,
6464
inout [5:0] led,
6565

66-
inout iic_scl,
67-
inout iic_sda,
66+
inout iic_ard_scl,
67+
inout iic_ard_sda,
6868

6969
// cn0561 SPI configuration interface
7070

@@ -142,8 +142,8 @@ module system_top (
142142
.gpio_i (gpio_i),
143143
.gpio_o (gpio_o),
144144
.gpio_t (gpio_t),
145-
.iic_0_io_scl_io (iic_scl),
146-
.iic_0_io_sda_io (iic_sda),
145+
.iic_ard_scl_io (iic_ard_scl),
146+
.iic_ard_sda_io (iic_ard_sda),
147147
.spi0_clk_i (cn0561_spi_sclk),
148148
.spi0_clk_o (cn0561_spi_sclk),
149149
.spi0_csn_0_o (cn0561_spi_cs),

‎projects/cn0579/common/cn0579_bd.tcl

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,18 +3,12 @@
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_dac
76
# ad7768-4 interface
87

98
create_bd_port -dir I clk_in
109
create_bd_port -dir I ready_in
1110
create_bd_port -dir I -from 7 -to 0 data_in
1211

13-
#dac iic
14-
15-
ad_ip_instance axi_iic axi_iic_dac
16-
ad_connect iic_dac axi_iic_dac/iic
17-
1812
# adc(cn0579-dma)
1913

2014
ad_ip_instance axi_dmac cn0579_dma
@@ -62,14 +56,12 @@ ad_connect cn0579_dma/sync cn0579_adc_pack/packed_sync
6256

6357
# interrupts
6458

65-
ad_cpu_interrupt "ps-13" "mb-13" cn0579_dma/irq
66-
ad_cpu_interrupt "ps-12" "mb-12" axi_iic_dac/iic2intc_irpt
59+
ad_cpu_interrupt "ps-12" "mb-12" cn0579_dma/irq
6760

6861
# cpu / memory interconnects
6962

7063
ad_cpu_interconnect 0x44a00000 axi_ad77684_adc
7164
ad_cpu_interconnect 0x44a30000 cn0579_dma
72-
ad_cpu_interconnect 0x44a40000 axi_iic_dac
7365

7466
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
7567
ad_mem_hp1_interconnect $sys_cpu_clk cn0579_dma/m_dest_axi

‎projects/cn0579/coraz7s/system_constr.xdc

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,6 @@
1818
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi ]; ## P12.7 IO11
1919
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso ]; ## P12.6 IO12
2020
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk ]; ## P12.5 IO13
21-
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports dac_i2c_scl]; ## P12.1 CK_SCL
22-
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports dac_i2c_sda]; ## P12.2 CK_SDA
2321

2422
set input_clock_period 30.51; # Period of input clock fMAX_DCLK=32.768MHz
2523
set hold_time 8.5;

‎projects/cn0579/coraz7s/system_top.v

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,9 @@ module system_top (
6262
inout [ 1:0] btn,
6363
inout [ 5:0] led,
6464

65+
inout iic_ard_scl,
66+
inout iic_ard_sda,
67+
6568
input clk_in,
6669
input ready_in,
6770
input [ 3:0] data_in,
@@ -71,12 +74,7 @@ module system_top (
7174
output spi_mosi,
7275
input spi_miso,
7376
output shutdown_n,
74-
output reset_n,
75-
76-
// dac i2c
77-
78-
inout dac_i2c_scl,
79-
inout dac_i2c_sda
77+
output reset_n
8078
);
8179

8280
// internal signals
@@ -112,8 +110,6 @@ module system_top (
112110
.clk_in (clk_in),
113111
.ready_in (ready_in),
114112
.data_in (data_in),
115-
.iic_dac_scl_io (dac_i2c_scl),
116-
.iic_dac_sda_io (dac_i2c_sda),
117113
.ddr_addr (ddr_addr),
118114
.ddr_ba (ddr_ba),
119115
.ddr_cas_n (ddr_cas_n),
@@ -155,6 +151,8 @@ module system_top (
155151
.spi1_csn_i (1'b1),
156152
.spi1_sdi_i (1'b0),
157153
.spi1_sdo_i (1'b0),
158-
.spi1_sdo_o ());
154+
.spi1_sdo_o (),
155+
.iic_ard_scl_io (iic_ard_scl),
156+
.iic_ard_sda_io (iic_ard_sda));
159157

160158
endmodule

‎projects/pulsar_adc/coraz7s/system_top.v

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,10 @@ module system_top (
6767
output pulsar_adc_spi_pd,
6868

6969
inout [ 1:0] btn,
70-
inout [ 5:0] led
70+
inout [ 5:0] led,
71+
72+
inout iic_ard_scl,
73+
inout iic_ard_sda
7174
);
7275

7376
// internal signals
@@ -148,6 +151,8 @@ module system_top (
148151
.spi1_sdi_i (1'b0),
149152
.spi1_sdo_i (1'b0),
150153
.spi1_sdo_o (),
154+
.iic_ard_scl_io (iic_ard_scl),
155+
.iic_ard_sda_io (iic_ard_sda),
151156
.pulsar_adc_spi_cs(pulsar_adc_spi_cs),
152157
.pulsar_adc_spi_sclk(pulsar_adc_spi_sclk),
153158
.pulsar_adc_spi_sdi(pulsar_adc_spi_sdi),

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