From 95dd69356877d3c657f8493d39b23347b3bbb7e7 Mon Sep 17 00:00:00 2001 From: caosjr Date: Wed, 18 Sep 2024 11:29:01 -0300 Subject: [PATCH] FIX: AD3552r doc some changes on the doc of the AD3552r Signed-off-by: --- docs/library/axi_ad3552r/index.rst | 57 ++++++++++++++------------ docs/regmap/adi_regmap_axi_ad3552r.txt | 2 +- projects/ad3542r_evb/Readme.md | 2 +- projects/ad35xxr_evb/Readme.md | 12 +++++- 4 files changed, 43 insertions(+), 30 deletions(-) diff --git a/docs/library/axi_ad3552r/index.rst b/docs/library/axi_ad3552r/index.rst index d18dfa000e..5bf5332d58 100644 --- a/docs/library/axi_ad3552r/index.rst +++ b/docs/library/axi_ad3552r/index.rst @@ -1,14 +1,17 @@ .. _axi_ad3552r: -AXI AD3552R +AXI AD35XXR ================================================================================ .. hdl-component-diagram:: + :path: library/axi_ad35xxr -The :git-hdl:`AXI AD3552R ` IP core -can be used to interface the :adi:`AD3552R`, a low drift, ultra-fast, 16-bit -accuracy, current output digital-to-analog converter (DAC) that can be -configured in multiple voltage span ranges. +The :git-hdl:`AXI AD3552R ` IP core can be used to +interface the :adi:`AD3552R`, a low drift, ultra-fast, 16-bit accuracy, current +output digital-to-analog converter (DAC) that can be configured in multiple +voltage span ranges. It also supports :adi:`AD3542R`, a low drift, dual channel, +ultra-fast, 12-/16-bit accuracy, voltage output digital-to-analog converter +(DAC) that can be configured in multiple voltage span ranges. Features -------------------------------------------------------------------------------- @@ -19,8 +22,8 @@ Features * 16b register read/write SDR/DDR * data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate) * selectable input source: DMA/ADC/TEST_RAMP -* data out clock(SCLK) has clk_in/8 frequency when the converter is configured and - clk_in/2 when the converter is in stream mode +* data out clock(SCLK) has clk_in/2 frequency for both configuration and streaming + mode * the IP reference clock (clk_in) can have a maximum frequency of 132MHz * the IP has multiple device synchronization capability when the DMA is set as an input data source @@ -33,19 +36,19 @@ Files * - Name - Description - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr.v` - Verilog source for the AXI AD3552R. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_channel.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_channel.v` - Verilog source for the AXI AD3552R channel. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_core.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_core.v` - Verilog source for the AXI AD3552R core. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if.v` - Verilog source for the AD3552R interface module. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if_tb.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if_tb.v` - Verilog source for the AD3552R interface module testbench. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if_tb` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if_tb` - Setup script for the AD3552R interface module testbench. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_ip.tcl` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_ip.tcl` - TCL script to generate the Vivado IP-integrator project. Block Diagram @@ -98,9 +101,9 @@ Interface * - valid_in_dma_sec - Valid from a secondary DMAC if synchronization is needed. * - external_sync - - External synchronization flag from another axi_ad3552r IP. + - External synchronization flag from another ad35xxr IP. * - sync_ext_device - - Start_sync external device to another axi_ad3552r IP. + - Start_sync external device to another ad35xxr IP. * - dac_sclk - Serial clock. * - dac_csn @@ -120,30 +123,31 @@ Detailed Architecture -------------------------------------------------------------------------------- .. image:: detailed_architecture.svg - :alt: AXI AD3552R detailed architecture + :alt: AXI AD3XXR detailed architecture Detailed Description -------------------------------------------------------------------------------- The top module instantiates: -* The axi_ad3552r interface module -* The axi_ad3552r core module +* The ad35xxr interface module +* The ad35xxr core module * The AXI handling interface -The axi_ad3552r_if has the state machine that controls the quad SPI interface. -The axi_ad3552r_core module instantiates 2 axi_ad3552r channel modules. +The axi_ad35xxr_if has the state machine that controls the SPI interface, +which can be Single SPI (Classic), Dual SPI, and Quad SPI. +The axi_ad35xxr_core module instantiates 2 ad35xxr channel modules. Register Map -------------------------------------------------------------------------------- -For the AXI_AD3552R control used registers from DAC Common are: +For the AXI_AD3XXR control used registers from DAC Common are: .. hdl-regmap:: :name: AXI_AD3552R_DAC_COMMON -For the AXI_AD3552R control used registers from DAC Channel are: +For the AXI_AD35XXR control used registers from DAC Channel are: .. hdl-regmap:: :name: AXI_AD3552R_DAC_CHANNEL @@ -165,7 +169,7 @@ For reference, all the register map templates are: Design Guidelines -------------------------------------------------------------------------------- -The control of the chip is done through the AXI_AD3552R IP. +The control of the chip is done through the AXI_AD35XXR IP. The *DAC interface* must be connected to an IO buffer. @@ -192,8 +196,9 @@ Software Support References -------------------------------------------------------------------------------- -* HDL IP core at :git-hdl:`library/axi_ad3552r` -* HDL project at :git-hdl:`projects/ad3552r_evb` +* HDL IP core at :git-hdl:`dev_ad3542r:library/axi_ad35xxr` +* HDL project at :git-hdl:`dev_ad3542r:projects/ad35xxr_evb` * :adi:`AD3552R` +* :adi:`AD3542R` * :xilinx:`Zynq-7000 SoC Overview ` * :xilinx:`Zynq-7000 SoC Packaging and Pinout ` diff --git a/docs/regmap/adi_regmap_axi_ad3552r.txt b/docs/regmap/adi_regmap_axi_ad3552r.txt index 0aeb64c59c..9acc0901b8 100644 --- a/docs/regmap/adi_regmap_axi_ad3552r.txt +++ b/docs/regmap/adi_regmap_axi_ad3552r.txt @@ -72,7 +72,7 @@ FIELD [3:2] 0x00000000 MULTI_IO_MODE RW -Controls the SPI mode (0: Single SPI, 1: Dual SPI). +Controls the SPI mode (0: Single SPI, 1: Dual SPI, 2: Quad SPI). ENDFIELD FIELD diff --git a/projects/ad3542r_evb/Readme.md b/projects/ad3542r_evb/Readme.md index a3cd8b3a25..32734cd341 100755 --- a/projects/ad3542r_evb/Readme.md +++ b/projects/ad3542r_evb/Readme.md @@ -2,7 +2,7 @@ Here are some pointers to help you: * [Board Product Page](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad3542r.html) - * Parts : [ AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/AD3542R.html) + * Parts : [ Dual Channel, 12-/16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/AD3542R.html) * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r * Linux Drivers: NA \ No newline at end of file diff --git a/projects/ad35xxr_evb/Readme.md b/projects/ad35xxr_evb/Readme.md index 4c92e827e6..a7205bbe84 100644 --- a/projects/ad35xxr_evb/Readme.md +++ b/projects/ad35xxr_evb/Readme.md @@ -1,8 +1,16 @@ -# AD3552R-EVB HDL Project +# AD35XXR-EVB HDL Project +# It supports both AD3552R and AD3542R Here are some pointers to help you: +* AD3552R: * [Board Product Page](https://www.analog.com/eval-ad3552r) * Parts : [ AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/ad3552r.html) * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed - * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-dac/axi-ad3552r \ No newline at end of file + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-dac/axi-ad3552r +* AD3442R: + * [Board Product Page](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad3542r.html) + * Parts : [ Dual Channel, 12-/16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/AD3542R.html) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r + * Linux Drivers: NA \ No newline at end of file