diff --git a/docs/projects/ad469x_evb/index.rst b/docs/projects/ad469x_evb/index.rst
index 1369f7cab3..2154c04bf6 100644
--- a/docs/projects/ad469x_evb/index.rst
+++ b/docs/projects/ad469x_evb/index.rst
@@ -71,19 +71,25 @@ Block diagram
 
 The data path and clock domains are depicted in the below diagram:
 
--  Zedboard
+Zedboard
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
 .. image:: ad469x_hdl_zed.svg
    :width: 800
    :align: center
    :alt: AD469X_FMC block diagram
 
--  Coraz7s
+Coraz7s
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
 .. image:: ad469x_hdl_coraz7s.svg
    :width: 800
    :align: center
    :alt: AD469X_FMC block diagram
 
--  De-10Nano
+De-10Nano
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
 .. image:: ad469x_hdl_de10nano.svg
    :width: 800
    :align: center
@@ -115,17 +121,17 @@ CPU/Memory interconnects addresses
 The addresses are dependent on the architecture of the FPGA, having an offset
 added to the base address from HDL(see more at :ref:`architecture`).
 
-=====================  ===========
-Instance               Address
-=====================  ===========
-axi_ad469x_dma*        0x44A3_0000
-spi_clkgen*            0x44A7_0000
-spi_ad469x_axi_regmap* 0x44A0_0000
-ad469x_trigger_gen*    0x44B0_0000
-axi_dmac_0**           0x0002_0000
-axi_spi_engine_0**     0x0003_0000
-ad469x_trigger_gen **  0x0004_0000
-=====================  ===========
+======================  ===========
+Instance                Address
+======================  ===========
+axi_ad469x_dma*         0x44A3_0000
+spi_clkgen*             0x44A7_0000
+spi_ad469x_axi_regmap*  0x44A0_0000
+ad469x_trigger_gen*     0x44B0_0000
+axi_dmac_0**            0x0002_0000
+axi_spi_engine_0**      0x0003_0000
+ad469x_trigger_gen **   0x0004_0000
+======================  ===========
 
 .. admonition:: Legend
    :class: note