From a85ebb9aae16dca40031a4b98bf8b48457a19f26 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Mon, 23 Oct 2023 19:22:21 +0300 Subject: [PATCH] ad9081: update clock schemes Signed-off-by: Iulia Moldovan --- docs/projects/ad9081_fmca_ebz/index.rst | 4 +- .../images/ad9081_clock_scheme_vcu118.svg | 958 ++++++++++++--- .../images/ad9081_clock_scheme_zcu102.svg | 1069 ++++++++++++++--- 3 files changed, 1679 insertions(+), 352 deletions(-) mode change 100755 => 100644 docs/projects/images/ad9081_clock_scheme_vcu118.svg mode change 100755 => 100644 docs/projects/images/ad9081_clock_scheme_zcu102.svg diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index 57afe97c1c..d33dc4c605 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -284,7 +284,7 @@ The clock sources depend on the carrier that is used: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .. image:: ../images/ad9081_clock_scheme_zcu102.svg - :width: 400 + :width: 800 :align: center :alt: AD9081-FMCA-EBZ ZCU102 clock scheme @@ -292,7 +292,7 @@ The clock sources depend on the carrier that is used: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .. image:: ../images/ad9081_clock_scheme_vcu118.svg - :width: 450 + :width: 800 :align: center :alt: AD9081-FMCA-EBZ VCU118 clock scheme diff --git a/docs/projects/images/ad9081_clock_scheme_vcu118.svg b/docs/projects/images/ad9081_clock_scheme_vcu118.svg old mode 100755 new mode 100644 index e8af394178..2eb8a7da89 --- a/docs/projects/images/ad9081_clock_scheme_vcu118.svg +++ b/docs/projects/images/ad9081_clock_scheme_vcu118.svg @@ -2,9 +2,9 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + units="mm" + scale-x="1" /> @@ -1697,39 +1840,31 @@ HMC_7044 - + x="47.822815" + y="-124.55183" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:8.14381px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke:none;stroke-width:0.465361px;stroke-opacity:1">HMC_7044 @@ -1747,57 +1882,143 @@ inkscape:export-xdpi="96" xml:space="preserve" style="font-style:normal;font-weight:normal;font-size:3.175px;line-height:0%;font-family:Arial;letter-spacing:0px;word-spacing:0px;display:inline;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.264583px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" - x="-3.55163" + x="-2.6747115" y="138.31087" id="text27277" transform="rotate(-90)">FPGA + + + + + H4,5 B20,21 + G2,3 + D4,5 + SYSREF + x="-28.494009" + y="-50.942856" + style="stroke-width:0.465361">SYSREF2 CLKOUT12(REFCLK) + id="tspan28155">CLKOUT12 @@ -1805,69 +2026,61 @@ inkscape:export-ydpi="96" inkscape:export-xdpi="96" xml:space="preserve" - style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:4.93607px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;display:inline;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.462758;shape-rendering:crispEdges;enable-background:new" - x="-98.996437" - y="-42.798512" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:4.96383px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;display:inline;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.465361;shape-rendering:crispEdges;enable-background:new" + x="-115.58714" + y="-50.005211" id="text28465" inkscape:export-filename="C:\src\ghdl\docs\block_diagrams\ad9208_dual_ebz\ad9208_vcu118_clocking.png">CLKOUT13(SYSREF2) + x="-115.58714" + y="-50.005211" + style="stroke-width:0.465361">CLKOUT13 CLKOUT6 - + x="-115.58714" + y="-74.056854" + style="stroke-width:0.465361">CLKOUT6 VCU118 AD9081-FMCA-EBZ + x="-76.376122" + y="-110.63258" + style="stroke-width:0.465361">AD9081-FMCA-EBZ @@ -1890,28 +2103,28 @@ REFCLK0 + id="tspan35996">ref_clkq0 REFCLK1 + x="74.090523" + y="-82.949844" + style="stroke-width:0.465357">ref_clkq1 + + rx_sysref + + tx_sysref VCU118 + x="-43.679028" + y="-20.709654" + style="stroke-width:0.407665">VCU118 + transform="matrix(1.5407849,0,0,1.5407849,-430.23042,141.44536)"> + transform="matrix(1.5407849,0,0,1.5407849,-430.23042,211.9944)"> + transform="matrix(1.5407849,0,0,1.5407849,-430.23042,176.71988)"> + transform="matrix(1.5407849,0,0,1.5407849,-430.23042,138.18403)"> @@ -2112,7 +2369,7 @@ + transform="matrix(1.5407849,0,0,1.5407849,-430.03965,145.56972)"> + d="m -131.58547,70.152809 h 51.594025" + style="fill:none;stroke:#000000;stroke-width:0.407665px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> CLKOUT12(REFCLK) + x="-130.60114" + y="67.75795" + style="stroke-width:0.407665">CLKOUT12(REFCLK) CLKOUT6 DEVICE_CLK RX/TX0 RX/TX1 + x="-34.913147" + y="37.559982" + style="stroke-width:0.407665">RX/TX1 TX_DEVICE_CLK + id="tspan6705-1">CLKIN6 CLKOUT8 RX_DEVICE_CLK + x="-28.491961" + y="-63.197697" + style="stroke-width:0.465361">CLKIN8 + SYSREF2 + CLKOUT_8 + CLKOUT_6 + FPGA_REFCLK + FPGA_REFCLK_IN + FMC + + + clkin6 + fpga_refclk_in + + tx_device_clk + + clkin8 + rx_device_clk + + sysref2 + GBTCLK0_M2C + MGTREFCLK0P_121 + CLK1_M2C + GBTCLK1_M2C + CLK0_M2C + IO_L14P_T2L_N2_GC_45 + MGTREFCLK1P_120 + IO_L13P_T2L_N0_GC_QBC_43 + MGTREFCLK0P_126 + MGTREFCLK0P_121 + + diff --git a/docs/projects/images/ad9081_clock_scheme_zcu102.svg b/docs/projects/images/ad9081_clock_scheme_zcu102.svg old mode 100755 new mode 100644 index 6e9746b7da..3af9abd636 --- a/docs/projects/images/ad9081_clock_scheme_zcu102.svg +++ b/docs/projects/images/ad9081_clock_scheme_zcu102.svg @@ -2,9 +2,9 @@ + + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + units="mm" + scale-x="1"> + + @@ -1663,201 +1855,585 @@ ry="0.25573522" /> + style="display:inline;opacity:1;vector-effect:none;fill:#aaccee;fill-opacity:1;fill-rule:nonzero;stroke:#003366;stroke-width:0.594305;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;marker:none;shape-rendering:crispEdges;enable-background:new" + id="rect17734" + width="50.386124" + height="65.040627" + x="-138.78259" + y="-96.181931" + inkscape:export-filename="C:\src\ghdl\docs\block_diagrams\ad9208_dual_ebz\ad9208_vcu118_clocking.png" /> HMC_7044 + xml:space="preserve" + style="font-style:normal;font-weight:normal;font-size:5.58431px;line-height:0%;font-family:Arial;letter-spacing:0px;word-spacing:0px;display:inline;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.465361px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + x="45.203575" + y="-124.926" + id="text17738" + transform="rotate(-90)" + inkscape:export-filename="C:\src\ghdl\docs\block_diagrams\ad9208_dual_ebz\ad9208_vcu118_clocking.png">HMC_7044 + inkscape:export-ydpi="96" + inkscape:export-filename="C:\src\ghdl\docs\block_diagrams\ad9208_dual_ebz\ad9208_vcu118_clocking.png"> + style="display:inline;opacity:1;vector-effect:none;fill:#aaccee;fill-opacity:1;fill-rule:nonzero;stroke:#003366;stroke-width:0.264583;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;marker:none;shape-rendering:crispEdges;enable-background:new" + id="rect17740" + width="12.806378" + height="51.96344" + x="130.34352" + y="-30.454613" /> FPGA + + + + FPGA + y="138.31087" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.63021px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke:none;stroke-width:0.264583px;stroke-opacity:1" /> H4,5 + SYSREF + id="tspan6705-1-3-9-0-1-8">G6,7 + G2,3 + D4,5 + SYSREF2 + + inkscape:export-ydpi="96" + inkscape:export-filename="C:\src\ghdl\docs\block_diagrams\ad9208_dual_ebz\ad9208_vcu118_clocking.png">CLKOUT12 + + CLKOUT13 CLKOUT6 + CLKOUT12(REFCLK) + id="tspan35786">ZCU102 + AD9081-FMCA-EBZ + ref_clk + + rx_sysref + + tx_sysref + CLKIN6 CLKOUT13(SYSREF2) + id="tspan5150">CLKOUT10 CLKIN10 + SYSREF2 + CLKOUT_10 + CLKOUT_6 + FPGA_REFCLK + FPGA_REFCLK_IN + CLKOUT6 + id="tspan17736-1" + x="1.6142108" + y="-105.77497" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:8.14381px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke:none;stroke-width:0.465361px;stroke-opacity:1">FMC + + + + id="path28181-9-10-1" + d="M 48.162573,-62.927732 H 62.558989" + style="fill:none;stroke:#000000;stroke-width:0.308077;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker5160)" + inkscape:export-xdpi="96" + inkscape:export-ydpi="96" + inkscape:export-filename="C:\src\ghdl\docs\block_diagrams\ad9208_dual_ebz\ad9208_vcu118_clocking.png" /> + + ZCU102 + x="20.606249" + y="-72.237328" + style="stroke-width:0.465366">clkin6 fpga_refclk_in + + AD9081-FMCA-EBZ + id="tspan35996-0">tx_device_clk + + REFCLK + x="20.985645" + y="-60.477325" + style="stroke-width:0.465366">clkin10 TX_DEVICE_CLK + id="tspan35996-0-0">rx_device_clk @@ -1865,37 +2441,178 @@ inkscape:export-ydpi="96" inkscape:export-xdpi="96" xml:space="preserve" - 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