From b098b412f0217ae149c852c1dfa2089a12491785 Mon Sep 17 00:00:00 2001 From: AndrDragomir Date: Mon, 7 Aug 2023 14:08:59 +0300 Subject: [PATCH] adrv9026: Add a10soc support Signed-off-by: AndrDragomir --- projects/adrv9026/a10soc/Makefile | 25 ++ projects/adrv9026/a10soc/system_constr.sdc | 15 + projects/adrv9026/a10soc/system_project.tcl | 176 +++++++++++ projects/adrv9026/a10soc/system_qsys.tcl | 24 ++ projects/adrv9026/a10soc/system_top.v | 324 ++++++++++++++++++++ projects/adrv9026/common/adrv9026_qsys.tcl | 252 +++++++++++++++ 6 files changed, 816 insertions(+) create mode 100755 projects/adrv9026/a10soc/Makefile create mode 100755 projects/adrv9026/a10soc/system_constr.sdc create mode 100644 projects/adrv9026/a10soc/system_project.tcl create mode 100755 projects/adrv9026/a10soc/system_qsys.tcl create mode 100755 projects/adrv9026/a10soc/system_top.v create mode 100644 projects/adrv9026/common/adrv9026_qsys.tcl diff --git a/projects/adrv9026/a10soc/Makefile b/projects/adrv9026/a10soc/Makefile new file mode 100755 index 00000000000..eb89c21b756 --- /dev/null +++ b/projects/adrv9026/a10soc/Makefile @@ -0,0 +1,25 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +############################################################################### + +PROJECT_NAME := adrv9026_a10soc + +M_DEPS += ../common/adrv9026_qsys.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl +M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += intel/adi_jesd204 +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../../scripts/project-intel.mk diff --git a/projects/adrv9026/a10soc/system_constr.sdc b/projects/adrv9026/a10soc/system_constr.sdc new file mode 100755 index 00000000000..2676b66d33f --- /dev/null +++ b/projects/adrv9026/a10soc/system_constr.sdc @@ -0,0 +1,15 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "4.06504065 ns" -name ref_clk [get_ports {ref_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*] +set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*] + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/adrv9026/a10soc/system_project.tcl b/projects/adrv9026/a10soc/system_project.tcl new file mode 100644 index 00000000000..32362eca227 --- /dev/null +++ b/projects/adrv9026/a10soc/system_project.tcl @@ -0,0 +1,176 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project adrv9026_a10soc + +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl + +#adrv9026 + +set_location_assignment PIN_N29 -to ref_clk ; ## D4 FMCA_GBTCLK0_M2C_P REFCLK_GXBL1H_CHTp +set_location_assignment PIN_N28 -to "ref_clk(n)" ; ## D5 FMCA_GBTCLK0_M2C_N REFCLK_GXBL1H_CHTn +#set_location_assignment PIN_E5 -to core_clk ; ## H4 FMCA_CLK0_M2C_P IO,CLK_3G_1p,LVDS3G_12p +#set_location_assignment PIN_F5 -to "core_clk(n)" ; ## H5 FMCA_CLK0_M2C_N IO,CLK_3G_1n,LVDS3G_12n + +set_instance_assignment -name IO_STANDARD LVDS -to core_clk + +set_location_assignment PIN_R33 -to rx_serial_data[0] ; ## A2 FMCA_DP01_M2C_P GXBL1H_RX_CH1p,GXBL1H_REFCLK1p +set_location_assignment PIN_R32 -to "rx_serial_data[0](n)" ; ## A3 FMCA_DP01_M2C_N GXBL1H_RX_CH1n,GXBL1H_REFCLK1n +set_location_assignment PIN_T31 -to rx_serial_data[1] ; ## C6 FMCA_DP00_M2C_P GXBL1H_RX_CH0p,GXBL1H_REFCLK0p +set_location_assignment PIN_T30 -to "rx_serial_data[1](n)" ; ## C7 FMCA_DP00_M2C_N GXBL1H_RX_CH0n,GXBL1H_REFCLK0n +set_location_assignment PIN_P35 -to rx_serial_data[2] ; ## A6 FMCA_DP02_M2C_P GXBL1H_RX_CH2p,GXBL1H_REFCLK2p +set_location_assignment PIN_P34 -to "rx_serial_data[2](n)" ; ## A7 FMCA_DP02_M2C_N GXBL1H_RX_CH2n,GXBL1H_REFCLK2n +set_location_assignment PIN_P31 -to rx_serial_data[3] ; ## A10 FMCA_DP03_M2C_P GXBL1H_RX_CH3p,GXBL1H_REFCLK3p +set_location_assignment PIN_P30 -to "rx_serial_data[3](n)" ; ## A11 FMCA_DP03_M2C_N GXBL1H_RX_CH3n,GXBL1H_REFCLK3n + +set_location_assignment PIN_M39 -to tx_serial_data[0] ; ## A22 FMCA_DP01_C2M_P GXBL1H_TX_CH1p +set_location_assignment PIN_M38 -to "tx_serial_data[0](n)" ; ## A23 FMCA_DP01_C2M_N GXBL1H_TX_CH1n +set_location_assignment PIN_N37 -to tx_serial_data[1] ; ## C2 FMCA_DP00_C2M_P GXBL1H_TX_CH0p +set_location_assignment PIN_N36 -to "tx_serial_data[1](n)" ; ## C3 FMCA_DP00_C2M_N GXBL1H_TX_CH0n +set_location_assignment PIN_L37 -to tx_serial_data[2] ; ## A26 FMCA_DP02_C2M_P GXBL1H_TX_CH2p +set_location_assignment PIN_L36 -to "tx_serial_data[2](n)" ; ## A27 FMCA_DP02_C2M_N GXBL1H_TX_CH2n +set_location_assignment PIN_K39 -to tx_serial_data[3] ; ## A30 FMCA_DP03_C2M_P GXBL1H_TX_CH3p +set_location_assignment PIN_K38 -to "tx_serial_data[3](n)" ; ## A31 FMCA_DP03_C2M_N GXBL1H_TX_CH3n + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data + +for {set i 0} {$i < 4} {incr i} { + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}] +} + +set_location_assignment PIN_C14 -to rx_sync ; ## G9 FMCA_LA03_P IO,LVDS3H_8p +set_location_assignment PIN_D14 -to "rx_sync(n)" ; ## G10 FMCA_LA03_N IO,LVDS3H_8n +set_location_assignment PIN_P11 -to rx_sync_2 ; ## G36 FMCA_LA33_P IO,LVDS3F_23 +set_location_assignment PIN_R11 -to "rx_sync_2(n)" ; ## G37 FMCA_LA33_N IO,LVDS3F_23 +set_location_assignment PIN_E3 -to rx_os_sync ; ## G27 FMCA_LA25_P IO,LVDS3F_4p +set_location_assignment PIN_F3 -to "rx_os_sync(n)" ; ## G28 FMCA_LA25_N IO,LVDS3F_4n + +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync_2 +set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync + +set_location_assignment PIN_G14 -to sysref ; ## G6 FMCA_LA00_CC_P IO,LVDS3H_7p +set_location_assignment PIN_H14 -to "sysref(n)" ; ## G7 FMCA_LA00_CC_N IO,LVDS3H_7n + +set_instance_assignment -name IO_STANDARD LVDS -to sysref +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref + +set_location_assignment PIN_C13 -to tx_sync ; ## H7 FMCA_LA02_P IO,LVDS3H_9p +set_location_assignment PIN_D13 -to "tx_sync(n)" ; ## H8 FMCA_LA02_N IO,LVDS3H_9n +set_location_assignment PIN_E1 -to tx_sync_1 ; ## H28 FMCA_LA24_P IO,LVDS3F_3p +set_location_assignment PIN_E2 -to "tx_sync_1(n)" ; ## H29 FMCA_LA24_N IO,LVDS3F_3n + +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync_1 +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync_1 + +set_location_assignment PIN_G1 -to ad9528_reset_b ; ## C26 FMCA_LA27_P IO,LVDS3F_6p +set_location_assignment PIN_H2 -to ad9528_sysref_req ; ## C27 FMCA_LA27_N IO,LVDS3F_6n +set_location_assignment PIN_F13 -to adrv9026_test ; ## D11 FMCA_LA05_P IO,CLK_3H_1p,LVDS3H_12p + +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_test + +set_location_assignment PIN_A10 -to adrv9026_orx_ctrl_a ; ## C10 FMCA_LA06_P IO,LVDS3H_19p +set_location_assignment PIN_B10 -to adrv9026_orx_ctrl_b ; ## C11 FMCA_LA06_N IO,LVDS3H_19n +set_location_assignment PIN_F2 -to adrv9026_orx_ctrl_c ; ## D26 FMCA_LA26_P IO,LVDS3F_5p +set_location_assignment PIN_A8 -to adrv9026_orx_ctrl_d ; ## C15 FMCA_LA10_N IO,LVDS3H_23n + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_orx_ctrl_a +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_orx_ctrl_b +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_orx_ctrl_c +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_orx_ctrl_d + +set_location_assignment PIN_K11 -to adrv9026_rx1_enable ; ## D18 FMCA_LA13_N IO,LVDS3G_20n +set_location_assignment PIN_J10 -to adrv9026_rx2_enable ; ## C19 FMCA_LA14_N IO,LVDS3G_23n +set_location_assignment PIN_D1 -to adrv9026_rx3_enable ; ## D24 FMCA_LA23_N IO,LVDS3F_2n +set_location_assignment PIN_C1 -to adrv9026_rx4_enable ; ## D23 FMCA_LA23_P IO,LVDS3F_2p + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_rx1_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_rx2_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_rx3_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_rx4_enable + +set_location_assignment PIN_J11 -to adrv9026_tx1_enable ; ## D17 FMCA_LA13_P IO,LVDS3G_20p +set_location_assignment PIN_J9 -to adrv9026_tx2_enable ; ## C18 FMCA_LA14_P IO,LVDS3G_23p +set_location_assignment PIN_G2 -to adrv9026_tx3_enable ; ## D27 FMCA_LA26_N IO,LVDS3F_5n +set_location_assignment PIN_A7 -to adrv9026_tx4_enable ; ## C14 FMCA_LA10_P IO,LVDS3H_23p + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_tx1_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_tx2_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_tx3_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_tx4_enable + +set_location_assignment PIN_H13 -to adrv9026_gpint1 ; ## H11 FMCA_LA04_N IO,LVDS3H_11n +set_location_assignment PIN_L5 -to adrv9026_gpint2 ; ## H31 FMCA_LA28_P IO,LVDS3F_18p +set_location_assignment PIN_H12 -to adrv9026_reset_b ; ## H10 FMCA_LA04_P IO,RZQ_3H,LVDS3H_11p + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpint1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpint2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_reset_b + +set_location_assignment PIN_D4 -to adrv9026_gpio[0] ; ## H19 FMCA_LA15_P IO,PLL_3G_CLKOUT1p,PLL_3G_CLKOUT1,PLL_3G_FB1,LVDS3G_10p +set_location_assignment PIN_D5 -to adrv9026_gpio[1] ; ## H20 FMCA_LA15_N IO,PLL_3G_CLKOUT1n,LVDS3G_10n +set_location_assignment PIN_D6 -to adrv9026_gpio[2] ; ## G18 FMCA_LA16_P IO,RZQ_3G,LVDS3G_11p +set_location_assignment PIN_E6 -to adrv9026_gpio[3] ; ## G19 FMCA_LA16_N IO,LVDS3G_11n +set_location_assignment PIN_C2 -to adrv9026_gpio[4] ; ## H25 FMCA_LA21_P IO,LVDS3G_8p +set_location_assignment PIN_D3 -to adrv9026_gpio[5] ; ## H26 FMCA_LA21_N IO,LVDS3G_8n +set_location_assignment PIN_G7 -to adrv9026_gpio[6] ; ## C22 FMCA_LA18_CC_P IO,LVDS3G_17p +set_location_assignment PIN_H7 -to adrv9026_gpio[7] ; ## C23 FMCA_LA18_CC_N IO,LVDS3G_17n +set_location_assignment PIN_G4 -to adrv9026_gpio[8] ; ## G25 FMCA_LA22_N IO,LVDS3F_1n +set_location_assignment PIN_G5 -to adrv9026_gpio[9] ; ## H22 FMCA_LA19_P IO,LVDS3G_16p +set_location_assignment PIN_G6 -to adrv9026_gpio[10] ; ## H23 FMCA_LA19_N IO,LVDS3G_16n +set_location_assignment PIN_C3 -to adrv9026_gpio[11] ; ## G21 FMCA_LA20_P IO,LVDS3G_7p +set_location_assignment PIN_C4 -to adrv9026_gpio[12] ; ## G22 FMCA_LA20_N IO,LVDS3G_7n +set_location_assignment PIN_P10 -to adrv9026_gpio[13] ; ## G31 FMCA_LA29_N IO,LVDS3F_19n +set_location_assignment PIN_N9 -to adrv9026_gpio[14] ; ## G30 FMCA_LA29_P IO,LVDS3F_19p +set_location_assignment PIN_F4 -to adrv9026_gpio[15] ; ## G24 FMCA_LA22_P IO,LVDS3F_1p +set_location_assignment PIN_N13 -to adrv9026_gpio[16] ; ## G16 FMCA_LA12_N IO,LVDS3G_21n +set_location_assignment PIN_M12 -to adrv9026_gpio[17] ; ## G15 FMCA_LA12_P IO,LVDS3G_21p +set_location_assignment PIN_F14 -to adrv9026_gpio[18] ; ## D12 FMCA_LA05_N IO,CLK_3H_1n,LVDS3H_12n + +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to adrv9026_gpio[18] + +set_location_assignment PIN_A12 -to spi_csn_adrv9026 ; ## D14 FMCA_LA09_P IO,LVDS3H_22p +set_location_assignment PIN_A13 -to spi_csn_ad9528 ; ## D15 FMCA_LA09_N IO,LVDS3H_22n +set_location_assignment PIN_A9 -to spi_clk ; ## H13 FMCA_LA07_P IO,LVDS3H_20p +set_location_assignment PIN_B11 -to spi_miso ; ## G12 FMCA_LA08_P IO,LVDS3H_21p +set_location_assignment PIN_B9 -to spi_mosi ; ## H14 FMCA_LA07_N IO,LVDS3H_20n + +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_adrv9026 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi + +execute_flow -compile diff --git a/projects/adrv9026/a10soc/system_qsys.tcl b/projects/adrv9026/a10soc/system_qsys.tcl new file mode 100755 index 00000000000..d1c14615cc5 --- /dev/null +++ b/projects/adrv9026/a10soc/system_qsys.tcl @@ -0,0 +1,24 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set dac_fifo_address_width 10 +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl + +if [info exists ad_project_dir] { + source ../../common/adrv9026_qsys.tcl +} else { + source ../common/adrv9026_qsys.tcl +} + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +sysid_gen_sys_init_file; + diff --git a/projects/adrv9026/a10soc/system_top.v b/projects/adrv9026/a10soc/system_top.v new file mode 100755 index 00000000000..d54706cc524 --- /dev/null +++ b/projects/adrv9026/a10soc/system_top.v @@ -0,0 +1,324 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // hps-ddr4 (32) + + input hps_ddr_ref_clk, + output [ 0:0] hps_ddr_clk_p, + output [ 0:0] hps_ddr_clk_n, + output [ 16:0] hps_ddr_a, + output [ 1:0] hps_ddr_ba, + output [ 0:0] hps_ddr_bg, + output [ 0:0] hps_ddr_cke, + output [ 0:0] hps_ddr_cs_n, + output [ 0:0] hps_ddr_odt, + output [ 0:0] hps_ddr_reset_n, + output [ 0:0] hps_ddr_act_n, + output [ 0:0] hps_ddr_par, + input [ 0:0] hps_ddr_alert_n, + inout [ 3:0] hps_ddr_dqs_p, + inout [ 3:0] hps_ddr_dqs_n, + inout [ 31:0] hps_ddr_dq, + inout [ 3:0] hps_ddr_dbi_n, + input hps_ddr_rzq, + + // pl-ddr4 + + input sys_ddr_ref_clk, + output [ 0:0] sys_ddr_clk_p, + output [ 0:0] sys_ddr_clk_n, + output [ 16:0] sys_ddr_a, + output [ 1:0] sys_ddr_ba, + output [ 0:0] sys_ddr_bg, + output [ 0:0] sys_ddr_cke, + output [ 0:0] sys_ddr_cs_n, + output [ 0:0] sys_ddr_odt, + output [ 0:0] sys_ddr_reset_n, + output [ 0:0] sys_ddr_act_n, + output [ 0:0] sys_ddr_par, + input [ 0:0] sys_ddr_alert_n, + inout [ 7:0] sys_ddr_dqs_p, + inout [ 7:0] sys_ddr_dqs_n, + inout [ 63:0] sys_ddr_dq, + inout [ 7:0] sys_ddr_dbi_n, + input sys_ddr_rzq, + + // hps-ethernet + + input [ 0:0] hps_eth_rxclk, + input [ 0:0] hps_eth_rxctl, + input [ 3:0] hps_eth_rxd, + output [ 0:0] hps_eth_txclk, + output [ 0:0] hps_eth_txctl, + output [ 3:0] hps_eth_txd, + output [ 0:0] hps_eth_mdc, + inout [ 0:0] hps_eth_mdio, + + // hps-sdio + + output [ 0:0] hps_sdio_clk, + inout [ 0:0] hps_sdio_cmd, + inout [ 7:0] hps_sdio_d, + + // hps-usb + + input [ 0:0] hps_usb_clk, + input [ 0:0] hps_usb_dir, + input [ 0:0] hps_usb_nxt, + output [ 0:0] hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + + input [ 0:0] hps_uart_rx, + output [ 0:0] hps_uart_tx, + + // hps-i2c (shared w fmc-a, fmc-b) + + inout [ 0:0] hps_i2c_sda, + inout [ 0:0] hps_i2c_scl, + + // hps-gpio (max-v-u16) + + inout [ 3:0] hps_gpio, + + // gpio (max-v-u21) + + input [ 7:0] gpio_bd_i, + output [ 3:0] gpio_bd_o, + + // adrv9026-interface + + input ref_clk, + input [ 3:0] rx_serial_data, + output [ 3:0] tx_serial_data, + output rx_sync, + output rx_os_sync, + input tx_sync, + input tx_sync_1, + input sysref, + + output ad9528_reset_b, + output ad9528_sysref_req, + output adrv9026_tx1_enable, + output adrv9026_tx2_enable, + output adrv9026_rx1_enable, + output adrv9026_rx2_enable, + output adrv9026_test, + output adrv9026_reset_b, + input adrv9026_gpint1, + input adrv9026_gpint2, + + inout [ 18:0] adrv9026_gpio, + + output spi_csn_ad9528, + output spi_csn_adrv9026, + output spi_clk, + output spi_mosi, + input spi_miso +); + + // internal signals + + wire sys_ddr_cal_success; + wire sys_ddr_cal_fail; + wire sys_hps_resetn; + wire sys_resetn_s; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire [ 7:0] spi_csn_s; + wire dac_fifo_bypass; + + // assignments + + assign spi_csn_ad9528 = spi_csn_s[0]; + assign spi_csn_adrv9026 = spi_csn_s[1]; + + // gpio (adrv9026) + + assign gpio_i[63:61] = gpio_o[63:61]; + + assign dac_fifo_bypass = gpio_o[60]; + assign gpio_i[60:60] = gpio_o[60]; + + assign ad9528_reset_b = gpio_o[59]; + assign ad9528_sysref_req = gpio_o[58]; + assign adrv9026_tx1_enable = gpio_o[57]; + assign adrv9026_tx2_enable = gpio_o[56]; + assign adrv9026_rx1_enable = gpio_o[55]; + assign adrv9026_rx2_enable = gpio_o[54]; + assign adrv9026_test = gpio_o[53]; + assign adrv9026_reset_b = gpio_o[52]; + assign gpio_i[59:52] = gpio_o[59:52]; + + assign gpio_i[51:51] = adrv9026_gpint1; + assign gpio_i[50:50] = adrv9026_gpint2; + + assign gpio_i[49:32] = gpio_o[49:32]; + + // board stuff (max-v-u21) + + assign gpio_i[31:14] = gpio_o[31:14]; + assign gpio_i[13:13] = sys_ddr_cal_success; + assign gpio_i[12:12] = sys_ddr_cal_fail; + assign gpio_i[11: 4] = gpio_bd_i; + assign gpio_i[ 3: 0] = gpio_o[3:0]; + + assign gpio_bd_o = gpio_o[3:0]; + + // peripheral reset + + assign sys_resetn_s = sys_resetn & sys_hps_resetn; + + // instantiations + + system_bd i_system_bd ( + .adrv9026_gpio_export (adrv9026_gpio), + .sys_clk_clk (sys_clk), + .sys_ddr_mem_mem_ck (sys_ddr_clk_p), + .sys_ddr_mem_mem_ck_n (sys_ddr_clk_n), + .sys_ddr_mem_mem_a (sys_ddr_a), + .sys_ddr_mem_mem_act_n (sys_ddr_act_n), + .sys_ddr_mem_mem_ba (sys_ddr_ba), + .sys_ddr_mem_mem_bg (sys_ddr_bg), + .sys_ddr_mem_mem_cke (sys_ddr_cke), + .sys_ddr_mem_mem_cs_n (sys_ddr_cs_n), + .sys_ddr_mem_mem_odt (sys_ddr_odt), + .sys_ddr_mem_mem_reset_n (sys_ddr_reset_n), + .sys_ddr_mem_mem_par (sys_ddr_par), + .sys_ddr_mem_mem_alert_n (sys_ddr_alert_n), + .sys_ddr_mem_mem_dqs (sys_ddr_dqs_p), + .sys_ddr_mem_mem_dqs_n (sys_ddr_dqs_n), + .sys_ddr_mem_mem_dq (sys_ddr_dq), + .sys_ddr_mem_mem_dbi_n (sys_ddr_dbi_n), + .sys_ddr_oct_oct_rzqin (sys_ddr_rzq), + .sys_ddr_ref_clk_clk (sys_ddr_ref_clk), + .sys_ddr_status_local_cal_success (sys_ddr_cal_success), + .sys_ddr_status_local_cal_fail (sys_ddr_cal_fail), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_hps_ddr_mem_ck (hps_ddr_clk_p), + .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n), + .sys_hps_ddr_mem_a (hps_ddr_a), + .sys_hps_ddr_mem_act_n (hps_ddr_act_n), + .sys_hps_ddr_mem_ba (hps_ddr_ba), + .sys_hps_ddr_mem_bg (hps_ddr_bg), + .sys_hps_ddr_mem_cke (hps_ddr_cke), + .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n), + .sys_hps_ddr_mem_odt (hps_ddr_odt), + .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n), + .sys_hps_ddr_mem_par (hps_ddr_par), + .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n), + .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p), + .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n), + .sys_hps_ddr_mem_dq (hps_ddr_dq), + .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n), + .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq), + .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk), + .sys_hps_ddr_rstn_reset_n (sys_resetn), + .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), + .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), + .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), + .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), + .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), + .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), + .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), + .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), + .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), + .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), + .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), + .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), + .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), + .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), + .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), + .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), + .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), + .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), + .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), + .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), + .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), + .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), + .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), + .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), + .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), + .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), + .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), + .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), + .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), + .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp), + .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), + .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), + .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx), + .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx), + .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), + .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), + .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), + .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), + .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), + .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), + .sys_hps_out_rstn_reset_n (sys_hps_resetn), + .sys_hps_rstn_reset_n (sys_resetn), + .sys_rstn_reset_n (sys_resetn_s), + .sys_spi_MISO (spi_miso), + .sys_spi_MOSI (spi_mosi), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s), + .tx_serial_data_tx_serial_data (tx_serial_data), + .tx_fifo_bypass_bypass (dac_fifo_bypass), + .tx_ref_clk_clk (ref_clk), + .tx_sync_export (tx_sync), + .tx_sysref_export (sysref), + .rx_serial_data_rx_serial_data (rx_serial_data), + .rx_ref_clk_clk (ref_clk), + .rx_sync_export (rx_sync), + .pr_rom_data_nc_rom_data('h0), + .rx_sysref_export (sysref)); + +endmodule diff --git a/projects/adrv9026/common/adrv9026_qsys.tcl b/projects/adrv9026/common/adrv9026_qsys.tcl new file mode 100644 index 00000000000..e33a6c82dd8 --- /dev/null +++ b/projects/adrv9026/common/adrv9026_qsys.tcl @@ -0,0 +1,252 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# TX parameters +set TX_NUM_OF_LANES 4 ; # L +set TX_NUM_OF_CONVERTERS 8 ; # M +set TX_SAMPLE_WIDTH 16 ; # N/NP + +set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \ + ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N) + +# RX parameters +set RX_NUM_OF_LANES 4 ; # L +set RX_NUM_OF_CONVERTERS 8 ; # M +set RX_SAMPLE_WIDTH 16 ; # N/NP + +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \ + ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N) + +set dac_fifo_name avl_adrv9026_tx_fifo +set dac_data_width 128 +set dac_dma_data_width 128 + +# NOTE: The real lane rate is 2457.6 Gbps (Tx) and 4915.2 Gbps (RX/Rx_Obs), +# with a real reference clock frequency of 122.88 MHz. A round up needed +# because the fPLL's configuration interface does not support fractional numbers. + +# adrv9026_tx JESD204 + +add_instance adrv9026_tx_jesd204 adi_jesd204 +set_instance_parameter_value adrv9026_tx_jesd204 {ID} {0} +set_instance_parameter_value adrv9026_tx_jesd204 {TX_OR_RX_N} {1} +set_instance_parameter_value adrv9026_tx_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value adrv9026_tx_jesd204 {LANE_RATE} {2460} +set_instance_parameter_value adrv9026_tx_jesd204 {REFCLK_FREQUENCY} {123} +set_instance_parameter_value adrv9026_tx_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES +set_instance_parameter_value adrv9026_tx_jesd204 {LANE_MAP} {0 3 2 1} + +add_connection sys_clk.clk adrv9026_tx_jesd204.sys_clk +add_connection sys_clk.clk_reset adrv9026_tx_jesd204.sys_resetn +add_interface tx_ref_clk clock sink +set_interface_property tx_ref_clk EXPORT_OF adrv9026_tx_jesd204.ref_clk +add_interface tx_serial_data conduit end +set_interface_property tx_serial_data EXPORT_OF adrv9026_tx_jesd204.serial_data +add_interface tx_sysref conduit end +set_interface_property tx_sysref EXPORT_OF adrv9026_tx_jesd204.sysref +add_interface tx_sync conduit end +set_interface_property tx_sync EXPORT_OF adrv9026_tx_jesd204.sync + +# adrv9026_rx JESD204 + +add_instance adrv9026_rx_jesd204 adi_jesd204 +set_instance_parameter_value adrv9026_rx_jesd204 {ID} {1} +set_instance_parameter_value adrv9026_rx_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value adrv9026_rx_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value adrv9026_rx_jesd204 {LANE_RATE} {4920} +set_instance_parameter_value adrv9026_rx_jesd204 {REFCLK_FREQUENCY} {123} +set_instance_parameter_value adrv9026_rx_jesd204 {NUM_OF_LANES} $RX_NUM_OF_LANES +set_instance_parameter_value adrv9026_rx_jesd204 {INPUT_PIPELINE_STAGES} {1} + +add_connection sys_clk.clk adrv9026_rx_jesd204.sys_clk +add_connection sys_clk.clk_reset adrv9026_rx_jesd204.sys_resetn +add_interface rx_ref_clk clock sink +set_interface_property rx_ref_clk EXPORT_OF adrv9026_rx_jesd204.ref_clk +add_interface rx_serial_data conduit end +set_interface_property rx_serial_data EXPORT_OF adrv9026_rx_jesd204.serial_data +add_interface rx_sysref conduit end +set_interface_property rx_sysref EXPORT_OF adrv9026_rx_jesd204.sysref +add_interface rx_sync conduit end +set_interface_property rx_sync EXPORT_OF adrv9026_rx_jesd204.sync + +# adrv9026 TPL cores + +add_instance axi_adrv9026_tx ad_ip_jesd204_tpl_dac +set_instance_parameter_value axi_adrv9026_tx {ID} {0} +set_instance_parameter_value axi_adrv9026_tx {NUM_CHANNELS} $TX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_adrv9026_tx {NUM_LANES} $TX_NUM_OF_LANES +set_instance_parameter_value axi_adrv9026_tx {BITS_PER_SAMPLE} $TX_SAMPLE_WIDTH +set_instance_parameter_value axi_adrv9026_tx {CONVERTER_RESOLUTION} $TX_SAMPLE_WIDTH + +add_instance axi_adrv9026_rx ad_ip_jesd204_tpl_adc +set_instance_parameter_value axi_adrv9026_rx {ID} {0} +set_instance_parameter_value axi_adrv9026_rx {NUM_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_adrv9026_rx {NUM_LANES} $RX_NUM_OF_LANES +set_instance_parameter_value axi_adrv9026_rx {BITS_PER_SAMPLE} $RX_SAMPLE_WIDTH +set_instance_parameter_value axi_adrv9026_rx {CONVERTER_RESOLUTION} $RX_SAMPLE_WIDTH +set_instance_parameter_value axi_adrv9026_rx {TWOS_COMPLEMENT} {1} + +add_connection sys_clk.clk axi_adrv9026_tx.s_axi_clock +add_connection sys_clk.clk_reset axi_adrv9026_tx.s_axi_reset +add_connection sys_clk.clk axi_adrv9026_rx.s_axi_clock +add_connection sys_clk.clk_reset axi_adrv9026_rx.s_axi_reset + +add_connection adrv9026_tx_jesd204.link_clk axi_adrv9026_tx.link_clk +add_connection axi_adrv9026_tx.link_data adrv9026_tx_jesd204.link_data +add_connection adrv9026_rx_jesd204.link_clk axi_adrv9026_rx.link_clk +add_connection adrv9026_rx_jesd204.link_sof axi_adrv9026_rx.if_link_sof +add_connection adrv9026_rx_jesd204.link_data axi_adrv9026_rx.link_data + +# pack(s) & unpack(s) + +add_instance axi_adrv9026_tx_upack util_upack2 +set_instance_parameter_value axi_adrv9026_tx_upack {NUM_OF_CHANNELS} $TX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_adrv9026_tx_upack {SAMPLES_PER_CHANNEL} $TX_SAMPLES_PER_CHANNEL +set_instance_parameter_value axi_adrv9026_tx_upack {SAMPLE_DATA_WIDTH} $TX_SAMPLE_WIDTH +set_instance_parameter_value axi_adrv9026_tx_upack {INTERFACE_TYPE} {1} +add_connection adrv9026_tx_jesd204.link_clk axi_adrv9026_tx_upack.clk +add_connection adrv9026_tx_jesd204.link_reset axi_adrv9026_tx_upack.reset +for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { + add_connection axi_adrv9026_tx_upack.dac_ch_$i axi_adrv9026_tx.dac_ch_$i +} + +add_instance axi_adrv9026_rx_cpack util_cpack2 +set_instance_parameter_value axi_adrv9026_rx_cpack {NUM_OF_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_adrv9026_rx_cpack {SAMPLES_PER_CHANNEL} $RX_SAMPLES_PER_CHANNEL +set_instance_parameter_value axi_adrv9026_rx_cpack {SAMPLE_DATA_WIDTH} $RX_SAMPLE_WIDTH +add_connection adrv9026_rx_jesd204.link_reset axi_adrv9026_rx_cpack.reset +add_connection adrv9026_rx_jesd204.link_clk axi_adrv9026_rx_cpack.clk +for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { + add_connection axi_adrv9026_rx.adc_ch_$i axi_adrv9026_rx_cpack.adc_ch_$i +} +add_connection axi_adrv9026_rx_cpack.if_fifo_wr_overflow axi_adrv9026_rx.if_adc_dovf + +# dac fifo + +ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width + +add_interface tx_fifo_bypass conduit end +set_interface_property tx_fifo_bypass EXPORT_OF avl_adrv9026_tx_fifo.if_bypass + +add_connection adrv9026_tx_jesd204.link_clk avl_adrv9026_tx_fifo.if_dac_clk +add_connection adrv9026_tx_jesd204.link_reset avl_adrv9026_tx_fifo.if_dac_rst +add_connection axi_adrv9026_tx_upack.if_packed_fifo_rd_en avl_adrv9026_tx_fifo.if_dac_valid +add_connection avl_adrv9026_tx_fifo.if_dac_data axi_adrv9026_tx_upack.if_packed_fifo_rd_data +add_connection avl_adrv9026_tx_fifo.if_dac_dunf axi_adrv9026_tx.if_dac_dunf + +# dac & adc dma + +add_instance axi_adrv9026_tx_dma axi_dmac +set_instance_parameter_value axi_adrv9026_tx_dma {ID} {0} +set_instance_parameter_value axi_adrv9026_tx_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value axi_adrv9026_tx_dma {DMA_DATA_WIDTH_DEST} [expr $TX_SAMPLE_WIDTH * \ + $TX_NUM_OF_CONVERTERS * \ + $TX_SAMPLES_PER_CHANNEL] +set_instance_parameter_value axi_adrv9026_tx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_adrv9026_tx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_adrv9026_tx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_adrv9026_tx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_adrv9026_tx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_adrv9026_tx_dma {CYCLIC} {1} +set_instance_parameter_value axi_adrv9026_tx_dma {DMA_TYPE_DEST} {1} +set_instance_parameter_value axi_adrv9026_tx_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value axi_adrv9026_tx_dma {FIFO_SIZE} {16} +set_instance_parameter_value axi_adrv9026_tx_dma {HAS_AXIS_TLAST} {1} + +add_connection sys_dma_clk.clk avl_adrv9026_tx_fifo.if_dma_clk +add_connection sys_dma_clk.clk_reset avl_adrv9026_tx_fifo.if_dma_rst +add_connection sys_dma_clk.clk axi_adrv9026_tx_dma.if_m_axis_aclk +add_connection axi_adrv9026_tx_dma.m_axis avl_adrv9026_tx_fifo.s_axis +add_connection axi_adrv9026_tx_dma.if_m_axis_xfer_req avl_adrv9026_tx_fifo.if_dma_xfer_req +add_connection sys_clk.clk axi_adrv9026_tx_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_adrv9026_tx_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_adrv9026_tx_dma.m_src_axi_clock +add_connection sys_dma_clk.clk_reset axi_adrv9026_tx_dma.m_src_axi_reset + +add_instance axi_adrv9026_rx_dma axi_dmac +set_instance_parameter_value axi_adrv9026_rx_dma {ID} {0} +set_instance_parameter_value axi_adrv9026_rx_dma {DMA_DATA_WIDTH_SRC} [expr $RX_SAMPLE_WIDTH * \ + $RX_NUM_OF_CONVERTERS * \ + $RX_SAMPLES_PER_CHANNEL] +set_instance_parameter_value axi_adrv9026_rx_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_adrv9026_rx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_adrv9026_rx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_adrv9026_rx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_adrv9026_rx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_adrv9026_rx_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_adrv9026_rx_dma {CYCLIC} {0} +set_instance_parameter_value axi_adrv9026_rx_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_adrv9026_rx_dma {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_adrv9026_rx_dma {FIFO_SIZE} {16} +add_connection adrv9026_rx_jesd204.link_clk axi_adrv9026_rx_dma.if_fifo_wr_clk +add_connection axi_adrv9026_rx_cpack.if_packed_fifo_wr_en axi_adrv9026_rx_dma.if_fifo_wr_en +add_connection axi_adrv9026_rx_cpack.if_packed_fifo_wr_sync axi_adrv9026_rx_dma.if_fifo_wr_sync +add_connection axi_adrv9026_rx_cpack.if_packed_fifo_wr_data axi_adrv9026_rx_dma.if_fifo_wr_din +add_connection axi_adrv9026_rx_dma.if_fifo_wr_overflow axi_adrv9026_rx_cpack.if_packed_fifo_wr_overflow +add_connection sys_clk.clk axi_adrv9026_rx_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_adrv9026_rx_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_adrv9026_rx_dma.m_dest_axi_clock +add_connection sys_dma_clk.clk_reset axi_adrv9026_rx_dma.m_dest_axi_reset + +# adrv9026 gpio + +add_instance avl_adrv9026_gpio altera_avalon_pio +set_instance_parameter_value avl_adrv9026_gpio {direction} {Bidir} +set_instance_parameter_value avl_adrv9026_gpio {generateIRQ} {1} +set_instance_parameter_value avl_adrv9026_gpio {width} {19} +add_connection sys_clk.clk avl_adrv9026_gpio.clk +add_connection sys_clk.clk_reset avl_adrv9026_gpio.reset +add_interface adrv9026_gpio conduit end +set_interface_property adrv9026_gpio EXPORT_OF avl_adrv9026_gpio.external_connection + +# reconfig sharing + +for {set i 0} {$i < 4} {incr i} { + add_instance avl_adxcfg_${i} avl_adxcfg + add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk + add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n + add_connection avl_adxcfg_${i}.rcfg_m0 adrv9026_tx_jesd204.phy_reconfig_${i} + add_connection avl_adxcfg_${i}.rcfg_m1 adrv9026_rx_jesd204.phy_reconfig_${i} + + set_instance_parameter_value avl_adxcfg_${i} {ADDRESS_WIDTH} $xcvr_reconfig_addr_width +} + +# addresses + +ad_cpu_interconnect 0x00020000 adrv9026_tx_jesd204.link_reconfig +ad_cpu_interconnect 0x00024000 adrv9026_tx_jesd204.link_management +ad_cpu_interconnect 0x00026000 adrv9026_tx_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00028000 adrv9026_tx_jesd204.lane_pll_reconfig +ad_cpu_interconnect 0x0002a000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x0002c000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x0002e000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x00030000 avl_adxcfg_3.rcfg_s0 +ad_cpu_interconnect 0x00032000 axi_adrv9026_tx_dma.s_axi + +ad_cpu_interconnect 0x00040000 adrv9026_rx_jesd204.link_reconfig +ad_cpu_interconnect 0x00044000 adrv9026_rx_jesd204.link_management +ad_cpu_interconnect 0x00046000 adrv9026_rx_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00048000 avl_adxcfg_0.rcfg_s1 +ad_cpu_interconnect 0x0004a000 avl_adxcfg_1.rcfg_s1 +ad_cpu_interconnect 0x0004c000 axi_adrv9026_rx_dma.s_axi + +ad_cpu_interconnect 0x00058000 avl_adxcfg_2.rcfg_s1 +ad_cpu_interconnect 0x0005a000 avl_adxcfg_3.rcfg_s1 + +ad_cpu_interconnect 0x00060000 axi_adrv9026_rx.s_axi +ad_cpu_interconnect 0x00064000 axi_adrv9026_tx.s_axi +ad_cpu_interconnect 0x00070000 avl_adrv9026_gpio.s1 + +# dma interconnects + +ad_dma_interconnect axi_adrv9026_tx_dma.m_src_axi +ad_dma_interconnect axi_adrv9026_rx_dma.m_dest_axi + +# interrupts + +ad_cpu_interrupt 11 axi_adrv9026_tx_dma.interrupt_sender +ad_cpu_interrupt 12 axi_adrv9026_rx_dma.interrupt_sender +ad_cpu_interrupt 14 avl_adrv9026_gpio.irq +