Skip to content

Commit e5a5ee3

Browse files
ladaceladace
committed
ad4630: Fefactoring for AD463x, AD403x and ADAQ4224
 Reduced the number of xdc files. Reduced the number of system_top files. Fixed *_fmc.txt files. Signed-off-by: Liviu Adace <liviu.adace@analog.com>
1 parent dc2e5c3 commit e5a5ee3

16 files changed

+249
-594
lines changed

‎projects/ad4630_fmc/common/ad4630_fmc.txt

Lines changed: 0 additions & 20 deletions
This file was deleted.

‎projects/ad4630_fmc/common/ad463x_fmc.txt

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,21 @@
11
FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
22

33
# ad463x
4-
G06 LA00_CC_P SCLK_FMC ad463x_spi_sclk LVCMOS25 #N/A
5-
G07 LA00_CC_N CS_FMC ad463x_spi_cs LVCMOS25 #N/A
6-
C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A
7-
H07 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A
8-
H08 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A
9-
G09 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A
10-
G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A
11-
H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A
12-
H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A
13-
D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A
14-
D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A
4+
G06 LA00_CC_P SCLK_FMC ad4x3x_spi_sclk LVCMOS25 #N/A
5+
G07 LA00_CC_N CS_FMC ad4x3x_spi_cs LVCMOS25 #N/A
6+
C11 LA06_N SDI_FMC ad4x3x_spi_sdo LVCMOS25 #N/A
7+
H07 LA02_P SDO0_FMC ad4x3x_spi_sdi[0] LVCMOS25 #N/A
8+
H08 LA02_N SDO1_FMC ad4x3x_spi_sdi[1] LVCMOS25 #N/A
9+
G09 LA03_P SDO2_FMC ad4x3x_spi_sdi[2] LVCMOS25 #N/A
10+
G10 LA03_N SDO3_FMC ad4x3x_spi_sdi[3] LVCMOS25 #N/A
11+
H10 LA04_P SDO4_FMC ad4x3x_spi_sdi[4] LVCMOS25 #N/A
12+
H11 LA04_N SDO5_FMC ad4x3x_spi_sdi[5] LVCMOS25 #N/A
13+
D11 LA05_P SDO6_FMC ad4x3x_spi_sdi[6] LVCMOS25 #N/A
14+
D12 LA05_N SDO7_FMC ad4x3x_spi_sdi[7] LVCMOS25 #N/A
1515

16-
D20 LA17_CC_p SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A
17-
D09 LA01_CC_N RESET_FMC ad463x_resetn LVCMOS25 #N/A
18-
D08 LA01_CC_P CNV_FMC ad463x_cnv LVCMOS25 #N/A
19-
C22 LA18_CC_P BUSY_FMC ad463x_busy LVCMOS25 #N/A
20-
H04 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A
16+
D20 LA17_CC_p SCK_OUT_FMC ad4x3x_echo_sclk LVCMOS25 #N/A
17+
D09 LA01_CC_N RESET_FMC ad4x3x_resetn LVCMOS25 #N/A
18+
D08 LA01_CC_P CNV_FMC ad4x3x_cnv LVCMOS25 #N/A
19+
C22 LA18_CC_P BUSY_FMC ad4x3x_busy LVCMOS25 #N/A
20+
H04 CLK0_M2C_P CLK ad4x3x_ext_clk LVCMOS25 #N/A
2121

‎projects/ad4630_fmc/common/ad463x_adaq42xx_bd.tcl renamed to ‎projects/ad4630_fmc/common/ad4x3x_bd.tcl

Lines changed: 48 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -5,13 +5,13 @@
55

66
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
77
# system level parameters
8-
set AD463X_ADAQ42XX_N $ad_project_params(AD463X_ADAQ42XX_N)
8+
set AD463X_AD403X_N $ad_project_params(AD463X_AD403X_N)
99
set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
1010
set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE)
1111
set CLK_MODE $ad_project_params(CLK_MODE)
1212
set DDR_EN $ad_project_params(DDR_EN)
1313

14-
puts "build parameters: AD463X_ADAQ42XX_N: $AD463X_ADAQ42XX_N ; NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ;DDR_EN: $DDR_EN"
14+
puts "build parameters: AD463X_AD403X_N: $AD463X_AD403X_N ; NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ;DDR_EN: $DDR_EN"
1515

1616
# block design ports and interfaces
1717
# specify the CNV generator's reference clock frequency in MHz
@@ -25,17 +25,17 @@ set adc_sampling_rate 1000000
2525
# specify the MAX17687 and LT8608 SYNC signal frequency (400KHz)
2626
set max17687_sync_freq 400000
2727

28-
#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad463x_adaq42xx_spi
28+
#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad4x3x_spi
2929

30-
create_bd_port -dir O ad463x_adaq42xx_spi_sclk
31-
create_bd_port -dir O ad463x_adaq42xx_spi_cs
32-
create_bd_port -dir O ad463x_adaq42xx_spi_sdo
33-
create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad463x_adaq42xx_spi_sdi
30+
create_bd_port -dir O ad4x3x_spi_sclk
31+
create_bd_port -dir O ad4x3x_spi_cs
32+
create_bd_port -dir O ad4x3x_spi_sdo
33+
create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad4x3x_spi_sdi
3434

35-
create_bd_port -dir I ad463x_adaq42xx_echo_sclk
36-
create_bd_port -dir I ad463x_adaq42xx_busy
37-
create_bd_port -dir O ad463x_adaq42xx_cnv
38-
create_bd_port -dir I ad463x_adaq42xx_ext_clk
35+
create_bd_port -dir I ad4x3x_echo_sclk
36+
create_bd_port -dir I ad4x3x_busy
37+
create_bd_port -dir O ad4x3x_cnv
38+
create_bd_port -dir I ad4x3x_ext_clk
3939

4040
create_bd_port -dir O max17687_sync_clk
4141

@@ -50,7 +50,7 @@ ad_connect spi_clk spi_clkgen/clk_0
5050

5151
# create a SPI Engine architecture
5252

53-
#spi_engine_create "spi_ad463x_adaq42xx" 32 1 1 $NUM_OF_SDI 0 1
53+
#spi_engine_create "spi_ad4x3x" 32 1 1 $NUM_OF_SDI 0 1
5454

5555
set data_width 32
5656
set async_spi_clk 1
@@ -60,7 +60,7 @@ set num_sdo 1
6060
set sdi_delay 1
6161
set echo_sclk 1
6262

63-
set hier_spi_engine spi_ad463x_adaq42xx
63+
set hier_spi_engine spi_ad4x3x
6464

6565
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
6666

@@ -92,18 +92,25 @@ ad_ip_parameter sync_generator CONFIG.PULSE_0_PERIOD $max17687_cycle
9292
ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17687_cycle) / 2))]
9393

9494
ad_ip_instance spi_axis_reorder data_reorder
95-
ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI
95+
switch $AD463X_AD403X_N {
96+
0 {
97+
ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES [expr $NUM_OF_SDI *2]
98+
}
99+
1 {
100+
ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI *2
101+
}
102+
}
96103

97104
# dma to receive data stream
98105

99-
ad_ip_instance axi_dmac axi_ad463x_adaq42xx_dma
100-
ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.DMA_TYPE_SRC 1
101-
ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.DMA_TYPE_DEST 0
102-
ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.CYCLIC 0
103-
ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.AXI_SLICE_DEST 1
104-
ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.AXI_SLICE_SRC 1
105-
ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.DMA_DATA_WIDTH_SRC 64
106-
ad_ip_parameter axi_ad463x_adaq42xx_dma CONFIG.DMA_DATA_WIDTH_DEST 64
106+
ad_ip_instance axi_dmac axi_ad4x3x_dma
107+
ad_ip_parameter axi_ad4x3x_dma CONFIG.DMA_TYPE_SRC 1
108+
ad_ip_parameter axi_ad4x3x_dma CONFIG.DMA_TYPE_DEST 0
109+
ad_ip_parameter axi_ad4x3x_dma CONFIG.CYCLIC 0
110+
ad_ip_parameter axi_ad4x3x_dma CONFIG.AXI_SLICE_DEST 1
111+
ad_ip_parameter axi_ad4x3x_dma CONFIG.AXI_SLICE_SRC 1
112+
ad_ip_parameter axi_ad4x3x_dma CONFIG.DMA_DATA_WIDTH_SRC 64
113+
ad_ip_parameter axi_ad4x3x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
107114

108115
# Trigger for SPI offload
109116
if {$CAPTURE_ZONE == 1} {
@@ -112,7 +119,7 @@ if {$CAPTURE_ZONE == 1} {
112119
# is used for SDI latching
113120
switch $CLK_MODE {
114121
0 {
115-
ad_connect $hier_spi_engine/echo_sclk ad463x_adaq42xx_echo_sclk
122+
ad_connect $hier_spi_engine/echo_sclk ad4x3x_echo_sclk
116123
}
117124
1 -
118125
2 {
@@ -135,7 +142,7 @@ if {$CAPTURE_ZONE == 1} {
135142
ad_connect busy_capture/rst GND
136143
ad_connect $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn busy_sync/out_resetn
137144

138-
ad_connect ad463x_adaq42xx_busy busy_sync/in_bits
145+
ad_connect ad4x3x_busy busy_sync/in_bits
139146
ad_connect busy_sync/out_bits busy_capture/signal_in
140147
ad_connect $hier_spi_engine/trigger busy_capture/signal_out
141148
## SDI is latched by the SPIE execution module
@@ -150,7 +157,7 @@ if {$CAPTURE_ZONE == 1} {
150157
## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY
151158
# is used for SDI latching
152159

153-
ad_connect $hier_spi_engine/echo_sclk ad463x_adaq42xx_echo_sclk
160+
ad_connect $hier_spi_engine/echo_sclk ad4x3x_echo_sclk
154161
switch $CLK_MODE {
155162
0 {
156163
## SDI is latched by the SPIE execution module
@@ -164,9 +171,9 @@ if {$CAPTURE_ZONE == 1} {
164171
ad_ip_parameter data_capture CONFIG.NUM_OF_LANES $NUM_OF_SDI
165172

166173
ad_connect spi_clk data_capture/clk
167-
ad_connect ad463x_adaq42xx_spi_cs data_capture/csn
168-
ad_connect ad463x_adaq42xx_busy data_capture/echo_sclk
169-
ad_connect ad463x_adaq42xx_spi_sdi data_capture/data_in
174+
ad_connect ad4x3x_spi_cs data_capture/csn
175+
ad_connect ad4x3x_busy data_capture/echo_sclk
176+
ad_connect ad4x3x_spi_sdi data_capture/data_in
170177

171178
ad_connect data_capture/m_axis data_reorder/s_axis
172179

@@ -183,7 +190,7 @@ if {$CAPTURE_ZONE == 1} {
183190
exit 2
184191

185192
}
186-
ad_connect ad463x_adaq42xx_cnv cnv_generator/pwm_1
193+
ad_connect ad4x3x_cnv cnv_generator/pwm_1
187194
ad_connect max17687_sync_clk sync_generator/pwm_0
188195

189196
# clocks
@@ -193,40 +200,40 @@ ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk
193200
ad_connect $sys_cpu_clk sync_generator/s_axi_aclk
194201
ad_connect spi_clk $hier_spi_engine/spi_clk
195202
ad_connect spi_clk data_reorder/axis_aclk
196-
ad_connect spi_clk axi_ad463x_adaq42xx_dma/s_axis_aclk
197-
ad_connect ad463x_adaq42xx_ext_clk cnv_generator/ext_clk
198-
ad_connect ad463x_adaq42xx_ext_clk sync_generator/ext_clk
203+
ad_connect spi_clk axi_ad4x3x_dma/s_axis_aclk
204+
ad_connect ad4x3x_ext_clk cnv_generator/ext_clk
205+
ad_connect ad4x3x_ext_clk sync_generator/ext_clk
199206

200207
# resets
201208

202209
ad_connect $sys_cpu_resetn cnv_generator/s_axi_aresetn
203210
ad_connect data_reorder/axis_aresetn VCC
204211
ad_connect $sys_cpu_resetn $hier_spi_engine/resetn
205-
ad_connect $sys_cpu_resetn axi_ad463x_adaq42xx_dma/m_dest_axi_aresetn
212+
ad_connect $sys_cpu_resetn axi_ad4x3x_dma/m_dest_axi_aresetn
206213

207214
# data path
208215

209-
ad_connect $hier_spi_engine/${hier_spi_engine}_execution/cs ad463x_adaq42xx_spi_cs
210-
ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sclk ad463x_adaq42xx_spi_sclk
211-
ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sdo ad463x_adaq42xx_spi_sdo
212-
ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sdi ad463x_adaq42xx_spi_sdi
216+
ad_connect $hier_spi_engine/${hier_spi_engine}_execution/cs ad4x3x_spi_cs
217+
ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sclk ad4x3x_spi_sclk
218+
ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sdo ad4x3x_spi_sdo
219+
ad_connect $hier_spi_engine/${hier_spi_engine}_execution/sdi ad4x3x_spi_sdi
213220

214-
ad_connect axi_ad463x_adaq42xx_dma/s_axis data_reorder/m_axis
221+
ad_connect axi_ad4x3x_dma/s_axis data_reorder/m_axis
215222

216223
# AXI memory mapped address space
217224

218225
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
219226
ad_cpu_interconnect 0x44b00000 cnv_generator
220227
ad_cpu_interconnect 0x44c00000 sync_generator
221-
ad_cpu_interconnect 0x44a30000 axi_ad463x_adaq42xx_dma
228+
ad_cpu_interconnect 0x44a30000 axi_ad4x3x_dma
222229
ad_cpu_interconnect 0x44a70000 spi_clkgen
223230

224231
# interrupts
225232

226-
ad_cpu_interrupt "ps-13" "mb-13" axi_ad463x_adaq42xx_dma/irq
233+
ad_cpu_interrupt "ps-13" "mb-13" axi_ad4x3x_dma/irq
227234
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
228235

229236
# interconnect to memory interface
230237

231238
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
232-
ad_mem_hp2_interconnect sys_cpu_clk axi_ad463x_adaq42xx_dma/m_dest_axi
239+
ad_mem_hp2_interconnect sys_cpu_clk axi_ad4x3x_dma/m_dest_axi

‎projects/ad4630_fmc/common/adaq42xx_fmc.txt

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,19 @@
11
FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
22

33
# adaq42xx
4-
G06 LA00_CC_P SCLK_FMC adaq42xx_spi_sclk LVCMOS25 #N/A
5-
G07 LA00_CC_N CS_FMC adaq42xx_spi_cs LVCMOS25 #N/A
6-
C11 LA06_N SDI_FMC adaq42xx_spi_sdo LVCMOS25 #N/A
7-
H07 LA02_P SDO0_FMC adaq42xx_spi_sdi[0] LVCMOS25 #N/A
8-
H08 LA02_N SDO1_FMC adaq42xx_spi_sdi[1] LVCMOS25 #N/A
9-
G09 LA03_P SDO2_FMC adaq42xx_spi_sdi[2] LVCMOS25 #N/A
10-
G10 LA03_N SDO3_FMC adaq42xx_spi_sdi[3] LVCMOS25 #N/A
4+
G06 LA00_CC_P SCLK_FMC ad4x3x_spi_sclk LVCMOS25 #N/A
5+
G07 LA00_CC_N CS_FMC ad4x3x_spi_cs LVCMOS25 #N/A
6+
C11 LA06_N SDI_FMC ad4x3x_spi_sdo LVCMOS25 #N/A
7+
H07 LA02_P SDO0_FMC ad4x3x_spi_sdi[0] LVCMOS25 #N/A
8+
H08 LA02_N SDO1_FMC ad4x3x_spi_sdi[1] LVCMOS25 #N/A
9+
G09 LA03_P SDO2_FMC ad4x3x_spi_sdi[2] LVCMOS25 #N/A
10+
G10 LA03_N SDO3_FMC ad4x3x_spi_sdi[3] LVCMOS25 #N/A
1111

12-
D20 LA17_CC_p SCK_OUT_FMC adaq42xx_echo_sclk LVCMOS25 #N/A
13-
D09 LA01_CC_N RESET_FMC adaq42xx_resetn LVCMOS25 #N/A
14-
D08 LA01_CC_P CNV_FMC adaq42xx_cnv LVCMOS25 #N/A
15-
C22 LA18_CC_P BUSY_FMC adaq42xx_busy LVCMOS25 #N/A
16-
H04 CLK0_M2C_P CLK adaq42xx_ext_clk LVCMOS25 #N/A
12+
D20 LA17_CC_p SCK_OUT_FMC ad4x3x_echo_sclk LVCMOS25 #N/A
13+
D09 LA01_CC_N RESET_FMC ad4x3x_resetn LVCMOS25 #N/A
14+
D08 LA01_CC_P CNV_FMC ad4x3x_cnv LVCMOS25 #N/A
15+
C22 LA18_CC_P BUSY_FMC ad4x3x_busy LVCMOS25 #N/A
16+
H04 CLK0_M2C_P CLK ad4x3x_ext_clk LVCMOS25 #N/A
1717

1818
G12 LA08_P MUX_A0 adaq42xx_pgia_mux[0] LVCMOS25 #N/A
1919
G13 LA08_N MUX_A1 adaq42xx_pgia_mux[1] LVCMOS25 #N/A

‎projects/ad4630_fmc/zed/Makefile

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,11 @@
44
## Auto-generated, do not modify!
55
####################################################################################
66

7-
PROJECT_NAME := ad463x_adaq42xx_fmc_zed
7+
PROJECT_NAME := ad4x3x_fmc_zed
88

9-
M_DEPS += system_constr_8sdi.xdc
10-
M_DEPS += system_constr_4sdi.xdc
11-
M_DEPS += system_constr_2sdi.xdc
12-
M_DEPS += system_constr_1sdi.xdc
13-
M_DEPS += ../common/ad463x_adaq42xx_bd.tcl
9+
M_DEPS += system_constr.xdc
10+
M_DEPS += system_constr.tcl
11+
M_DEPS += ../common/ad4x3x_bd.tcl
1412
M_DEPS += ../../scripts/adi_pd.tcl
1513
M_DEPS += ../../common/zed/zed_system_constr.xdc
1614
M_DEPS += ../../common/zed/zed_system_bd.tcl

‎projects/ad4630_fmc/zed/system_bd.tcl

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@ source $ad_hdl_dir/projects/scripts/adi_pd.tcl
77
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
88

99
# add RTL source that will be instantiated in system_bd directly
10-
adi_project_files ad463x_adaq42xx_fmc_zed [list \
10+
adi_project_files ad4x3x_fmc_zed [list \
1111
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
1212
"$ad_hdl_dir/library/util_cdc/sync_bits.v" ]
1313

1414
# block design
15-
source ../common/ad463x_adaq42xx_bd.tcl
15+
source ../common/ad4x3x_bd.tcl
1616

1717
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
1818

0 commit comments

Comments
 (0)