From e815b2e41b1e79760c402090278323a65bf61eb0 Mon Sep 17 00:00:00 2001 From: caosjr Date: Wed, 25 Sep 2024 18:52:34 -0300 Subject: [PATCH] FIX: qspi_sel connected properly Changed some parts of the documentation. Inserted EVAL-AD3552R documentation with some more info Signed-off-by: --- docs/library/axi_ad3552r/index.rst | 57 +- .../ad3552r_evb_zed_block_diagram.svg | 1925 +++++++++++++++++ docs/projects/ad3552r_evb/index.rst | 228 ++ docs/projects/index.rst | 1 + library/axi_ad35xxr/axi_ad35xxr.v | 2 +- 5 files changed, 2189 insertions(+), 24 deletions(-) create mode 100644 docs/projects/ad3552r_evb/ad3552r_evb_zed_block_diagram.svg create mode 100644 docs/projects/ad3552r_evb/index.rst diff --git a/docs/library/axi_ad3552r/index.rst b/docs/library/axi_ad3552r/index.rst index 5bf5332d58..3dbe0f591b 100644 --- a/docs/library/axi_ad3552r/index.rst +++ b/docs/library/axi_ad3552r/index.rst @@ -6,27 +6,32 @@ AXI AD35XXR .. hdl-component-diagram:: :path: library/axi_ad35xxr -The :git-hdl:`AXI AD3552R ` IP core can be used to -interface the :adi:`AD3552R`, a low drift, ultra-fast, 16-bit accuracy, current -output digital-to-analog converter (DAC) that can be configured in multiple -voltage span ranges. It also supports :adi:`AD3542R`, a low drift, dual channel, -ultra-fast, 12-/16-bit accuracy, voltage output digital-to-analog converter -(DAC) that can be configured in multiple voltage span ranges. +The :git-hdl:`AXI AD3552R ` IP core can be used to +interface the :adi:`AD3552R`, :adi:`AD3551R`, :adi:`AD3542R`, and +:adi:`AD3541R`. :adi:`AD3552R` is a low drift, dual channel, ultra-fast, +16-bit accuracy, current output digital-to-analog converter (DAC) that can be +configured in multiple voltage span ranges, the :adi:`AD3551R` is the single +channel part. :adi:`AD3542R` is is a low drift, dual channel, ultra-fast, +12-/16-bit accuracy, voltage output digital-to-analog converter (DAC) that +can be configured in multiple voltage span ranges, the :adi:`AD3541R` is the +single channel part. + Features -------------------------------------------------------------------------------- -* AXI-based configuration -* Vivado compatible -* 8b register read/write SDR/DDR -* 16b register read/write SDR/DDR -* data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate) -* selectable input source: DMA/ADC/TEST_RAMP -* data out clock(SCLK) has clk_in/2 frequency for both configuration and streaming - mode -* the IP reference clock (clk_in) can have a maximum frequency of 132MHz -* the IP has multiple device synchronization capability when the DMA is set - as an input data source +* AXI-based configuration; +* Vivado compatible; +* 8b register read/write SDR/DDR; +* 16b register read/write SDR/DDR; +* Data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate); +* Selectable input source: DMA/ADC/TEST_RAMP; +* Data out clock(SCLK) has clk_in/2 frequency for both configuration and streaming + mode; +* The IP reference clock (clk_in) can have a maximum frequency of 132MHz; +* The IP has multiple device synchronization capability when the DMA is set + as an input data source. + Files -------------------------------------------------------------------------------- @@ -101,9 +106,9 @@ Interface * - valid_in_dma_sec - Valid from a secondary DMAC if synchronization is needed. * - external_sync - - External synchronization flag from another ad35xxr IP. + - External synchronization flag from another axi_ad35xxr IP. * - sync_ext_device - - Start_sync external device to another ad35xxr IP. + - Start_sync external device to another _axi_ad35xxr IP. * - dac_sclk - Serial clock. * - dac_csn @@ -115,7 +120,8 @@ Interface * - sdio_t - I/O buffer control signal. * - qspi_sel - - QSPI Mode Enable. High level enables quad SPI interface mode. + - QSPI Mode Enable. High level enables quad SPI interface mode + (ad3552r and ad3551r). * - s_axi - Standard AXI Slave Memory Map interface. @@ -130,13 +136,16 @@ Detailed Description The top module instantiates: -* The ad35xxr interface module -* The ad35xxr core module +* The axi_ad35xxr interface module +* The axi_ad35xxr core module * The AXI handling interface The axi_ad35xxr_if has the state machine that controls the SPI interface, which can be Single SPI (Classic), Dual SPI, and Quad SPI. -The axi_ad35xxr_core module instantiates 2 ad35xxr channel modules. +The axi_ad35xxr_core module instantiates 2 ad35xxr channel modules even for +the ad35x1r cases. For the single channel and 12 bit accuracy cases, consider +the 16 LSBs -- The 4 LSBs of this word are 0's for the 12-bit accuracy. + Register Map -------------------------------------------------------------------------------- @@ -199,6 +208,8 @@ References * HDL IP core at :git-hdl:`dev_ad3542r:library/axi_ad35xxr` * HDL project at :git-hdl:`dev_ad3542r:projects/ad35xxr_evb` * :adi:`AD3552R` +* :adi:`AD3551R` * :adi:`AD3542R` +* :adi:`AD3541R` * :xilinx:`Zynq-7000 SoC Overview ` * :xilinx:`Zynq-7000 SoC Packaging and Pinout ` diff --git a/docs/projects/ad3552r_evb/ad3552r_evb_zed_block_diagram.svg b/docs/projects/ad3552r_evb/ad3552r_evb_zed_block_diagram.svg new file mode 100644 index 0000000000..554b0371a5 --- /dev/null +++ b/docs/projects/ad3552r_evb/ad3552r_evb_zed_block_diagram.svg @@ -0,0 +1,1925 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + Transmit path + + MEMORY INTERCONNECT + ZedBoard + + + FMC CONNECTOR + + + DMA + ARM (Zynq) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 32 + 32 + DMA_CLK=100MHz + REF_CLK= 133.3MHz + + + + + + + + AXI_AD3552R  IP architecture + + + + AXI_AD3552R  IP + + + + + + + + + + AXI_AD3552R_IF + + + + AXI_AD3552R_IF + + + + + + + + + + + + UP_AXI + + + + UP_AXI + + + + + + + + + + AXI_AD3552R + +CHANNEL 0 + + + + AXI_AD3552RCHANNEL 0 + + + + + + + + + AXI_AD3552R + +CHANNEL 1 + + + + AXI_AD3552RCHANNEL 1 + + + + + + + + + UP_DAC + +COMMON  + + + + UP_DACCOMMON + + + + + + + + + AXI_AD3552R_CORE + + + + AXI_AD3552R_CORE + + + + + + Text is not SVG - cannot display + + + + + + + ad3552r_spi_sdio[3:0] + ad3552r_spi_sclk + + ad3552r_spi_cs + + diff --git a/docs/projects/ad3552r_evb/index.rst b/docs/projects/ad3552r_evb/index.rst new file mode 100644 index 0000000000..7299650719 --- /dev/null +++ b/docs/projects/ad3552r_evb/index.rst @@ -0,0 +1,228 @@ +.. _ad3552r_evb: + +EVAL-AD3552R HDL project +================================================================================ + +Overview +------------------------------------------------------------------------------- + +The :adi:`EVAL-AD3552R ` is an evaluation board for the +:adi:`AD3552R `, a dual-channel, 16-bit fast precision +digital-to-analog converter (DAC). The same eval board can be used to evaluate +the :adi:`AD3551R `, the single channel part. Each channel of the +:adi:`AD3552R ` is equipped with a different transimpedance +amplifier: Channel 0 has a fast amplifier that achieves the optimal dynamic +performance and Channel 1 has a precision amplifier that guarantees the +optimal DC precision over temperature. + +The board allows testing all the output ranges of the DAC, waveform generation, +power supply and reference options. + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-AD3552R ` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`AD3552R` +- :adi:`AD3551R` + +Supported carriers +------------------------------------------------------------------------------- + +.. list-table:: + :widths: 35 35 30 + :header-rows: 1 + + * - Evaluation board + - Carrier + - FMC slot + * - :adi:`EVAL-AD3552R ` + - :xilinx:`ZedBoard ` + - FMC-LPC + +Block design +------------------------------------------------------------------------------- + +.. warning:: + + The VADJ for the Zedboard must be set to 1.8V. + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data path and clock domains are depicted in the below diagram: + +.. image:: ad3552r_evb_zed_block_diagram.svg + :width: 800 + :align: center + :alt: EVAL-AD3552R/ZedBoard block diagram + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture`). + +==================== =============== +Instance Zynq/Microblaze +==================== =============== +axi_ad35xxr_dac 0x44A7_0000 +axi_dac_dma 0x44A3_0000 +axi_clkgen 0x44B0_0000 +==================== =============== + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 20 20 20 15 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + - Software GPIO + * - + - (from FPGA view) + - + - Zynq-7000 + - Zynq MP + * - ad35xxr_resetn + - OUT + - 38 + - 92 + - 116 + * - ad35xxr_gpio_9 + - INOUT + - 37 + - 91 + - 115 + * - ad35xxr_gpio_8 + - INOUT + - 36 + - 90 + - 114 + * - ad35xxr_gpio_7 + - INOUT + - 35 + - 89 + - 113 + * - ad35xxr_gpio_6 + - INOUT + - 34 + - 88 + - 112 + * - ad35xxr_alertn + - INOUT + - 33 + - 87 + - 111 + * - ad35xxr_ldacn + - INOUT + - 32 + - 86 + - 110 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +================ === ========== =========== +Instance name HDL Linux Zynq Actual Zynq +================ === ========== =========== +axi_dac_dma 13 57 89 +================ === ========== =========== + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository, and then build the project as follows: + +**Linux/Cygwin/WSL** + +.. code-block:: + :linenos: + + user@analog:~$ cd hdl/projects/ad35xxr_evb/zed + user@analog:~/hdl/projects/ad35xxr_evb/zed$ make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Resources +------------------------------------------------------------------------------- + +Systems related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`[Wiki] EVAL-AD3552R Evaluation Board on ZedBoard User Guide ` + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: + + - :adi:`AD3552R` + - :adi:`AD3551R` + +- :adi:`UG-2217, User Guide | EVAL-AD3552R ` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`EVAL-AD3552R HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + + * - AXI_AD35XXR + - :git-hdl:`dev_ad3542r:library/axi_ad35xxr` + - :ref:`here ` + * - AXI_CLKGEN + - :git-hdl:`library/axi_clkgen` + - :ref:`here ` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac` + - :ref:`here ` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`here ` + * - AXI_I2S_ADI + - :git-hdl:`library/axi_i2s_adi` + - — + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx` + - — + * - AXI_SYSID + - :git-hdl:`library/axi_sysid` + - :ref:`here ` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom` + - :ref:`here ` + * - UTIL_I2C_MIXER + - :git-hdl:`library/util_i2c_mixer` + - — + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`[Wiki] AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver ` + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 8f627196e1..cf1c8d1255 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -19,6 +19,7 @@ Contents :maxdepth: 1 AD-GMSL2ETH-SL + AD3552R-EVB AD4110-SDZ AD411x-AD717x AD4134-FMC diff --git a/library/axi_ad35xxr/axi_ad35xxr.v b/library/axi_ad35xxr/axi_ad35xxr.v index 31dac51475..8796ebdfd3 100644 --- a/library/axi_ad35xxr/axi_ad35xxr.v +++ b/library/axi_ad35xxr/axi_ad35xxr.v @@ -133,7 +133,7 @@ module axi_ad35xxr #( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; - assign qspi = (multi_io_mode == 2'd2); //2'd2 is quad spi in multi_io_mode reg + assign qspi_sel = (multi_io_mode == 2'd2); //2'd2 is quad spi in multi_io_mode reg // device interface axi_ad35xxr_if axi_ad35xxr_interface (