From ea052a4cc0602a3281a9f35f6824961ae91ca2f6 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Tue, 10 Dec 2024 11:26:09 +0200 Subject: [PATCH] library: intel: adi_jesd204: adi_jesd204_hw: Fix sip_tile string In quartus 24.2 the 'get_part_info -sip_tile' command also returns the number of tiles which made some of the ifs that were matching on the type of tile fail. Signed-off-by: Bogdan Luncan --- library/intel/adi_jesd204/adi_jesd204_hw.tcl | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl index a774c7bc70d..319d0b52f78 100644 --- a/library/intel/adi_jesd204/adi_jesd204_hw.tcl +++ b/library/intel/adi_jesd204/adi_jesd204_hw.tcl @@ -345,8 +345,9 @@ proc jesd204_compose {} { set data_path_width [get_parameter_value "DATA_PATH_WIDTH"] set link_mode [get_parameter_value "LINK_MODE"] - set sip_tile [quartus::device::get_part_info -sip_tile $device] - + set sip_tile_info [quartus::device::get_part_info -sip_tile $device] + regexp -nocase {([a-z])\-tile} $sip_tile_info -> sip_tile + set sip_tile [string toupper $sip_tile] if {$link_mode == 1} { # jesd204b @@ -442,7 +443,7 @@ proc jesd204_compose {} { add_connection sys_clock.clk_reset link_pll_reset_control.reset add_connection link_pll_reset_control.pll_powerdown link_pll.pll_powerdown - } elseif {$device_family == "Stratix 10" && $sip_tile == "{H-Tile}"} { + } elseif {$device_family == "Stratix 10" && $sip_tile == "H"} { send_message info "Instantiate a fpll_s10_htile for link_pll." add_instance link_pll altera_xcvr_fpll_s10_htile @@ -462,7 +463,7 @@ proc jesd204_compose {} { set outclk_name "outclk_div1" add_connection link_pll.$outclk_name link_clock.in_clk - } elseif {$device_family == "Stratix 10" && $sip_tile == "E-Tile"} { + } elseif {$device_family == "Stratix 10" && $sip_tile == "E"} { ## No fPLL here, PLL embedded in Native PHY