From 872279e1bb56457a9abf62c38596701764edc3fa Mon Sep 17 00:00:00 2001 From: Cristian Mihai Popa Date: Mon, 19 Aug 2024 14:04:02 +0300 Subject: [PATCH 1/3] projects/ad9265_fmc: New carrier Zedboard - Added support for ZedBoard Signed-off-by: Cristian Mihai Popa --- projects/ad9265_fmc/zed/Makefile | 26 +++ projects/ad9265_fmc/zed/system_bd.tcl | 17 ++ projects/ad9265_fmc/zed/system_constr.xdc | 39 ++++ projects/ad9265_fmc/zed/system_project.tcl | 18 ++ projects/ad9265_fmc/zed/system_top.v | 242 +++++++++++++++++++++ 5 files changed, 342 insertions(+) create mode 100644 projects/ad9265_fmc/zed/Makefile create mode 100644 projects/ad9265_fmc/zed/system_bd.tcl create mode 100644 projects/ad9265_fmc/zed/system_constr.xdc create mode 100644 projects/ad9265_fmc/zed/system_project.tcl create mode 100644 projects/ad9265_fmc/zed/system_top.v diff --git a/projects/ad9265_fmc/zed/Makefile b/projects/ad9265_fmc/zed/Makefile new file mode 100644 index 0000000000..d3209d5767 --- /dev/null +++ b/projects/ad9265_fmc/zed/Makefile @@ -0,0 +1,26 @@ +#################################################################################### +## Copyright (c) 2018 - 2024 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9265_fmc_zed + +M_DEPS += ../common/ad9265_spi.v +M_DEPS += ../common/ad9265_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_ad9265 +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9265_fmc/zed/system_bd.tcl b/projects/ad9265_fmc/zed/system_bd.tcl new file mode 100644 index 0000000000..fb2e29a322 --- /dev/null +++ b/projects/ad9265_fmc/zed/system_bd.tcl @@ -0,0 +1,17 @@ +############################################################################### +## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source ../common/ad9265_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file diff --git a/projects/ad9265_fmc/zed/system_constr.xdc b/projects/ad9265_fmc/zed/system_constr.xdc new file mode 100644 index 0000000000..20937df3d6 --- /dev/null +++ b/projects/ad9265_fmc/zed/system_constr.xdc @@ -0,0 +1,39 @@ +############################################################################### +## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ad9265 + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## H4 FMC_CLK0_M2C_P IO_L12P_T1_MRCC_34 +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## H5 FMC_CLK0_M2C_N IO_L12N_T1_MRCC_34 + +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## D14 FMC_LA09_P IO_L17P_T2_34 +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## D15 FMC_LA09_N IO_L17N_T2_34 +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C10 FMC_LA06_P IO_L10P_T1_34 +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C11 FMC_LA06_N IO_L10N_T1_34 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## H13 FMC_LA07_P IO_L21P_T3_DQS_34 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## H14 FMC_LA07_N IO_L21N_T3_DQS_34 +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## G12 FMC_LA08_P IO_L8P_T1_34 +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## G13 FMC_LA08_N IO_L8N_T1_34 +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34 +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34 +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D11 FMC_LA05_P IO_L7P_T1_34 +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D12 FMC_LA05_N IO_L7N_T1_34 +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H7 FMC_LA02_P IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H8 FMC_LA02_N IO_L20N_T3_34 +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G9 FMC_LA03_P IO_L16P_T2_34 +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G10 FMC_LA03_N IO_L16N_T2_34 +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_p] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_n] ; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34 + +# spi + +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## G36 FMC_LA33_P IO_L18P_T2_AD13P_35 +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## G37 FMC_LA33_N IO_L18N_T2_AD13N_35 +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H37 FMC_LA32_P IO_L15P_T2_DQS_AD12P_35 +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H38 FMC_LA32_N IO_L15N_T2_DQS_AD12N_35 + +# clocks + +create_clock -name adc_clk -period 8.000 [get_ports adc_clk_in_p] ; diff --git a/projects/ad9265_fmc/zed/system_project.tcl b/projects/ad9265_fmc/zed/system_project.tcl new file mode 100644 index 0000000000..7808bab297 --- /dev/null +++ b/projects/ad9265_fmc/zed/system_project.tcl @@ -0,0 +1,18 @@ +############################################################################### +## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project ad9265_fmc_zed +adi_project_files ad9265_fmc_zed [list \ + "../common/ad9265_spi.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +adi_project_run ad9265_fmc_zed diff --git a/projects/ad9265_fmc/zed/system_top.v b/projects/ad9265_fmc/zed/system_top.v new file mode 100644 index 0000000000..d37811592b --- /dev/null +++ b/projects/ad9265_fmc/zed/system_top.v @@ -0,0 +1,242 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + input adc_clk_in_n, + input adc_clk_in_p, + input [ 7:0] adc_data_in_n, + input [ 7:0] adc_data_in_p, + input adc_data_or_n, + input adc_data_or_p, + + output spi_clk, + output spi_csn_adc, + output spi_csn_clk, + inout spi_sdio +); + + // internal signals + + wire spi_miso; + wire spi_mosi; + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + wire [ 2:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + wire [ 2:0] spi1_csn; + wire spi1_clk; + wire spi1_mosi; + wire spi1_miso; + + assign gpio_i[63:32] = gpio_o[63:32]; + + assign spi_csn_adc = spi0_csn[0]; + assign spi_csn_clk = spi0_csn[1]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH (32) + ) i_iobuf ( + .dio_t (gpio_t[31:0]), + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + ad9265_spi i_spi ( + .spi_csn(spi0_csn[1:0]), + .spi_clk(spi_clk), + .spi_mosi(spi_mosi), + .spi_miso(spi_miso), + .spi_sdio(spi_sdio)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + + .spdif (spdif), + + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + + .otg_vbusoc (otg_vbusoc), + + .adc_clk_in_n(adc_clk_in_n), + .adc_clk_in_p(adc_clk_in_p), + .adc_data_in_n(adc_data_in_n), + .adc_data_in_p(adc_data_in_p), + .adc_data_or_n(adc_data_or_n), + .adc_data_or_p(adc_data_or_p), + + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_2_o (spi0_csn[2]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi), + .spi1_clk_i (spi1_clk), + .spi1_clk_o (spi1_clk), + .spi1_csn_0_o (spi1_csn[0]), + .spi1_csn_1_o (spi1_csn[1]), + .spi1_csn_2_o (spi1_csn[2]), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b1), + .spi1_sdo_i (spi1_mosi), + .spi1_sdo_o (spi1_mosi)); + +endmodule From 8621391bf3d53be4b026f44ff8fb72e2b2787610 Mon Sep 17 00:00:00 2001 From: Cristian Mihai Popa Date: Mon, 19 Aug 2024 15:02:13 +0300 Subject: [PATCH 2/3] docs/projects/ad9265_fmc: Documentation for AD9265 HDL project Signed-off-by: Cristian Mihai Popa --- .../ad9265_fmc/ad9265_fmc_block_diagram.svg | 1612 +++++++++++++++++ docs/projects/ad9265_fmc/index.rst | 213 +++ docs/projects/index.rst | 1 + 3 files changed, 1826 insertions(+) create mode 100644 docs/projects/ad9265_fmc/ad9265_fmc_block_diagram.svg create mode 100644 docs/projects/ad9265_fmc/index.rst diff --git a/docs/projects/ad9265_fmc/ad9265_fmc_block_diagram.svg b/docs/projects/ad9265_fmc/ad9265_fmc_block_diagram.svg new file mode 100644 index 0000000000..61e65cc667 --- /dev/null +++ b/docs/projects/ad9265_fmc/ad9265_fmc_block_diagram.svg @@ -0,0 +1,1612 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + MEMORY INTERCONNECT + + + + ZC706/ZED + FMC CONNECTOR +   + +   +   +   + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Recive path + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + Zynq SoC + Timer + + + DAC core frame + + + + LVDS INTERFACE + + + + + + AD9265 CORE + + + + + DMA_Clk =100MHz + ADC_Clk =500MHz + + + + + AD9265_DMA + + CLK_IN_P + CLK_IN_N + + 64 + 64 + 64 + adc_data_p[7:0] + adc_data_n[7:0] + + ADC_Clk_in =500MHz +   +   +   +   + + + ADC CHANNEL + + + + + + + + + + + + + + + + + + IQ Corr + + + + + + PNMON + + + DC Filter + + diff --git a/docs/projects/ad9265_fmc/index.rst b/docs/projects/ad9265_fmc/index.rst new file mode 100644 index 0000000000..52c9d3551d --- /dev/null +++ b/docs/projects/ad9265_fmc/index.rst @@ -0,0 +1,213 @@ +.. _ad9265_fmc: + +AD9265-FMC HDL project +================================================================================ + +Overview +------------------------------------------------------------------------------- + +The :adi:`AD9265` is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The +:adi:`AD9265` is designed to support communications applications where high +performance combined with low cost, small size, and versatility is desired. The +ADC core features a multistage, differential pipelined architecture with +integrated output error correction logic to provide 16-bit accuracy at 125 MSPS +data rates and guarantees no missing codes over the full operating temperature +range. The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). +A data output clock is provided to ensure proper latch timing with receiving +logic. The board also provides other options to drive the clock and analog +inputs of the ADC. + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-AD9265 ` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`AD9265` + +Supported carriers +------------------------------------------------------------------------------- + +.. list-table:: + :widths: 35 35 30 + :header-rows: 1 + + * - Evaluation board + - Carrier + - FMC slot + * - :adi:`EVAL-AD9265-FMC-500EBZ ` + - :xilinx:`ZC706` + - FMC LPC + * - + - :xilinx:`ZedBoard ` + - FMC LPC + +Block design +------------------------------------------------------------------------------- + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: ad9265_fmc_block_diagram.svg + :width: 800 + :align: center + :alt: AD9265/ZedBoard block diagram + +Clock scheme +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There are 3 ways to configure the clock source for :adi:`AD9265`: + +- External passive clock (default) +- Optional active clock path using the :adi:`AD9517` +- Optional oscillator + +For more details, check :adi:`AD9265` schematic. + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture`). + +Check-out the table below to find out the conditions. + +==================== =============== +Instance Zynq/Microblaze +==================== =============== +axi_ad9265 0x44A00000 +axi_ad9265_dma 0x44A30000 +==================== =============== + +SPI connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PS + - SPI 0 + - AD9517 + - 1 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +.. list-table:: + :widths: 30 10 15 15 + :header-rows: 1 + + * - Instance name + - HDL + - Linux Zynq + - Actual Zynq + * - axi_ad9265_dma + - 13 + - 57 + - 89 + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository. + +Then go to the project location (**projects/ad9265_fmc/carrier**) and run the +make command by typing in your command prompt(this example :xilinx:`ZC706`): + +**Linux/Cygwin/WSL** + +.. code-block:: + + user@analog:~$ cd hdl/projects/ad9265_fmc/zc706 + user@analog:~/hdl/projects/ad9265_fmc/zc706$ make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Resources +------------------------------------------------------------------------------- + +Systems related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Here you can find the quick start guides available for these evaluation boards: + +.. list-table:: + :widths: 20 10 + :header-rows: 1 + + * - Evaluation board + - Zynq-7000 + * - AD9265-FMC + - :dokuwiki:`ZC706 ` + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: :adi:`AD9265` +- :dokuwiki:`Evaluating AD9265, user guide ` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`AD9265-FMC HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_AD9265 + - :git-hdl:`library/axi_ad9265 ` + - :ref:`here ` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac ` + - :ref:`here ` + * - AXI_CLKGEN + - :git-hdl:`library/axi_clkgen ` + - :ref:`here ` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx ` + - :ref:`here ` + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx ` + - --- + * - AXI_I2S_ADI + - :git-hdl:`library/axi_sysid ` + - --- + * - AXI_SYSID + - :git-hdl:`library/axi_sysid ` + - :ref:`here ` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom ` + - :ref:`here ` + * - UTIL_I2C_MIXER + - :git-hdl:`library/util_i2c_mixer ` + - :ref:`here ` + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-linux:`Linux device tree zynq-zc706-adv7511-ad9265-fmc-125ebz.dts ` +- :git-linux:`Linux driver ad9467.c ` + (used for AD9265-FMC as well) + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/docs/projects/index.rst b/docs/projects/index.rst index d741817d64..77e1641aa7 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -33,6 +33,7 @@ Contents AD7616-SDZ AD7768-EVB AD9081/AD9082/AD9986/AD9988 + AD9265-FMC AD9434-FMC AD9739A-FMC AD9783-EBZ From 90768591283b337239d0bd8c31f8c097900591cc Mon Sep 17 00:00:00 2001 From: Cristian Mihai Popa Date: Mon, 19 Aug 2024 17:40:32 +0300 Subject: [PATCH 3/3] docs/projects/ad9265_fmc: Fixed the mistakes pointed in the PR Signed-off-by: Cristian Mihai Popa --- docs/projects/ad9265_fmc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/projects/ad9265_fmc/index.rst b/docs/projects/ad9265_fmc/index.rst index 52c9d3551d..8a10d076fb 100644 --- a/docs/projects/ad9265_fmc/index.rst +++ b/docs/projects/ad9265_fmc/index.rst @@ -159,7 +159,7 @@ Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Product datasheets: :adi:`AD9265` -- :dokuwiki:`Evaluating AD9265, user guide ` +- :dokuwiki:`[Wiki] Evaluating AD9265, user guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~