diff --git a/docs/projects/ad4052_ardz/ad4052_hdl.svg b/docs/projects/ad4052_ardz/ad4052_hdl.svg
new file mode 100644
index 0000000000..892f7a2a34
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+++ b/docs/projects/ad4052_ardz/ad4052_hdl.svg
@@ -0,0 +1,2618 @@
+
+
+
+
diff --git a/docs/projects/ad4052_ardz/index.rst b/docs/projects/ad4052_ardz/index.rst
new file mode 100644
index 0000000000..efc93881b1
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+++ b/docs/projects/ad4052_ardz/index.rst
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+.. _ad4052-ardz:
+
+AD4052-ARDZ HDL project
+================================================================================
+
+Overview
+--------------------------------------------------------------------------------
+
+The HDL reference design for the :adi:`AD4050`, :adi:`AD4052`, :adi:`AD4056`, and
+:adi:`AD4058` .
+They are versatile, 16-bit/12-bit, successive approximation register (SAR)
+analog-to-digital converters (ADCs) that enable low-power, high-density data
+acquisition solutions without sacrificing precision. These ADCs offer a unique
+balance of performance and power efficiency, plus innovative features for
+seamlessly switching between high-resolution and low-power modes tailored to the
+immediate needs of the system.
+
+The :adi:`AD4050`/:adi:`AD4052`/:adi:`AD4056`/:adi:`AD4058` are ideal for
+battery-powered, compact data acquisition and edge sensing applications.
+
+The :adi:`EVAL-AD4050-ARDZ`/:adi:`EVAL-AD4052-ARDZ` evaluation boards enable
+quick and easy evaluation of the performance and features of the :adi:`AD4050`
+or the :adi:`AD4052`, respectively.
+The AD4050 and AD4052 are compact, low power, 12-bit or 16-bit (respectively)
+Easy Drive successive approximation register (SAR) analog-to-digital converters
+(ADCs).
+
+This project has a :ref:`spi_engine` instance to control and acquire data from
+the precision ADC.
+This instance provides support for capturing continuous samples at the maximum
+sample rate.
+
+Supported boards
+-------------------------------------------------------------------------------
+
+- :adi:`EVAL-AD4050-ARDZ`
+- :adi:`EVAL-AD4052-ARDZ`
+
+Supported devices
+-------------------------------------------------------------------------------
+
+- :adi:`AD4050`
+- :adi:`AD4052`
+- :adi:`AD4056`
+- :adi:`AD4058`
+
+Supported carriers
+-------------------------------------------------------------------------------
+
+- :xilinx:`Cora Z7-07S `
+ Arduino shield connector
+- :intel:`DE10-Nano `
+ Arduino shield connector
+
+Block design
+-------------------------------------------------------------------------------
+
+The data path and clock domains are depicted in the below diagram:
+
+.. image:: ad4052_hdl.svg
+ :width: 800
+ :align: center
+ :alt: AD4052-ARDZ block diagram
+
+CPU/Memory interconnects addresses
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The addresses are dependent on the architecture of the FPGA, having an offset
+added to the base address from HDL (see more at :ref:`architecture`).
+
+.. table:: Cora Z7S
+
+ ======================== ===========
+ Instance Address
+ ======================== ===========
+ spi_adc_axi_regmap 0x44A0_0000
+ spi_adc_dmac 0x44A3_0000
+ axi_iic_eeprom 0x44A4_0000
+ spi_clkgen 0x44A7_0000
+ adc_trigger_gen 0x44B0_0000
+ ======================== ===========
+
+.. table:: DE10-Nano
+
+ ======================== ===========
+ Instance Address
+ ======================== ===========
+ axi_dmac_0 0x0002_0000
+ axi_spi_engine_0 0x0003_0000
+ pwm_trigger 0x0004_0000
+ spi_clk_pll_reconfig 0x0005_0000
+ ======================== ===========
+
+I2C connections
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table:: Cora Z7s
+ :header-rows: 1
+
+ * - I2C type
+ - I2C manager instance
+ - Alias
+ - Address
+ - Device Address
+ - I2C subordinate
+ * - PS
+ - axi_iic_eeprom
+ - axi_iic_eeprom_io
+ - 0x44A4_0000
+ - 0x52
+ - EEPROM
+
+.. list-table:: DE10-Nano
+ :header-rows: 1
+
+ * - I2C type
+ - I2C manager instance
+ - Alias
+ - Address
+ - Device Address
+ - I2C subordinate
+ * - PS
+ - i2c1
+ - sys_hps_i2c1
+ - ---
+ - 0x52
+ - ---
+
+Device address considering the EEPROM address pins ``A0=0``, ``A1=1``, ``A2=0``.
+
+SPI connections
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table::
+ :widths: 25 25 25 25
+ :header-rows: 1
+
+ * - SPI type
+ - SPI manager instance
+ - SPI subordinate
+ - CS
+ * - PL
+ - axi_spi_engine
+ - ad4052
+ - 0
+
+GPIOs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Software GPIO number is calculated as follows:
+
+- Cora Z7S: the offset is 54
+
+.. list-table::
+ :widths: 25 25 25 25
+ :header-rows: 2
+
+ * - GPIO signal
+ - Direction
+ - HDL GPIO EMIO
+ - Software GPIO
+ * -
+ - (from FPGA view)
+ -
+ - Zynq-7000
+ * - adc_cnv
+ - OUTPUT
+ - 34
+ - 88
+ * - adc_gp1
+ - INOUT
+ - 33
+ - 87
+ * - adc_gp0
+ - INOUT
+ - 32
+ - 86
+
+- DE10-Nano: the offset is 32
+
+.. list-table::
+ :widths: 25 25 25 25
+ :header-rows: 2
+
+ * - GPIO signal
+ - Direction
+ - HDL GPIO EMIO
+ - Software GPIO
+ * -
+ - (from FPGA view)
+ -
+ - DE10-Nano
+ * - adc_cnv
+ - OUTPUT
+ - 34
+ - 2
+ * - adc_gp1
+ - INPUT
+ - 33
+ - 1
+ * - adc_gp0
+ - INPUT
+ - 32
+ - 0
+
+Interrupts
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Below are the Programmable Logic interrupts used in this project.
+
+=================== === ========== ===========
+Instance name HDL Linux Zynq Actual Zynq
+=================== === ========== ===========
+axi_adc_dma 13 57 89
+spi_adc_axi_regmap 12 56 88
+axi_iic_eeprom 11 55 87
+=================== === ========== ===========
+
+================ === =============== ================
+Instance name HDL Linux DE10-Nano Actual DE10-Nano
+================ === =============== ================
+axi_dmac_0 4 44 76
+axi_spi_engine_0 3 43 75
+================ === =============== ================
+
+Building the HDL project
+-------------------------------------------------------------------------------
+
+The design is built upon ADI's generic HDL reference design framework.
+ADI distributes the bit/elf files of these projects as part of the
+:dokuwiki:`ADI Kuiper Linux `.
+If you want to build the sources, ADI makes them available on the
+:git-hdl:`HDL repository `. To get the source you must
+`clone `__
+the HDL repository, and then build the project as follows:
+
+**Linux/Cygwin/WSL**
+
+.. shell::
+
+ $cd hdl/projects/ad4052_ardz/coraz7s
+ $make
+
+.. shell::
+
+ $cd hdl/projects/ad4052_ardz/de10nano
+ $make
+
+A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
+
+Resources
+-------------------------------------------------------------------------------
+
+Hardware related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Product datasheets:
+
+ - :adi:`AD4050`
+ - :adi:`AD4052`
+
+HDL related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- :git-hdl:`AD4052-ARDZ HDL project source code `
+
+.. list-table::
+ :widths: 30 35 35
+ :header-rows: 1
+
+ * - IP name
+ - Source code link
+ - Documentation link
+ * - AXI_PWM_GEN
+ - :git-hdl:`library/axi_pwm_gen `
+ - :ref:`here `
+ * - AXI_CLKGEN
+ - :git-hdl:`library/axi_dmac ` *
+ - :ref:`here `
+ * - AXI_DMAC
+ - :git-hdl:`library/axi_dmac `
+ - :ref:`here `
+ * - AXI_HDMI_TX
+ - :git-hdl:`library/axi_hdmi_tx ` **
+ - :ref:`here `
+ * - AXI_SYSID
+ - :git-hdl:`library/axi_sysid `
+ - :ref:`here `
+ * - AXI_SPI_ENGINE
+ - :git-hdl:`library/spi_engine/axi_spi_engine `
+ - :ref:`here `
+ * - SPI_ENGINE_EXECUTION
+ - :git-hdl:`library/spi_engine/spi_engine_execution `
+ - :ref:`here `
+ * - SPI_ENGINE_INTERCONNECT
+ - :git-hdl:`library/spi_engine/spi_engine_interconnect `
+ - :ref:`here `
+ * - SPI_ENGINE_OFFLOAD
+ - :git-hdl:`library/spi_engine/spi_engine_offload`
+ - :ref:`here `
+ * - SYSID_ROM
+ - :git-hdl:`library/sysid_rom `
+ - :ref:`here `
+
+.. admonition:: Legend
+ :class: note
+
+ - ``*`` instantiated only for Cora Z7S
+ - ``**`` instantiated only for DE10-Nano
+
+- :ref:`SPI Engine Framework documentation `
+
+Software related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- :git-linux:`AD4052 Linux driver ad4052.c `
+
+.. include:: ../common/more_information.rst
+
+.. include:: ../common/support.rst
diff --git a/docs/projects/index.rst b/docs/projects/index.rst
index 8fa7c61b11..2441c06434 100644
--- a/docs/projects/index.rst
+++ b/docs/projects/index.rst
@@ -25,6 +25,7 @@ Contents
AD411x-AD717x
AD4134-FMC
AD4170-ASDZ
+ AD4052-ARDZ
AD4630-FMC/AD4030-FMC/ADAQ4224-FMC
AD469X-EVB
AD485X-FMCZ
diff --git a/projects/ad4052_ardz/Makefile b/projects/ad4052_ardz/Makefile
new file mode 100644
index 0000000000..6667c4f442
--- /dev/null
+++ b/projects/ad4052_ardz/Makefile
@@ -0,0 +1,7 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+include ../scripts/project-toplevel.mk
diff --git a/projects/ad4052_ardz/Readme.md b/projects/ad4052_ardz/Readme.md
new file mode 100755
index 0000000000..62dd9f0dfb
--- /dev/null
+++ b/projects/ad4052_ardz/Readme.md
@@ -0,0 +1,19 @@
+# AD4052-ARDZ HDL Project
+
+Here are some pointers to help you:
+ * [Board Product Page](https://www.analog.com/eval-ad4050-ardz)
+ * [Board Product Page](https://www.analog.com/eval-ad4052-ardz)
+ * Parts : [AD4050: Compact, Low Power, 12-Bit, 500 kSPS Easy Drive SAR ADC](https://www.analog.com/ad4050)
+ * Parts : [AD4052: Compact, Low Power, 16-Bit, 2 MSPS Easy Drive SAR ADC](https://www.analog.com/ad4052)
+ * Parts : [AD4056: Compact, Low Power, 12-Bit, 500 kSPS Easy Drive SAR ADC](https://www.analog.com/ad4056)
+ * Parts : [AD4058: Compact, Low Power, 16-Bit, 2 MSPS Easy Drive SAR ADC](https://www.analog.com/ad4058)
+
+ * HDL Doc: https://analogdevicesinc.github.io/hdl/projects/ad4052_ardz/index.html
+ * Linux Drivers: https://github.com/analogdevicesinc/linux/tree/staging/ad4052/drivers/iio/adc/ad4052.c
+
+## Supported parts
+
+ * AD4050
+ * AD4052
+ * AD4056
+ * AD4058
diff --git a/projects/ad4052_ardz/common/ad4052_bd.tcl b/projects/ad4052_ardz/common/ad4052_bd.tcl
new file mode 100644
index 0000000000..0b01a486e0
--- /dev/null
+++ b/projects/ad4052_ardz/common/ad4052_bd.tcl
@@ -0,0 +1,74 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_bd_port -dir O adc_cnv
+create_bd_port -dir I adc_gp1_n
+create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
+
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 1
+set num_sdo 1
+set sdi_delay 1
+set echo_sclk 0
+
+set hier_spi_engine spi_adc
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+
+ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1
+
+ad_ip_instance axi_clkgen spi_clkgen
+ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
+ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
+ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 9
+
+ad_ip_instance axi_pwm_gen adc_trigger_gen
+ad_ip_parameter adc_trigger_gen CONFIG.PULSE_0_PERIOD 120
+ad_ip_parameter adc_trigger_gen CONFIG.PULSE_0_WIDTH 1
+
+# dma to receive data stream
+ad_ip_instance axi_dmac axi_adc_dma
+ad_ip_parameter axi_adc_dma CONFIG.DMA_TYPE_SRC 1
+ad_ip_parameter axi_adc_dma CONFIG.DMA_TYPE_DEST 0
+ad_ip_parameter axi_adc_dma CONFIG.CYCLIC 0
+ad_ip_parameter axi_adc_dma CONFIG.SYNC_TRANSFER_START 0
+ad_ip_parameter axi_adc_dma CONFIG.AXI_SLICE_SRC 0
+ad_ip_parameter axi_adc_dma CONFIG.AXI_SLICE_DEST 1
+ad_ip_parameter axi_adc_dma CONFIG.DMA_2D_TRANSFER 0
+ad_ip_parameter axi_adc_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
+ad_ip_parameter axi_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64
+
+ad_connect $sys_cpu_clk spi_clkgen/clk
+ad_connect spi_clk spi_clkgen/clk_0
+
+ad_connect spi_clk adc_trigger_gen/ext_clk
+ad_connect $sys_cpu_clk adc_trigger_gen/s_axi_aclk
+ad_connect sys_cpu_resetn adc_trigger_gen/s_axi_aresetn
+ad_connect $hier_spi_engine/trigger adc_gp1_n
+ad_connect adc_trigger_gen/pwm_0 adc_cnv
+
+ad_connect axi_adc_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
+ad_connect $hier_spi_engine/m_spi adc_spi
+
+ad_connect $sys_cpu_clk $hier_spi_engine/clk
+ad_connect spi_clk $hier_spi_engine/spi_clk
+ad_connect spi_clk axi_adc_dma/s_axis_aclk
+ad_connect sys_cpu_resetn $hier_spi_engine/resetn
+ad_connect sys_cpu_resetn axi_adc_dma/m_dest_axi_aresetn
+
+ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
+ad_cpu_interconnect 0x44a30000 axi_adc_dma
+ad_cpu_interconnect 0x44a70000 spi_clkgen
+ad_cpu_interconnect 0x44b00000 adc_trigger_gen
+
+ad_cpu_interrupt "ps-13" "mb-13" axi_adc_dma/irq
+ad_cpu_interrupt "ps-12" "mb-12" /$hier_spi_engine/irq
+
+ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
+ad_mem_hp1_interconnect $sys_cpu_clk axi_adc_dma/m_dest_axi
diff --git a/projects/ad4052_ardz/common/ad4052_qsys.tcl b/projects/ad4052_ardz/common/ad4052_qsys.tcl
new file mode 100644
index 0000000000..bd57a4a1aa
--- /dev/null
+++ b/projects/ad4052_ardz/common/ad4052_qsys.tcl
@@ -0,0 +1,177 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# receive dma
+add_instance axi_dmac_0 axi_dmac
+set_instance_parameter_value axi_dmac_0 {DMA_TYPE_SRC} {1}
+set_instance_parameter_value axi_dmac_0 {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
+set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
+set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
+
+# axi_spi_engine
+
+add_instance axi_spi_engine_0 axi_spi_engine
+set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
+set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32}
+set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0}
+set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1}
+set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1}
+
+# spi_engine_execution
+
+add_instance spi_engine_execution_0 spi_engine_execution
+set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
+set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
+set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
+
+# spi_engine_interconnect
+
+add_instance spi_engine_interconnect_0 spi_engine_interconnect
+set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
+set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
+
+# spi_engine_offload
+
+add_instance spi_engine_offload_0 spi_engine_offload
+set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1}
+set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
+set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32}
+set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1}
+
+# axi_pwm_gen
+
+add_instance pwm_trigger axi_pwm_gen
+set_instance_parameter_value pwm_trigger {PULSE_0_PERIOD} {120}
+set_instance_parameter_value pwm_trigger {PULSE_0_WIDTH} {1}
+
+# spi_clk pll
+
+add_instance spi_clk_pll altera_pll
+set_instance_parameter_value spi_clk_pll {gui_feedback_clock} {Global Clock}
+set_instance_parameter_value spi_clk_pll {gui_operation_mode} {direct}
+set_instance_parameter_value spi_clk_pll {gui_number_of_clocks} {1}
+set_instance_parameter_value spi_clk_pll {gui_output_clock_frequency0} {150}
+set_instance_parameter_value spi_clk_pll {gui_phase_shift0} {0}
+set_instance_parameter_value spi_clk_pll {gui_phase_shift1} {0}
+set_instance_parameter_value spi_clk_pll {gui_phase_shift_deg0} {0.0}
+set_instance_parameter_value spi_clk_pll {gui_phase_shift_deg1} {0.0}
+set_instance_parameter_value spi_clk_pll {gui_phout_division} {1}
+set_instance_parameter_value spi_clk_pll {gui_pll_auto_reset} {Off}
+set_instance_parameter_value spi_clk_pll {gui_pll_bandwidth_preset} {Auto}
+set_instance_parameter_value spi_clk_pll {gui_pll_mode} {Fractional-N PLL}
+set_instance_parameter_value spi_clk_pll {gui_ps_units0} {ps}
+set_instance_parameter_value spi_clk_pll {gui_refclk_switch} {0}
+set_instance_parameter_value spi_clk_pll {gui_reference_clock_frequency} {50.0}
+set_instance_parameter_value spi_clk_pll {gui_switchover_delay} {0}
+set_instance_parameter_value spi_clk_pll {gui_en_reconf} {1}
+
+add_instance spi_clk_pll_reconfig altera_pll_reconfig
+set_instance_parameter_value spi_clk_pll_reconfig {ENABLE_BYTEENABLE} {0}
+set_instance_parameter_value spi_clk_pll_reconfig {ENABLE_MIF} {0}
+set_instance_parameter_value spi_clk_pll_reconfig {MIF_FILE_NAME} {}
+
+add_connection spi_clk_pll.reconfig_from_pll spi_clk_pll_reconfig.reconfig_from_pll
+set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll endPort {}
+set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll endPortLSB {0}
+set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll startPort {}
+set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll startPortLSB {0}
+set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll width {0}
+
+add_connection spi_clk_pll.reconfig_to_pll spi_clk_pll_reconfig.reconfig_to_pll
+set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll endPort {}
+set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll endPortLSB {0}
+set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPort {}
+set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
+set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
+
+# exported interface
+
+add_interface adc_spi_sclk clock source
+add_interface adc_spi_sdi conduit end
+add_interface adc_spi_sdo conduit end
+add_interface adc_spi_cs conduit end
+add_interface adc_drdy conduit end
+
+set_interface_property adc_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk
+set_interface_property adc_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi
+set_interface_property adc_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo
+set_interface_property adc_spi_cs EXPORT_OF spi_engine_execution_0.if_cs
+set_interface_property adc_drdy_trigger EXPORT_OF spi_engine_offload_0.if_trigger
+set_interface_property adc_cnv EXPORT_OF pwm_trigger.if_pwm_0
+
+# clocks
+
+add_connection sys_clk.clk spi_clk_pll.refclk
+add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
+add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
+add_connection sys_clk.clk axi_dmac_0.s_axi_clock
+add_connection sys_clk.clk pwm_trigger.s_axi_clock
+
+add_connection spi_clk_pll.outclk0 pwm_trigger.if_ext_clk
+add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk
+add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk
+add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk
+add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk
+add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk
+add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk
+
+add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
+
+# resets
+
+add_connection sys_clk.clk_reset spi_clk_pll.reset
+add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
+add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
+add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
+add_connection sys_clk.clk_reset pwm_trigger.s_axi_reset
+
+add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
+add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
+add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
+
+add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
+
+# interfaces
+
+add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
+add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
+add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
+add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
+
+add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s0_cmd
+add_connection spi_engine_interconnect_0.s0_sdi axi_spi_engine_0.sdi_data
+add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s0_sdo
+add_connection spi_engine_interconnect_0.s0_sync axi_spi_engine_0.sync
+
+add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s1_cmd
+add_connection spi_engine_interconnect_0.s1_sdi spi_engine_offload_0.sdi_data
+add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s1_sdo
+add_connection spi_engine_interconnect_0.s1_sync spi_engine_offload_0.sync
+
+add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd
+add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo
+add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable
+add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled
+add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
+add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync
+
+add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+
+# cpu interconnects
+
+ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
+ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00040000 pwm_trigger.s_axi
+ad_cpu_interconnect 0x00050000 spi_clk_pll_reconfig.mgmt_avalon_slave
+
+# dma interconnect
+
+ad_dma_interconnect axi_dmac_0.m_dest_axi
+
+#interrupts
+
+ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
+ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
diff --git a/projects/ad4052_ardz/common/eval_ad4052_ardz.txt b/projects/ad4052_ardz/common/eval_ad4052_ardz.txt
new file mode 100644
index 0000000000..7c464fed92
--- /dev/null
+++ b/projects/ad4052_ardz/common/eval_ad4052_ardz.txt
@@ -0,0 +1,13 @@
+Header/Pin Schematic_name Device.Pin System_top_name IOSTANDARD Termination
+
+# eval_ad4052_ardz
+
+P3.10 SCL_ARD EEPROM.SCL iic_eeprom_scl LVCMOS33 #N/A
+P3.9 SDA_ARD EEPROM.SDA iic_eeprom_sda LVCMOS33 #N/A
+P3.6 SCLK_ARD AD4052.SCLK adc_spi_sclk LVCMOS33 IOB TRUE
+P3.5 MISO_ARD AD4052.SDO adc_spi_sdi LVCMOS33 IOB TRUE
+P3.4 MOSI_ARD AD4052.SDI adc_spi_sdo LVCMOS33 IOB TRUE
+P3.3 CSB_ARD AD4052.CSB adc_spi_cs LVCMOS33 IOB TRUE
+P4.7 CNV_ARD AD4052.CNV adc_spi_cnv LVCMOS33 IOB TRUE
+P3.2 D9_ARD AD4052.GP0 adc_spi_gpio0 LVCMOS33 #N/A
+P3.1 D8_ARD AD4052.GP1 adc_spi_gpio1 LVCMOS33 #N/A
diff --git a/projects/ad4052_ardz/coraz7s/Makefile b/projects/ad4052_ardz/coraz7s/Makefile
new file mode 100644
index 0000000000..7119cb108f
--- /dev/null
+++ b/projects/ad4052_ardz/coraz7s/Makefile
@@ -0,0 +1,27 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad4052_ardz_coraz7s
+
+M_DEPS += ../common/ad4052_bd.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
+M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
+M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_pwm_gen
+LIB_DEPS += axi_sysid
+LIB_DEPS += spi_engine/axi_spi_engine
+LIB_DEPS += spi_engine/spi_engine_execution
+LIB_DEPS += spi_engine/spi_engine_interconnect
+LIB_DEPS += spi_engine/spi_engine_offload
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-xilinx.mk
diff --git a/projects/ad4052_ardz/coraz7s/system_bd.tcl b/projects/ad4052_ardz/coraz7s/system_bd.tcl
new file mode 100644
index 0000000000..f42bfda557
--- /dev/null
+++ b/projects/ad4052_ardz/coraz7s/system_bd.tcl
@@ -0,0 +1,15 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+source ../common/ad4052_bd.tcl
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file
diff --git a/projects/ad4052_ardz/coraz7s/system_constr.xdc b/projects/ad4052_ardz/coraz7s/system_constr.xdc
new file mode 100644
index 0000000000..f63e2c8cac
--- /dev/null
+++ b/projects/ad4052_ardz/coraz7s/system_constr.xdc
@@ -0,0 +1,23 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# ADC SPI interface
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports adc_spi_sclk] ; ## Arduino_IO13
+set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports adc_spi_sdi] ; ## Arduino_IO12
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports adc_spi_sdo] ; ## Arduino_IO11
+set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports adc_spi_cs] ; ## Arduino_IO10
+set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports adc_cnv] ; ## Arduino_IO06
+set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports adc_gp0] ; ## Arduino_IO09
+set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports adc_gp1] ; ## Arduino_IO08
+
+# rename auto-generated clock for SPIEngine to spi_clk - 160MHz
+# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
+create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
+
+# relax the SDO path to help closing timing at high frequencies
+set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
+set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
+set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
+set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
diff --git a/projects/ad4052_ardz/coraz7s/system_project.tcl b/projects/ad4052_ardz/coraz7s/system_project.tcl
new file mode 100755
index 0000000000..860b4cc888
--- /dev/null
+++ b/projects/ad4052_ardz/coraz7s/system_project.tcl
@@ -0,0 +1,18 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project ad4052_ardz_coraz7s
+
+adi_project_files ad4052_ardz_coraz7s [list \
+ "$ad_hdl_dir/library/common/ad_iobuf.v" \
+ "system_top.v" \
+ "system_constr.xdc" \
+ "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
+
+adi_project_run ad4052_ardz_coraz7s
diff --git a/projects/ad4052_ardz/coraz7s/system_top.v b/projects/ad4052_ardz/coraz7s/system_top.v
new file mode 100644
index 0000000000..61cc0f1ce9
--- /dev/null
+++ b/projects/ad4052_ardz/coraz7s/system_top.v
@@ -0,0 +1,173 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+// 1. The GNU General Public License version 2 as published by the
+// Free Software Foundation, which can be found in the top level directory
+// of this repository (LICENSE_GPL2), and also online at:
+//
+//
+// OR
+//
+// 2. An ADI specific BSD license, which can be found in the top level directory
+// of this repository (LICENSE_ADIBSD), and also on-line at:
+// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+// This will allow to generate bit files and not release the source code,
+// as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+ inout [14:0] ddr_addr,
+ inout [ 2:0] ddr_ba,
+ inout ddr_cas_n,
+ inout ddr_ck_n,
+ inout ddr_ck_p,
+ inout ddr_cke,
+ inout ddr_cs_n,
+ inout [ 3:0] ddr_dm,
+ inout [31:0] ddr_dq,
+ inout [ 3:0] ddr_dqs_n,
+ inout [ 3:0] ddr_dqs_p,
+ inout ddr_odt,
+ inout ddr_ras_n,
+ inout ddr_reset_n,
+ inout ddr_we_n,
+
+ inout fixed_io_ddr_vrn,
+ inout fixed_io_ddr_vrp,
+ inout [53:0] fixed_io_mio,
+ inout fixed_io_ps_clk,
+ inout fixed_io_ps_porb,
+ inout fixed_io_ps_srstb,
+
+ inout [ 1:0] btn,
+ inout [ 5:0] led,
+
+ inout iic_ard_scl,
+ inout iic_ard_sda,
+
+ output adc_spi_sclk,
+ input adc_spi_sdi,
+ output adc_spi_sdo,
+ output adc_spi_cs,
+ output adc_cnv,
+ inout adc_gp1,
+ inout adc_gp0
+);
+
+ // internal signals
+
+ wire [63:0] gpio_i;
+ wire [63:0] gpio_o;
+ wire [63:0] gpio_t;
+ wire adc_cnv_w;
+ wire adc_gp1_n = ~adc_gp1;
+
+ // instantiations
+
+ assign gpio_i[31:8] = gpio_o[31:8];
+ assign gpio_i[63:35] = gpio_o[63:35];
+
+ assign adc_cnv = adc_cnv_w | (gpio_o[34] & ~gpio_t[34]);
+ assign gpio_i[34] = adc_cnv;
+
+ ad_iobuf #(
+ .DATA_WIDTH(2)
+ ) i_iobuf_gp (
+ .dio_t(gpio_t[33:32]),
+ .dio_i(gpio_o[33:32]),
+ .dio_o(gpio_i[33:32]),
+ .dio_p({adc_gp1, // device ready then ~data ready
+ adc_gp0})); // threshold event
+
+ ad_iobuf #(
+ .DATA_WIDTH(2)
+ ) i_iobuf_buttons (
+ .dio_t(gpio_t[1:0]),
+ .dio_i(gpio_o[1:0]),
+ .dio_o(gpio_i[1:0]),
+ .dio_p(btn));
+
+ ad_iobuf #(
+ .DATA_WIDTH(6)
+ ) i_iobuf_leds (
+ .dio_t(gpio_t[7:2]),
+ .dio_i(gpio_o[7:2]),
+ .dio_o(gpio_i[7:2]),
+ .dio_p(led));
+
+ system_wrapper i_system_wrapper (
+ .ddr_addr (ddr_addr),
+ .ddr_ba (ddr_ba),
+ .ddr_cas_n (ddr_cas_n),
+ .ddr_ck_n (ddr_ck_n),
+ .ddr_ck_p (ddr_ck_p),
+ .ddr_cke (ddr_cke),
+ .ddr_cs_n (ddr_cs_n),
+ .ddr_dm (ddr_dm),
+ .ddr_dq (ddr_dq),
+ .ddr_dqs_n (ddr_dqs_n),
+ .ddr_dqs_p (ddr_dqs_p),
+ .ddr_odt (ddr_odt),
+ .ddr_ras_n (ddr_ras_n),
+ .ddr_reset_n (ddr_reset_n),
+ .ddr_we_n (ddr_we_n),
+ .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+ .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+ .fixed_io_mio (fixed_io_mio),
+ .fixed_io_ps_clk (fixed_io_ps_clk),
+ .fixed_io_ps_porb (fixed_io_ps_porb),
+ .fixed_io_ps_srstb (fixed_io_ps_srstb),
+ .gpio_i (gpio_i),
+ .gpio_o (gpio_o),
+ .gpio_t (gpio_t),
+ .spi0_clk_i (1'b0),
+ .spi0_clk_o (),
+ .spi0_csn_0_o (),
+ .spi0_csn_1_o (),
+ .spi0_csn_2_o (),
+ .spi0_csn_i (1'b1),
+ .spi0_sdi_i (1'b0),
+ .spi0_sdo_i (1'b0),
+ .spi0_sdo_o (),
+ .spi1_clk_i (1'b0),
+ .spi1_clk_o (),
+ .spi1_csn_0_o (),
+ .spi1_csn_1_o (),
+ .spi1_csn_2_o (),
+ .spi1_csn_i (1'b1),
+ .spi1_sdi_i (1'b0),
+ .spi1_sdo_i (1'b0),
+ .spi1_sdo_o (),
+ .iic_ard_scl_io(iic_ard_scl),
+ .iic_ard_sda_io(iic_ard_sda),
+ .adc_spi_sclk(adc_spi_sclk),
+ .adc_spi_sdi(adc_spi_sdi),
+ .adc_spi_sdo(adc_spi_sdo),
+ .adc_spi_cs(adc_spi_cs),
+ .adc_spi_sdo_t(),
+ .adc_spi_three_wire(),
+ .adc_cnv(adc_cnv_w),
+ .adc_gp1_n(adc_gp1_n));
+
+endmodule
diff --git a/projects/ad4052_ardz/de10nano/Makefile b/projects/ad4052_ardz/de10nano/Makefile
new file mode 100644
index 0000000000..6bb8191415
--- /dev/null
+++ b/projects/ad4052_ardz/de10nano/Makefile
@@ -0,0 +1,24 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad4052_ardz_de10nano
+
+M_DEPS += ../common/ad4052_qsys.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl
+M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl
+
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_pwm_gen
+LIB_DEPS += axi_sysid
+LIB_DEPS += spi_engine/axi_spi_engine
+LIB_DEPS += spi_engine/spi_engine_execution
+LIB_DEPS += spi_engine/spi_engine_interconnect
+LIB_DEPS += spi_engine/spi_engine_offload
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-intel.mk
diff --git a/projects/ad4052_ardz/de10nano/system_constr.sdc b/projects/ad4052_ardz/de10nano/system_constr.sdc
new file mode 100644
index 0000000000..85c9d05c67
--- /dev/null
+++ b/projects/ad4052_ardz/de10nano/system_constr.sdc
@@ -0,0 +1,10 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
+create_clock -period "16.666 ns" -name usb1_clk [get_ports {usb1_clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty
diff --git a/projects/ad4052_ardz/de10nano/system_project.tcl b/projects/ad4052_ardz/de10nano/system_project.tcl
new file mode 100644
index 0000000000..c8c3bec046
--- /dev/null
+++ b/projects/ad4052_ardz/de10nano/system_project.tcl
@@ -0,0 +1,44 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+set REQUIRED_QUARTUS_VERSION 22.1std.0
+set QUARTUS_PRO_ISUSED 0
+source ../../../scripts/adi_env.tcl
+source ../../scripts/adi_project_intel.tcl
+
+adi_project ad4052_ardz_de10nano
+
+source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl
+
+# eeprom
+
+set_location_assignment PIN_AH9 -to i2c_sda ; ## Arduino_SDA
+set_location_assignment PIN_AG11 -to i2c_scl ; ## Arduino_SCL
+
+# ad4052 interface
+
+set_location_assignment PIN_AH12 -to adc_spi_sclk ; ## Arduino_IO13
+set_location_assignment PIN_AH11 -to adc_spi_sdi ; ## Arduino_IO12
+set_location_assignment PIN_AG16 -to adc_spi_sdo ; ## Arduino_IO11
+set_location_assignment PIN_AF15 -to adc_spi_cs ; ## Arduino_IO10
+set_location_assignment PIN_AG8 -to adc_cnv ; ## Arduino_IO06
+set_location_assignment PIN_AE15 -to adc_gp0 ; ## Arduino_IO09
+set_location_assignment PIN_AF17 -to adc_gp1 ; ## Arduino_IO08
+
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_scl
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_sda
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_spi_sclk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_spi_sdi
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_spi_sdo
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_spi_cs
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_cnv
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_gp0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_gp1
+
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+
+execute_flow -compile
diff --git a/projects/ad4052_ardz/de10nano/system_qsys.tcl b/projects/ad4052_ardz/de10nano/system_qsys.tcl
new file mode 100644
index 0000000000..d1e283d294
--- /dev/null
+++ b/projects/ad4052_ardz/de10nano/system_qsys.tcl
@@ -0,0 +1,15 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl
+source ../common/ad4052_qsys.tcl
+
+#system ID
+set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9}
+set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
+set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "$mem_init_sys_file_path/mem_init_sys.txt"
+
+sysid_gen_sys_init_file
diff --git a/projects/ad4052_ardz/de10nano/system_top.v b/projects/ad4052_ardz/de10nano/system_top.v
new file mode 100644
index 0000000000..153bc005fc
--- /dev/null
+++ b/projects/ad4052_ardz/de10nano/system_top.v
@@ -0,0 +1,278 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+// 1. The GNU General Public License version 2 as published by the
+// Free Software Foundation, which can be found in the top level directory
+// of this repository (LICENSE_GPL2), and also online at:
+//
+//
+// OR
+//
+// 2. An ADI specific BSD license, which can be found in the top level directory
+// of this repository (LICENSE_ADIBSD), and also on-line at:
+// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+// This will allow to generate bit files and not release the source code,
+// as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+ // clock and resets
+
+ input sys_clk,
+
+ // hps-ddr
+
+ output [14:0] ddr3_a,
+ output [ 2:0] ddr3_ba,
+ output ddr3_reset_n,
+ output ddr3_ck_p,
+ output ddr3_ck_n,
+ output ddr3_cke,
+ output ddr3_cs_n,
+ output ddr3_ras_n,
+ output ddr3_cas_n,
+ output ddr3_we_n,
+ inout [31:0] ddr3_dq,
+ inout [ 3:0] ddr3_dqs_p,
+ inout [ 3:0] ddr3_dqs_n,
+ output [ 3:0] ddr3_dm,
+ output ddr3_odt,
+ input ddr3_rzq,
+
+ // hps-ethernet
+
+ output eth1_tx_clk,
+ output eth1_tx_ctl,
+ output [ 3:0] eth1_tx_d,
+ input eth1_rx_clk,
+ input eth1_rx_ctl,
+ input [ 3:0] eth1_rx_d,
+ output eth1_mdc,
+ inout eth1_mdio,
+
+ // hps-sdio
+
+ output sdio_clk,
+ inout sdio_cmd,
+ inout [ 3:0] sdio_d,
+
+ // hps-spim1
+
+ output spim1_ss0,
+ output spim1_clk,
+ output spim1_mosi,
+ input spim1_miso,
+
+ // hps-usb
+
+ input usb1_clk,
+ output usb1_stp,
+ input usb1_dir,
+ input usb1_nxt,
+ inout [ 7:0] usb1_d,
+
+ // hps-uart
+
+ input uart0_rx,
+ output uart0_tx,
+ inout hps_conv_usb_n,
+
+ // board gpio
+
+ output [ 7:0] gpio_bd_o,
+ input [ 5:0] gpio_bd_i,
+
+ // hdmi
+
+ output hdmi_out_clk,
+ output hdmi_vsync,
+ output hdmi_hsync,
+ output hdmi_data_e,
+ output [ 23:0] hdmi_data,
+
+ inout hdmi_i2c_scl,
+ inout hdmi_i2c_sda,
+
+ inout i2c_sda,
+ inout i2c_scl,
+
+ // ad4052
+
+ output adc_spi_sclk,
+ input adc_spi_sdi,
+ output adc_spi_sdo,
+ output adc_spi_cs,
+ output adc_cnv,
+ input adc_gp0,
+ input adc_gp1 /* gpio */
+);
+
+ // internal signals
+
+ wire sys_resetn;
+ wire [63:0] gpio_i;
+ wire [63:0] gpio_o;
+
+ wire i2c1_scl;
+ wire i2c1_scl_oe;
+ wire i2c1_sda;
+ wire i2c1_sda_oe;
+
+ wire i2c0_out_data;
+ wire i2c0_sda;
+ wire i2c0_out_clk;
+ wire i2c0_scl_in_clk;
+
+ wire adc_cnv_w;
+ wire adc_gp1_n = ~adc_gp1;
+
+ // adc control gpio assign
+
+ assign gpio_i[63:35] = gpio_o[63:35];
+ assign gpio_i[31:14] = gpio_o[31:14];
+
+ assign gpio_i[13:8] = gpio_bd_i[5:0];
+ assign gpio_bd_o[7:0] = gpio_o[7:0];
+
+ // gpio inputs
+
+ assign gpio_i[33] = adc_gp1; // device ready then ~data ready
+ assign gpio_i[32] = adc_gp0; // threshold event
+ assign adc_cnv = adc_cnv_w | gpio_o[34];
+
+
+ // IO Buffers for I2C
+
+ ALT_IOBUF scl_iobuf (
+ .i(1'b0),
+ .oe(i2c1_scl_oe),
+ .o(i2c1_scl),
+ .io(i2c_scl));
+
+ ALT_IOBUF sda_iobuf (
+ .i(1'b0),
+ .oe(i2c1_sda_oe),
+ .o(i2c1_sda),
+ .io(i2c_sda));
+
+ ALT_IOBUF scl_video_iobuf (
+ .i(1'b0),
+ .oe(i2c0_out_clk),
+ .o(i2c0_scl_in_clk),
+ .io(hdmi_i2c_scl));
+
+ ALT_IOBUF sda_video_iobuf (
+ .i(1'b0),
+ .oe(i2c0_out_data),
+ .o(i2c0_sda),
+ .io(hdmi_i2c_sda));
+
+ system_bd i_system_bd (
+ .sys_clk_clk (sys_clk),
+ .sys_hps_h2f_reset_reset_n (sys_resetn),
+ .sys_hps_memory_mem_a (ddr3_a),
+ .sys_hps_memory_mem_ba (ddr3_ba),
+ .sys_hps_memory_mem_ck (ddr3_ck_p),
+ .sys_hps_memory_mem_ck_n (ddr3_ck_n),
+ .sys_hps_memory_mem_cke (ddr3_cke),
+ .sys_hps_memory_mem_cs_n (ddr3_cs_n),
+ .sys_hps_memory_mem_ras_n (ddr3_ras_n),
+ .sys_hps_memory_mem_cas_n (ddr3_cas_n),
+ .sys_hps_memory_mem_we_n (ddr3_we_n),
+ .sys_hps_memory_mem_reset_n (ddr3_reset_n),
+ .sys_hps_memory_mem_dq (ddr3_dq),
+ .sys_hps_memory_mem_dqs (ddr3_dqs_p),
+ .sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
+ .sys_hps_memory_mem_odt (ddr3_odt),
+ .sys_hps_memory_mem_dm (ddr3_dm),
+ .sys_hps_memory_oct_rzqin (ddr3_rzq),
+ .sys_rst_reset_n (sys_resetn),
+ .sys_hps_i2c0_out_data (i2c0_out_data),
+ .sys_hps_i2c0_sda (i2c0_sda),
+ .sys_hps_i2c0_clk_clk (i2c0_out_clk),
+ .sys_hps_i2c0_scl_in_clk (i2c0_scl_in_clk),
+ .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
+ .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
+ .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
+ .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
+ .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
+ .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
+ .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
+ .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
+ .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
+ .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
+ .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
+ .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
+ .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
+ .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
+ .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
+ .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
+ .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
+ .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
+ .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
+ .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
+ .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
+ .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
+ .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
+ .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
+ .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
+ .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
+ .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
+ .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
+ .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
+ .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
+ .sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n),
+ .sys_hps_i2c1_sda (i2c1_sda),
+ .sys_hps_i2c1_out_data (i2c1_sda_oe),
+ .sys_hps_i2c1_clk_clk (i2c1_scl_oe),
+ .sys_hps_i2c1_scl_in_clk (i2c1_scl),
+ .sys_gpio_bd_in_port (gpio_i[31:0]),
+ .sys_gpio_bd_out_port (gpio_o[31:0]),
+ .sys_gpio_in_export (gpio_i[63:32]),
+ .sys_gpio_out_export (gpio_o[63:32]),
+ .sys_spi_MISO (1'b0),
+ .sys_spi_MOSI (),
+ .sys_spi_SCLK (),
+ .sys_spi_SS_n (),
+ .axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk),
+ .axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync),
+ .axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync),
+ .axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e),
+ .axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data),
+ .adc_spi_sclk_clk (adc_spi_sclk),
+ .adc_spi_sdi_sdi (adc_spi_sdi),
+ .adc_spi_sdo_sdo (adc_spi_sdo),
+ .adc_spi_cs_cs (adc_spi_cs),
+ .adc_cnv_if_pwm (adc_cnv_w),
+ .adc_drdy_trigger_if_pwm (adc_gp1_n));
+
+endmodule