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i3c_controller: Add testbench project
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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‎i3c_controller/Makefile

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####################################################################################
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####################################################################################
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## Copyright (C) 2024 Analog Devices, Inc.
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####################################################################################
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####################################################################################
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# All test-bench dependencies except test programs
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SV_DEPS += ../common/sv/utils.svh
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SV_DEPS += ../common/sv/logger_pkg.sv
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SV_DEPS += ../common/sv/reg_accessor.sv
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SV_DEPS += ../common/sv/m_axis_sequencer.sv
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SV_DEPS += ../common/sv/s_axis_sequencer.sv
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SV_DEPS += ../common/sv/m_axi_sequencer.sv
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SV_DEPS += ../common/sv/s_axi_sequencer.sv
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SV_DEPS += ../common/sv/dmac_api.sv
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SV_DEPS += ../common/sv/adi_regmap_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_dmac_pkg.sv
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SV_DEPS += ../common/sv/dma_trans.sv
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SV_DEPS += ../common/sv/axi_dmac_pkg.sv
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SV_DEPS += system_tb.sv
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ENV_DEPS +=../../library/util_cdc/sync_bits.v
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ENV_DEPS +=../../library/common/ad_edge_detect.v
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ENV_DEPS += system_project.tcl
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ENV_DEPS += system_bd.tcl
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ENV_DEPS +=../scripts/adi_sim.tcl
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ENV_DEPS +=../scripts/run_sim.tcl
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += i3c_controller/i3c_controller_host_interface
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LIB_DEPS += i3c_controller/i3c_controller_core
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LIB_DEPS += sysid_rom
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# default test program
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TP := test_program
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# config files should have the following format
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# cfg_<param1>_<param2>.tcl
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CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
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#$(warning $(CFG_FILES))
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# List of tests and configuration combinations that has to be run
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# Format is: <configuration>:<test name>
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TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
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include ../scripts/project-sim.mk
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# usage :
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#
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# run specific test on a specific configuration in gui mode
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# make CFG=cfg1 TST=test_program MODE=gui
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#
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# run all test from a configuration
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# make cfg1
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####################################################################################
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####################################################################################

‎i3c_controller/README.md

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Usage :
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Run all tests in batch mode:
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make
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Run all tests in GUI mode:
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make MODE=gui
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Run specific test on a specific configuration in gui mode:
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make CFG=<name of cfg> TST=<name of test> MODE=gui
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Run all test from a configuration:
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make <name of cfg>
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Where:
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* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
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* <name of test> is a file from the tests directory without the tcl extension
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‎i3c_controller/cfgs/cfg1.tcl

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global ad_project_params

‎i3c_controller/system_bd.tcl

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# ***************************************************************************
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# ***************************************************************************
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# Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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source ../../scripts/adi_env.tcl
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global ad_project_params
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adi_project_files [list \
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"../../library/common/ad_edge_detect.v" \
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"../../library/util_cdc/sync_bits.v" \
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"../../library/common/ad_iobuf.v" \
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]
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#
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# Block design under test
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#
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create_bd_intf_port -mode Master -vlnv analog.com:interface:i3c_controller_rtl:1.0 i3c_controller_0
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source $ad_hdl_dir/library/i3c_controller/scripts/i3c_controller.tcl
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set async_clk 0
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set offload 1
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set max_devs 16
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set hier_i3c_controller i3c_controller_0
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i3c_controller_create $hier_i3c_controller $async_clk $offload $max_devs
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# pwm to trigger on offload data burst
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ad_ip_instance axi_pwm_gen i3c_offload_pwm
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ad_ip_parameter i3c_offload_pwm CONFIG.PULSE_0_PERIOD 120
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ad_ip_parameter i3c_offload_pwm CONFIG.PULSE_0_WIDTH 1
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# dma to receive offload data stream
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ad_ip_instance axi_dmac i3c_offload_dma
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter i3c_offload_dma CONFIG.CYCLIC 0
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ad_ip_parameter i3c_offload_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter i3c_offload_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter i3c_offload_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect $sys_cpu_clk i3c_offload_pwm/ext_clk
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ad_connect $sys_cpu_clk i3c_offload_pwm/s_axi_aclk
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ad_connect sys_cpu_resetn i3c_offload_pwm/s_axi_aresetn
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ad_connect i3c_offload_pwm/pwm_0 $hier_i3c_controller/trigger
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ad_connect i3c_offload_dma/s_axis $hier_i3c_controller/m_offload
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ad_connect $hier_i3c_controller/m_i3c i3c_controller_0
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ad_connect $sys_cpu_clk $hier_i3c_controller/clk
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ad_connect $sys_cpu_clk i3c_offload_dma/s_axis_aclk
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ad_connect sys_cpu_resetn $hier_i3c_controller/reset_n
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ad_connect sys_cpu_resetn i3c_offload_dma/m_dest_axi_aresetn
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ad_cpu_interconnect 0x44a00000 $hier_i3c_controller/host_interface
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ad_cpu_interconnect 0x44a30000 i3c_offload_dma
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ad_cpu_interconnect 0x44b00000 i3c_offload_pwm
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ad_cpu_interrupt "ps-13" "mb-13" i3c_offload_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /$hier_i3c_controller/irq
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk i3c_offload_dma/m_dest_axi
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create_bd_port -dir O i3c_irq
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create_bd_port -dir O i3c_clk
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ad_connect i3c_irq i3c_controller_0/irq
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ad_connect i3c_clk sys_clk_vip/clk_out

‎i3c_controller/system_project.tcl

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# ***************************************************************************
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# ***************************************************************************
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# Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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source ../scripts/adi_sim.tcl
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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if {$argc < 1} {
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puts "Expecting at least one argument that specifies the test configuration"
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exit 1
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} else {
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set cfg_file [lindex $argv 0]
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}
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# Read common config file
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source "cfgs/${cfg_file}"
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# Set the project name
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set project_name [file rootname $cfg_file]
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# Create the project
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adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e"
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# Add test files to the project
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adi_sim_project_files [list \
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"../common/sv/utils.svh" \
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"../common/sv/logger_pkg.sv" \
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"../common/sv/reg_accessor.sv" \
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"../common/sv/m_axis_sequencer.sv" \
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"../common/sv/s_axis_sequencer.sv" \
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"../common/sv/m_axi_sequencer.sv" \
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"../common/sv/s_axi_sequencer.sv" \
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"../common/sv/dmac_api.sv" \
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"../common/sv/adi_regmap_pkg.sv" \
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"../common/sv/adi_regmap_dmac_pkg.sv" \
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"../common/sv/dma_trans.sv" \
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"../common/sv/axi_dmac_pkg.sv" \
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"../common/sv/test_harness_env.sv" \
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"tests/test_program.sv" \
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"system_tb.sv" \
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]
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#set a default test program
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adi_sim_add_define "TEST_PROGRAM=test_program"
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adi_sim_generate $project_name

‎i3c_controller/system_tb.sv

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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
7+
// developed independently, and may be accompanied by separate and unique license
8+
// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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`include "utils.svh"
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module system_tb();
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wire i3c_irq;
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wire i3c_clk;
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wire i3c_scl;
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wire i3c_sda;
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wire i3c_sdi;
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wire i3c_sdo;
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wire i3c_t;
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_iobuf_sda (
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.dio_t(i3c_t),
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.dio_i(i3c_sdo),
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.dio_o(i3c_sdi),
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.dio_p(i3c_sda));
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`TEST_PROGRAM test(
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.i3c_irq(i3c_irq),
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.i3c_clk(i3c_clk),
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.i3c_controller_0_scl(i3c_scl),
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.i3c_controller_0_sda(i3c_sda));
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test_harness `TH (
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.i3c_irq(i3c_irq),
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.i3c_clk(i3c_clk),
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.i3c_controller_0_scl(i3c_scl),
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.i3c_controller_0_sdi(i3c_sdi),
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.i3c_controller_0_sdo(i3c_sdo),
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.i3c_controller_0_t(i3c_t));
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endmodule

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