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arm/cortex-a,r: replace cp15 instruct to macros align operation
1. move cp15.h to arch public 2. replace cp15 instruct to macros align operation 3. add memory barrier to avoid compiler optimization Signed-off-by: chao an <anchao@lixiang.com>
1 parent 0561b55 commit 90e5f4c

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10 files changed

+68
-65
lines changed

10 files changed

+68
-65
lines changed

‎arch/arm/src/armv7-a/barriers.h renamed to ‎arch/arm/include/armv7-a/barriers.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/****************************************************************************
2-
* arch/arm/src/armv7-a/barriers.h
2+
* arch/arm/include/armv7-a/barriers.h
33
*
44
* Licensed to the Apache Software Foundation (ASF) under one or more
55
* contributor license agreements. See the NOTICE file distributed with

‎arch/arm/src/armv7-a/cp15.h renamed to ‎arch/arm/include/armv7-a/cp15.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/****************************************************************************
2-
* arch/arm/src/armv7-a/cp15.h
2+
* arch/arm/include/armv7-a/cp15.h
33
*
44
* Licensed to the Apache Software Foundation (ASF) under one or more
55
* contributor license agreements. See the NOTICE file distributed with

‎arch/arm/include/armv7-a/irq.h

Lines changed: 9 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@
3636
# include <stdint.h>
3737
#endif
3838

39+
#include "cp15.h"
40+
#include "barriers.h"
41+
3942
/****************************************************************************
4043
* Pre-processor Prototypes
4144
****************************************************************************/
@@ -457,11 +460,8 @@ static inline_function int up_cpu_index(void)
457460

458461
/* Read the Multiprocessor Affinity Register (MPIDR) */
459462

460-
__asm__ __volatile__
461-
(
462-
"mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
463-
: "=r"(mpidr)
464-
);
463+
ARM_ISB();
464+
mpidr = CP15_GET(MPIDR);
465465

466466
/* And return the CPU ID field */
467467

@@ -500,23 +500,15 @@ static inline_function uint32_t up_getsp(void)
500500
noinstrument_function
501501
static inline_function uint32_t *up_current_regs(void)
502502
{
503-
uint32_t *regs;
504-
__asm__ __volatile__
505-
(
506-
"mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
507-
: "=r"(regs)
508-
);
509-
return regs;
503+
ARM_ISB();
504+
return (uint32_t *)CP15_GET(TPIDRPRW);
510505
}
511506

512507
noinstrument_function
513508
static inline_function void up_set_current_regs(uint32_t *regs)
514509
{
515-
__asm__ __volatile__
516-
(
517-
"mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
518-
:: "r"(regs)
519-
);
510+
CP15_SET(TPIDRPRW, regs);
511+
ARM_ISB();
520512
}
521513

522514
noinstrument_function

‎arch/arm/src/armv7-r/barriers.h renamed to ‎arch/arm/include/armv7-r/barriers.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/****************************************************************************
2-
* arch/arm/src/armv7-r/barriers.h
2+
* arch/arm/include/armv7-r/barriers.h
33
*
44
* Licensed to the Apache Software Foundation (ASF) under one or more
55
* contributor license agreements. See the NOTICE file distributed with

‎arch/arm/src/armv7-r/cp15.h renamed to ‎arch/arm/include/armv7-r/cp15.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/****************************************************************************
2-
* arch/arm/src/armv7-r/cp15.h
2+
* arch/arm/include/armv7-r/cp15.h
33
*
44
* Licensed to the Apache Software Foundation (ASF) under one or more
55
* contributor license agreements. See the NOTICE file distributed with

‎arch/arm/include/armv7-r/irq.h

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@
3636
# include <stdint.h>
3737
#endif
3838

39+
#include "cp15.h"
40+
#include "barriers.h"
41+
3942
/****************************************************************************
4043
* Pre-processor Prototypes
4144
****************************************************************************/
@@ -357,7 +360,7 @@ static inline irqstate_t irqstate(void)
357360

358361
/* Disable IRQs and return the previous IRQ state */
359362

360-
static inline irqstate_t up_irq_save(void)
363+
noinstrument_function static inline irqstate_t up_irq_save(void)
361364
{
362365
unsigned int cpsr;
363366

@@ -417,7 +420,7 @@ static inline irqstate_t up_irq_disable(void)
417420

418421
/* Restore saved IRQ & FIQ state */
419422

420-
static inline void up_irq_restore(irqstate_t flags)
423+
noinstrument_function static inline void up_irq_restore(irqstate_t flags)
421424
{
422425
__asm__ __volatile__
423426
(
@@ -452,11 +455,8 @@ static inline_function int up_cpu_index(void)
452455

453456
/* Read the Multiprocessor Affinity Register (MPIDR) */
454457

455-
__asm__ __volatile__
456-
(
457-
"mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
458-
: "=r"(mpidr)
459-
);
458+
ARM_ISB();
459+
mpidr = CP15_GET(MPIDR);
460460

461461
/* And return the CPU ID field */
462462

@@ -479,26 +479,31 @@ static inline_function uint32_t up_getsp(void)
479479
return sp;
480480
}
481481

482+
/****************************************************************************
483+
* Name:
484+
* up_current_regs/up_set_current_regs
485+
*
486+
* Description:
487+
* We use the following code to manipulate the TPIDRPRW register,
488+
* which exists uniquely for each CPU and is primarily designed to store
489+
* current thread information. Currently, we leverage it to store interrupt
490+
* information, with plans to further optimize its use for storing both
491+
* thread and interrupt information in the future.
492+
*
493+
****************************************************************************/
494+
482495
noinstrument_function
483496
static inline_function uint32_t *up_current_regs(void)
484497
{
485-
uint32_t *regs;
486-
__asm__ __volatile__
487-
(
488-
"mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
489-
: "=r"(regs)
490-
);
491-
return regs;
498+
ARM_ISB();
499+
return (uint32_t *)CP15_GET(TPIDRPRW);
492500
}
493501

494502
noinstrument_function
495503
static inline_function void up_set_current_regs(uint32_t *regs)
496504
{
497-
__asm__ __volatile__
498-
(
499-
"mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
500-
:: "r"(regs)
501-
);
505+
CP15_SET(TPIDRPRW, regs);
506+
ARM_ISB();
502507
}
503508

504509
noinstrument_function

‎arch/arm/src/armv8-r/barriers.h renamed to ‎arch/arm/include/armv8-r/barriers.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/****************************************************************************
2-
* arch/arm/src/armv8-r/barriers.h
2+
* arch/arm/include/armv8-r/barriers.h
33
*
44
* Licensed to the Apache Software Foundation (ASF) under one or more
55
* contributor license agreements. See the NOTICE file distributed with

‎arch/arm/src/armv8-r/cp15.h renamed to ‎arch/arm/include/armv8-r/cp15.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/****************************************************************************
2-
* arch/arm/src/armv8-r/cp15.h
2+
* arch/arm/include/armv8-r/cp15.h
33
*
44
* Licensed to the Apache Software Foundation (ASF) under one or more
55
* contributor license agreements. See the NOTICE file distributed with

‎arch/arm/include/armv8-r/irq.h

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@
3636
# include <stdint.h>
3737
#endif
3838

39+
#include "cp15.h"
40+
#include "barriers.h"
41+
3942
/****************************************************************************
4043
* Pre-processor Prototypes
4144
****************************************************************************/
@@ -357,7 +360,7 @@ static inline irqstate_t irqstate(void)
357360

358361
/* Disable IRQs and return the previous IRQ state */
359362

360-
static inline irqstate_t up_irq_save(void)
363+
noinstrument_function static inline irqstate_t up_irq_save(void)
361364
{
362365
unsigned int cpsr;
363366

@@ -417,7 +420,7 @@ static inline irqstate_t up_irq_disable(void)
417420

418421
/* Restore saved IRQ & FIQ state */
419422

420-
static inline void up_irq_restore(irqstate_t flags)
423+
noinstrument_function static inline void up_irq_restore(irqstate_t flags)
421424
{
422425
__asm__ __volatile__
423426
(
@@ -452,11 +455,8 @@ static inline_function int up_cpu_index(void)
452455

453456
/* Read the Multiprocessor Affinity Register (MPIDR) */
454457

455-
__asm__ __volatile__
456-
(
457-
"mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n"
458-
: "=r"(mpidr)
459-
);
458+
ARM_ISB();
459+
mpidr = CP15_GET(MPIDR);
460460

461461
/* And return the CPU ID field */
462462

@@ -479,26 +479,31 @@ static inline_function uint32_t up_getsp(void)
479479
return sp;
480480
}
481481

482+
/****************************************************************************
483+
* Name:
484+
* up_current_regs/up_set_current_regs
485+
*
486+
* Description:
487+
* We use the following code to manipulate the TPIDRPRW register,
488+
* which exists uniquely for each CPU and is primarily designed to store
489+
* current thread information. Currently, we leverage it to store interrupt
490+
* information, with plans to further optimize its use for storing both
491+
* thread and interrupt information in the future.
492+
*
493+
****************************************************************************/
494+
482495
noinstrument_function
483496
static inline_function uint32_t *up_current_regs(void)
484497
{
485-
uint32_t *regs;
486-
__asm__ __volatile__
487-
(
488-
"mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
489-
: "=r"(regs)
490-
);
491-
return regs;
498+
ARM_ISB();
499+
return (uint32_t *)CP15_GET(TPIDRPRW);
492500
}
493501

494502
noinstrument_function
495503
static inline_function void up_set_current_regs(uint32_t *regs)
496504
{
497-
__asm__ __volatile__
498-
(
499-
"mcr " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
500-
:: "r"(regs)
501-
);
505+
CP15_SET(TPIDRPRW, regs);
506+
ARM_ISB();
502507
}
503508

504509
noinstrument_function

‎arch/arm/src/Makefile

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,12 @@ else # ARM9, ARM7TDMI, etc.
3737
ARCH_SUBDIR = arm
3838
endif
3939

40-
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
40+
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)
4141

42-
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip
43-
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common
44-
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR)
42+
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)src$(DELIM)chip
43+
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)src$(DELIM)common
44+
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)src$(DELIM)$(ARCH_SUBDIR)
45+
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)include$(DELIM)$(ARCH_SUBDIR)
4546
INCLUDES += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)sched
4647

4748
CPPFLAGS += $(INCLUDES)

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