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sxb-hacker.lst
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Mon Jun 18 2018 20:56 Page 1
***************************************
** WDC 65C816 Macro Assembler **
** **
** Version 3.49.1- Feb 6 2006 **
***************************************
1 ;===============================================================================
2 ; ______ ______ _ _ _
3 ; / ___\ \/ / __ ) | | | | __ _ ___| | _____ _ __
4 ; \___ \\ /| _ \ _____| |_| |/ _` |/ __| |/ / _ \ '__|
5 ; ___) / \| |_) |_____| _ | (_| | (__| < __/ |
6 ; |____/_/\_\____/ |_| |_|\__,_|\___|_|\_\___|_|
7 ;
8 ; A program for Hacking your W65C265SXB or W65C816SXB
9 ;-------------------------------------------------------------------------------
10 ; Copyright (C),2015-2018 Andrew Jacobs
11 ; All rights reserved.
12 ;
13 ; This work is made available under the terms of the Creative Commons
14 ; Attribution-NonCommercial-ShareAlike 4.0 International license. Open the
15 ; following URL to see the details.
16 ;
17 ; http://creativecommons.org/licenses/by-nc-sa/4.0/
18 ;
19 ;===============================================================================
20 ; Notes:
21 ;
22 ; This program provides a simple monitor that you can use to inspect the memory
23 ; in your SXB and reprogram parts of the flash ROM.
24 ;
25 ;-------------------------------------------------------------------------------
26
27 pw 132
28 inclist on
29
30 chip 65816
31
32 ifdef W65C265SXB
33 include "w65c265.inc"
1 ;===============================================================================
2 ; __ ____ ____ ____ ____ __ ____
3 ; \ \ / / /_| ___| / ___|___ \ / /_| ___|
4 ; \ \ /\ / / '_ \___ \| | __) | '_ \___ \
5 ; \ V V /| (_) |__) | |___ / __/| (_) |__) |
6 ; \_/\_/ \___/____/ \____|_____|\___/____/
7 ;
8 ; Western Design Center W65C265 device definitions
9 ;-------------------------------------------------------------------------------
10 ; Copyright (C)2015 HandCoded Software Ltd.
11 ; All rights reserved.
12 ;
13 ; This work is made available under the terms of the Creative Commons
14 ; Attribution-NonCommercial-ShareAlike 4.0 International license. Open the
15 ; following URL to see the details.
16 ;
17 ; http://creativecommons.org/licenses/by-nc-sa/4.0/
18 ;
19 ;===============================================================================
Mon Jun 18 2018 20:56 Page 2
20 ; Notes:
21 ;
22 ; Various macros and definitions for the W65C265 microcontroller.
23 ;
24 ;===============================================================================
25 ; Revision History:
26 ;
27 ; 2015-12-18 AJ Initial version
28 ;-------------------------------------------------------------------------------
29 ; $Id$
30 ;-------------------------------------------------------------------------------
31
32 ;===============================================================================
33 ; Hardware Registers
34 ;-------------------------------------------------------------------------------
35
36 ;00DF00-1F CS0 Port Replacement & Expansion uninitialized
37
38 0000DF00 PD0 equ $00DF00 ; Port 0 Data Register
39 0000DF01 PD1 equ $00DF01 ; Port 1 Data Register
40 0000DF02 PD2 equ $00DF02 ; Port 2 Data Register
41 0000DF03 PD3 equ $00DF03 ; Port 3 Data Register
42 0000DF04 PDD0 equ $00DF04 ; Port 0 Data Direction Register
43 0000DF05 PDD1 equ $00DF05 ; Port 1 Data Direction Register
44 0000DF06 PDD2 equ $00DF06 ; Port 2 Data Direction Register
45 0000DF07 PDD3 equ $00DF07 ; Port 3 Data Direction Register
46
47 0000DF20 PD4 equ $00DF20 ; Port 4 Data Register
48 0000DF21 PD5 equ $00DF21 ; Port 5 Data Register
49 0000DF22 PD6 equ $00DF22 ; Port 6 Data Register
50 0000DF23 PD7 equ $00DF23 ; Port 7 Data Register
51 0000DF24 PDD4 equ $00DF24 ; Port 4 Data Direction Register
52 0000DF25 PDD5 equ $00DF25 ; Port 5 Data Direction Register
53 0000DF26 PDD6 equ $00DF26 ; Port 6 Data Direction Register
54 0000DF27 PCS7 equ $00DF27 ; Port 7 Chip Select
55
56 ;00DF28-3F --- Reserved uninitialized
57
58 0000DF40 BCR equ $00DF40 ; Bus Control Register
59 0000DF41 SSCR equ $00DF41 ; System Speed Control Register
60 0000DF42 TCR equ $00DF42 ; Timer Control Register
61 0000DF43 TER equ $00DF43 ; Timer Enable Register
62 0000DF44 TIFR equ $00DF44 ; Timer Interrupt Flag Register
63 0000DF45 EIFR equ $00DF45 ; Edge Interrupt Flag Register
64 0000DF46 TIER equ $00DF46 ; Timer Interrupt Enable Register
65 0000DF47 EIER equ $00DF47 ; Edge Interrupt Enable Register
66 0000DF48 UIFR equ $00DF48 ; UART Interrupt Flag Register
67 0000DF49 UIER equ $00DF49 ; UART Interrupt Enable Register
68
69 0000DF50 T0LL equ $00DF50 ; Timer 0 Latch Low
70 0000DF51 T0LH equ $00DF51 ; Timer 0 Latch High
71 0000DF52 T1LL equ $00DF52 ; Timer 1 Latch Low
72 0000DF53 T1LH equ $00DF53 ; Timer 1 Latch High
73 0000DF54 T2LL equ $00DF54 ; Timer 2 Latch Low
74 0000DF55 T2LH equ $00DF55 ; Timer 2 Latch High
75 0000DF56 T3LL equ $00DF56 ; Timer 3 Latch Low
76 0000DF57 T3LH equ $00DF57 ; Timer 3 Latch High
77 0000DF58 T4LL equ $00DF58 ; Timer 4 Latch Low
Mon Jun 18 2018 20:56 Page 3
78 0000DF59 T4LH equ $00DF59 ; Timer 4 Latch High
79 0000DF5A T5LL equ $00DF5A ; Timer 5 Latch Low
80 0000DF5B T5LH equ $00DF5B ; Timer 5 Latch High
81 0000DF5C T6LL equ $00DF5C ; Timer 6 Latch Low
82 0000DF5D T6LH equ $00DF5D ; Timer 6 Latch High
83 0000DF5E T7LL equ $00DF5E ; Timer 7 Latch Low
84 0000DF5F T7LH equ $00DF5F ; Timer 7 Latch High
85 0000DF60 T0CL equ $00DF60 ; Timer 0 Counter Low
86 0000DF61 T0CH equ $00DF61 ; Timer 0 Counter High
87 0000DF62 T1CL equ $00DF62 ; Timer 1 Counter Low
88 0000DF63 T1CH equ $00DF63 ; Timer 1 Counter High
89 0000DF64 T2CL equ $00DF64 ; Timer 2 Counter Low
90 0000DF65 T2CH equ $00DF65 ; Timer 2 Counter High
91 0000DF66 T3CL equ $00DF66 ; Timer 3 Counter Low
92 0000DF67 T3CH equ $00DF67 ; Timer 3 Counter High
93 0000DF68 T4CL equ $00DF68 ; Timer 4 Counter Low
94 0000DF69 T4CH equ $00DF69 ; Timer 4 Counter High
95 0000DF6A T5CL equ $00DF6A ; Timer 5 Counter Low
96 0000DF6B T5CH equ $00DF6B ; Timer 5 Counter High
97 0000DF6C T6CL equ $00DF6C ; Timer 6 Counter Low
98 0000DF6D T6CH equ $00DF6D ; Timer 6 Counter High
99 0000DF6E T7CL equ $00DF6E ; Timer 7 Counter Low
100 0000DF6F T7CH equ $00DF6F ; Timer 7 Counter High
101
102 ;00DFC0-FF CS1 COProcessor Expansion uninitialized
103
104 0000DF70 ACSR0 equ $00DF70 ; UART 0 Control/Status Register
105 0000DF71 ARTD0 equ $00DF71 ; UART 0 Data Register
106 0000DF72 ACSR1 equ $00DF72 ; UART 1 Control/Status Register
107 0000DF73 ARTD1 equ $00DF73 ; UART 1 Data Register
108 0000DF74 ACSR2 equ $00DF74 ; UART 2 Control/Status Register
109 0000DF75 ARTD2 equ $00DF75 ; UART 2 Data Register
110 0000DF76 ACSR3 equ $00DF76 ; UART 3 Control/Status Register
111 0000DF77 ARTD3 equ $00DF77 ; UART 3 Data Register
112 0000DF78 PIBFR equ $00DF78 ; Parallel Interface Flag Register
113 0000DF79 PIBER equ $00DF79 ; Parallel Interface Enable Register
114 0000DF7A PIR2 equ $00DF7A ; Parallel Interface Register 2
115 0000DF7B PIR3 equ $00DF7B ; Parallel Interface Register 3
116 0000DF7C PIR4 equ $00DF7C ; Parallel Interface Register 4
117 0000DF7D PIR5 equ $00DF7D ; Parallel Interface Register 5
118 0000DF7E PIR6 equ $00DF7E ; Parallel Interface Register 6
119 0000DF7F PIR7 equ $00DF7F ; Parallel Interface Register 7
120
121 ;00DF80-BF RAM RAM Registers uninitialized
122
123 include "w65c816.inc"
1 ;==============================================================================
2 ; __ ____ ____ ____ ___ _ __
3 ; \ \ / / /_| ___| / ___( _ )/ |/ /_
4 ; \ \ /\ / / '_ \___ \| | / _ \| | '_ \
5 ; \ V V /| (_) |__) | |__| (_) | | (_) |
6 ; \_/\_/ \___/____/ \____\___/|_|\___/
7 ;
8 ; Western Design Center W65C816 device definitions
9 ;------------------------------------------------------------------------------
10 ; Copyright (C)2015 HandCoded Software Ltd.
11 ; All rights reserved.
12 ;
Mon Jun 18 2018 20:56 Page 4
13 ; This work is made available under the terms of the Creative Commons
14 ; Attribution-NonCommercial-ShareAlike 4.0 International license. Open the
15 ; following URL to see the details.
16 ;
17 ; http://creativecommons.org/licenses/by-nc-sa/4.0/
18 ;
19 ;===============================================================================
20 ; Notes:
21 ;
22 ; Various macros and definitions for the W65C816 microprocessor.
23 ;
24 ;===============================================================================
25 ; Revision History:
26 ;
27 ; 2015-12-18 AJ Initial version
28 ;-------------------------------------------------------------------------------
29 ; $Id$
30 ;-------------------------------------------------------------------------------
31
32 ;==============================================================================
33 ; Status Register Bits
34 ;------------------------------------------------------------------------------
35
36 00000080 N_FLAG equ 1<<7
37 00000040 V_FLAG equ 1<<6
38 00000020 M_FLAG equ 1<<5
39 00000010 X_FLAG equ 1<<4
40 00000010 B_FLAG equ 1<<4
41 00000008 D_FLAG equ 1<<3
42 00000004 I_FLAG equ 1<<2
43 00000002 Z_FLAG equ 1<<1
44 00000001 C_FLAG equ 1<<0
45
46 ;==============================================================================
47 ; Macros
48 ;------------------------------------------------------------------------------
49
50 ; Puts the processor in emulation mode. A, X and Y become 8-bits and the stack
51 ; is fixed at $0100-$01ff.
52
53 emulate macro
54 sec
55 xce
56 endm
57
58 ; Puts the processor in native mode. The size of the memory and index register
59 ; operations is not controlled by the M & X bits in the status register.
60
61 native macro
62 clc
63 xce
64 endm
65
66 ; Resets the M bit making the accumulator and memory accesses 16-bits wide.
67
68 long_a macro
69 rep #M_FLAG
70 longa on
Mon Jun 18 2018 20:56 Page 5
71 endm
72
73 ; Resets the X bit making the index registers 16-bits wide
74
75 long_i macro
76 rep #X_FLAG
77 longi on
78 endm
79
80 ; Resets the M and X bits making the accumulator, memory accesses and index
81 ; registers 16-bits wide.
82
83 long_ai macro
84 rep #M_FLAG|X_FLAG
85 longa on
86 longi on
87 endm
88
89 ; Sets the M bit making the accumulator and memory accesses 8-bits wide.
90
91 short_a macro
92 sep #M_FLAG
93 longa off
94 endm
95
96 ; Sets the X bit making the index registers 8-bits wide.
97
98 short_i macro
99 sep #X_FLAG
100 longi off
101 endm
102
103 ; Sets the M & X bits making the accumulator, memory accesses and index
104 ; registers 8-bits wide.
105
106 short_ai macro
107 sep #M_FLAG|X_FLAG
108 longa off
109 longi off
110 endm
34 else
35 include "w65c816.inc"
36 endif
37
38 ;===============================================================================
39 ;-------------------------------------------------------------------------------
40
41 MNEM macro P,Q,R
42 dw ((((P-'@')<<5)|(Q-'@'))<<5)|(R-'@')
43 endm
44
45 ;===============================================================================
46 ; ASCII Character Codes
47 ;-------------------------------------------------------------------------------
48
49 00000001 SOH equ $01
50 00000004 EOT equ $04
51 00000006 ACK equ $06
Mon Jun 18 2018 20:56 Page 6
52 00000007 BEL equ $07
53 00000008 BS equ $08
54 0000000A LF equ $0a
55 0000000D CR equ $0d
56 00000015 NAK equ $15
57 00000018 CAN equ $18
58 0000001B ESC equ $1b
59 0000007F DEL equ $7f
60
61 ;===============================================================================
62 ;-------------------------------------------------------------------------------
63
64 00000000 OP_ADC equ 0<<1
65 00000002 OP_AND equ 1<<1
66 00000004 OP_ASL equ 2<<1
67 00000006 OP_BCC equ 3<<1
68 00000008 OP_BCS equ 4<<1
69 0000000A OP_BEQ equ 5<<1
70 0000000C OP_BIT equ 6<<1
71 0000000E OP_BMI equ 7<<1
72 00000010 OP_BNE equ 8<<1
73 00000012 OP_BPL equ 9<<1
74 00000014 OP_BRA equ 10<<1
75 00000016 OP_BRK equ 11<<1
76 00000018 OP_BRL equ 12<<1
77 0000001A OP_BVC equ 13<<1
78 0000001C OP_BVS equ 14<<1
79 0000001E OP_CLC equ 15<<1
80 00000020 OP_CLD equ 16<<1
81 00000022 OP_CLI equ 17<<1
82 00000024 OP_CLV equ 18<<1
83 00000026 OP_CMP equ 19<<1
84 00000028 OP_COP equ 20<<1
85 0000002A OP_CPX equ 21<<1
86 0000002C OP_CPY equ 22<<1
87 0000002E OP_DEC equ 23<<1
88 00000030 OP_DEX equ 24<<1
89 00000032 OP_DEY equ 25<<1
90 00000034 OP_EOR equ 26<<1
91 00000036 OP_INC equ 27<<1
92 00000038 OP_INX equ 28<<1
93 0000003A OP_INY equ 29<<1
94 0000003C OP_JML equ 30<<1
95 0000003E OP_JMP equ 31<<1
96 00000040 OP_JSL equ 32<<1
97 00000042 OP_JSR equ 33<<1
98 00000044 OP_LDA equ 34<<1
99 00000046 OP_LDX equ 35<<1
100 00000048 OP_LDY equ 36<<1
101 0000004A OP_LSR equ 37<<1
102 0000004C OP_MVN equ 38<<1
103 0000004E OP_MVP equ 39<<1
104 00000050 OP_NOP equ 40<<1
105 00000052 OP_ORA equ 41<<1
106 00000054 OP_PEA equ 42<<1
107 00000056 OP_PEI equ 43<<1
108 00000058 OP_PER equ 44<<1
109 0000005A OP_PHA equ 45<<1
Mon Jun 18 2018 20:56 Page 7
110 0000005C OP_PHB equ 46<<1
111 0000005E OP_PHD equ 47<<1
112 00000060 OP_PHK equ 48<<1
113 00000062 OP_PHP equ 49<<1
114 00000064 OP_PHX equ 50<<1
115 00000066 OP_PHY equ 51<<1
116 00000068 OP_PLA equ 52<<1
117 0000006A OP_PLB equ 53<<1
118 0000006C OP_PLD equ 54<<1
119 0000006E OP_PLP equ 55<<1
120 00000070 OP_PLX equ 56<<1
121 00000072 OP_PLY equ 57<<1
122 00000074 OP_REP equ 58<<1
123 00000076 OP_ROL equ 59<<1
124 00000078 OP_ROR equ 60<<1
125 0000007A OP_RTI equ 61<<1
126 0000007C OP_RTL equ 62<<1
127 0000007E OP_RTS equ 63<<1
128 00000080 OP_SBC equ 64<<1
129 00000082 OP_SEC equ 65<<1
130 00000084 OP_SED equ 66<<1
131 00000086 OP_SEI equ 67<<1
132 00000088 OP_SEP equ 68<<1
133 0000008A OP_STA equ 69<<1
134 0000008C OP_STP equ 70<<1
135 0000008E OP_STX equ 71<<1
136 00000090 OP_STY equ 72<<1
137 00000092 OP_STZ equ 73<<1
138 00000094 OP_TAX equ 74<<1
139 00000096 OP_TAY equ 75<<1
140 00000098 OP_TCD equ 76<<1
141 0000009A OP_TCS equ 77<<1
142 0000009C OP_TDC equ 78<<1
143 0000009E OP_TRB equ 79<<1
144 000000A0 OP_TSB equ 80<<1
145 000000A2 OP_TSC equ 81<<1
146 000000A4 OP_TSX equ 82<<1
147 000000A6 OP_TXA equ 83<<1
148 000000A8 OP_TXS equ 84<<1
149 000000AA OP_TXY equ 85<<1
150 000000AC OP_TYA equ 86<<1
151 000000AE OP_TYX equ 87<<1
152 000000B0 OP_WAI equ 88<<1
153 000000B2 OP_WDM equ 89<<1
154 000000B4 OP_XBA equ 90<<1
155 000000B6 OP_XCE equ 91<<1
156
157 00000000 MD_ABS equ 0<<1 ; a
158 00000002 MD_ACC equ 1<<1 ; A
159 00000004 MD_ABX equ 2<<1 ; a,x
160 00000006 MD_ABY equ 3<<1 ; a,y
161 00000008 MD_ALG equ 4<<1 ; al
162 0000000A MD_ALX equ 5<<1 ; al,x
163 0000000C MD_AIN equ 6<<1 ; (a)
164 0000000E MD_AIX equ 7<<1 ; (a,x)
165 00000010 MD_DPG equ 8<<1 ; d
166 00000012 MD_STK equ 9<<1 ; d,s
167 00000014 MD_DPX equ 10<<1 ; d,x
Mon Jun 18 2018 20:56 Page 8
168 00000016 MD_DPY equ 11<<1 ; d,x
169 00000018 MD_DIN equ 12<<1 ; (d)
170 0000001A MD_DLI equ 13<<1 ; [d]
171 0000001C MD_SKY equ 14<<1 ; (d,s),y
172 0000001E MD_DIX equ 15<<1 ; (d,x)
173 00000020 MD_DIY equ 16<<1 ; (d),y
174 00000022 MD_DLY equ 17<<1 ; [d],y
175 00000024 MD_IMP equ 18<<1 ;
176 00000026 MD_REL equ 19<<1 ; r
177 00000028 MD_RLG equ 20<<1 ; rl
178 0000002A MD_MOV equ 21<<1 ; xyc
179 0000002C MD_IMM equ 22<<1 ; # (A or M)
180 0000002E MD_INT equ 23<<1 ; # (BRK/COP/WDM)
181 00000030 MD_IMX equ 24<<1 ; # (X or Y)
182
183 ;===============================================================================
184 ; Data Areas
185 ;-------------------------------------------------------------------------------
186
187 page0
188 org $20
189
190 00:0020: FLAGS ds 1 ; Emulated processor flags
191 00:0021: BUFLEN ds 1 ; Command buffer length
192 00:0022: BANK ds 1 ; Memory bank
193
194 00:0023: ADDR_S ds 3 ; Start address
195 00:0026: ADDR_E ds 3 ; End address
196
197 00:0029: BLOCK ds 1 ; XMODEM block number
198 00:002A: RETRIES ds 1 ; Retry count
199 00:002B: SUM ds 1 ; Checksum
200
201 00:002C: TEMP ds 4 ; Scratch workspace
202
203 data
204 org $200
205
206 00:0200: BUFFER ds 128 ; Command buffer
207
208 ;===============================================================================
209 ; Initialisation
210 ;-------------------------------------------------------------------------------
211
212 code
213 public Start
214 extern UartRx
215 extern UartTx
216 extern UartRxTest
217 extern RomSelect
218 extern RomCheck
219 Start:
220 short_a ; Configure register sizes
+ 220 00:0000: E2 20 sep #M_FLAG
+ 220 longa off
221 long_i
+ 221 00:0002: C2 10 rep #X_FLAG
+ 221 longi on
Mon Jun 18 2018 20:56 Page 9
222 00:0004: 20 xx xx jsr TxCRLF
223 00:0007: A2 xx xx ldx #TITLE ; Display application title
224 00:000A: 20 xx xx jsr TxStr
225
226 00:000D: 64 22 stz BANK ; Reset default bank
227
228 ;===============================================================================
229 ; Command Processor
230 ;-------------------------------------------------------------------------------
231
232 NewCommand:
233 00:000F: 64 21 stz BUFLEN ; Clear the buffer
234 ShowCommand:
235 short_i
+ 235 00:0011: E2 10 sep #X_FLAG
+ 235 longi off
236 00:0013: 20 xx xx jsr TxCRLF ; Move to a new line
237
238 00:0016: A9 2E lda #'.' ; Output the prompt
239 00:0018: 20 xx xx jsr UartTx
240
241 00:001B: A2 00 ldx #0
242 00:001D: E4 21 DisplayCmd: cpx BUFLEN ; Any saved characters
243 00:001F: F0 0E beq ReadCommand
244 00:0021: BD 00 02 lda BUFFER,x ; Yes, display them
245 00:0024: 20 xx xx jsr UartTx
246 00:0027: E8 inx
247 00:0028: 80 F3 bra DisplayCmd
248
249 RingBell:
250 00:002A: A9 07 lda #BEL ; Make a beep
251 00:002C: 20 xx xx jsr UartTx
252
253 ReadCommand:
254 00:002F: 20 xx xx jsr UartRx ; Wait for character
255
256 00:0032: C9 1B cmp #ESC ; Cancel input?
257 00:0034: F0 D9 beq NewCommand ; Yes, clear and restart
258 00:0036: C9 0D cmp #CR ; End of command?
259 00:0038: F0 2D beq ProcessCommand ; Yes, start processing
260
261 00:003A: C9 08 cmp #BS ; Back space?
262 00:003C: F0 15 beq BackSpace
263 00:003E: C9 7F cmp #DEL ; Delete?
264 00:0040: F0 11 beq BackSpace
265
266 00:0042: C9 20 cmp #' ' ; Printable character
267 00:0044: 90 E4 bcc RingBell ; No.
268 00:0046: C9 7F cmp #DEL
269 00:0048: B0 E0 bcs RingBell ; No.
270 00:004A: 9D 00 02 sta BUFFER,x ; Save the character
271 00:004D: E8 inx
272 00:004E: 20 xx xx jsr UartTx ; Echo it and repeat
273 00:0051: 80 DC bra ReadCommand
274
275 BackSpace:
276 00:0053: E0 00 cpx #0 ; Buffer empty?
277 00:0055: F0 D3 beq RingBell ; Yes, beep and continue
Mon Jun 18 2018 20:56 Page 10
278 00:0057: CA dex ; No, remove last character
279 00:0058: A9 08 lda #BS
280 00:005A: 20 xx xx jsr UartTx
281 00:005D: 20 xx xx jsr TxSpace
282 00:0060: A9 08 lda #BS
283 00:0062: 20 xx xx jsr UartTx
284 00:0065: 80 C8 bra ReadCommand ; And retry
285
286 ProcessCommand:
287 00:0067: 86 21 stx BUFLEN ; Save final length
288 00:0069: A0 00 ldy #0 ; Load index for start
289
290 00:006B: 20 xx xx jsr SkipSpaces ; Fetch command character
291 00:006E: B0 9F bcs NewCommand ; None, empty command
292
293 ;===============================================================================
294 ; B - Select Memory Bank
295 ;-------------------------------------------------------------------------------
296
297 00:0070: C9 42 cmp #'B' ; Select memory bank?
298 00:0072: D0 0D bne NotMemoryBank
299
300 00:0074: A2 22 ldx #BANK ; Parse bank
301 00:0076: 20 xx xx jsr GetByte
302 00:0079: 90 03 bcc $+5
303 00:007B: 4C xx xx jmp ShowError
304 00:007E: 4C xx xx jmp NewCommand
305 NotMemoryBank:
306
307 ;===============================================================================
308 ; D - Disassemble Memory
309 ;-------------------------------------------------------------------------------
310
311 00:0081: C9 44 cmp #'D' ; Memory display?
312 00:0083: D0 78 bne NotDisassemble
313
314 00:0085: A2 23 ldx #ADDR_S ; Parse start address
315 00:0087: 20 xx xx jsr GetAddr
316 00:008A: 90 03 bcc $+5
317 00:008C: 4C xx xx jmp ShowError
318 00:008F: A2 26 ldx #ADDR_E ; Parse end address
319 00:0091: 20 xx xx jsr GetAddr
320 00:0094: 90 03 bcc $+5
321 00:0096: 4C xx xx jmp ShowError
322
323 00:0099: 08 php
324 00:009A: 68 pla
325 00:009B: 85 20 sta FLAGS
326
327 Disassemble:
328 00:009D: 20 xx xx jsr TxCRLF
329 00:00A0: A5 25 lda ADDR_S+2 ; Show memory address
330 00:00A2: 20 xx xx jsr TxHex2
331 00:00A5: A9 3A lda #':'
332 00:00A7: 20 xx xx jsr UartTx
333 00:00AA: A5 24 lda ADDR_S+1
334 00:00AC: 20 xx xx jsr TxHex2
335 00:00AF: A5 23 lda ADDR_S+0
Mon Jun 18 2018 20:56 Page 11
336 00:00B1: 20 xx xx jsr TxHex2
337 00:00B4: 20 xx xx jsr TxSpace
338
339 00:00B7: 20 xx xx jsr TxCodeBytes ; Show code bytes
340 00:00BA: 20 xx xx jsr TxSymbolic ; And instruction
341
342 00:00BD: A7 23 lda [ADDR_S] ; Fetch opcode again
343 00:00BF: 48 pha
344 00:00C0: A0 01 ldy #1
345
346 00:00C2: C9 18 cmp #$18 ; CLC?
347 00:00C4: D0 04 bne NotCLC
348 00:00C6: A9 01 lda #C_FLAG
349 00:00C8: 80 0E bra DoREP
350 NotCLC:
351 00:00CA: C9 38 cmp #$38 ; SEC?
352 00:00CC: D0 04 bne NotSEC
353 00:00CE: A9 01 lda #C_FLAG
354 00:00D0: 80 10 bra DoSEP
355 NotSEC:
356 00:00D2: C9 C2 cmp #$c2 ; REP?
357 00:00D4: D0 06 bne NotREP
358 00:00D6: B7 23 lda [ADDR_S],Y
359 00:00D8: 14 20 DoREP: trb FLAGS
360 00:00DA: 80 08 bra NextOpcode
361 NotREP:
362 00:00DC: C9 E2 cmp #$e2 ; SEP?
363 00:00DE: D0 04 bne NextOpcode
364 00:00E0: B7 23 lda [ADDR_S],Y
365 00:00E2: 04 20 DoSEP: tsb FLAGS
366
367 NextOpcode:
368 00:00E4: 68 pla
369 00:00E5: 20 xx xx jsr OpcodeSize
370
371 00:00E8: 18 clc
372 00:00E9: 65 23 adc ADDR_S+0 ; And move start address on
373 00:00EB: 85 23 sta ADDR_S+0
374 00:00ED: 90 02 bcc $+4
375 00:00EF: E6 24 inc ADDR_S+1
376
377 00:00F1: 38 sec ; Exceeded the end address?
378 00:00F2: E5 26 sbc ADDR_E+0
379 00:00F4: A5 24 lda ADDR_S+1
380 00:00F6: E5 27 sbc ADDR_E+1
381 00:00F8: 30 A3 bmi Disassemble ; No, show more
382
383 00:00FA: 4C xx xx jmp NewCommand ; Done
384 NotDisassemble:
385
386 ;===============================================================================
387 ; E - Erase ROM bank
388 ;-------------------------------------------------------------------------------
389
390 00:00FD: C9 45 cmp #'E' ; Erase bank?
391 00:00FF: D0 52 bne NotEraseBank
392
393 00:0101: 20 xx xx jsr CheckSafe
Mon Jun 18 2018 20:56 Page 12
394
395 ifdef W65C265SXB
396 00:0104: AD 40 DF lda BCR ; Save mask rom state
397 00:0107: 48 pha
398 00:0108: A9 80 lda #$80 ; Then ensure disabled
399 00:010A: 0C 40 DF tsb BCR
400 endif
401
402 00:010D: A9 00 lda #$00 ; Set start address
403 00:010F: 85 23 sta ADDR_S+0
404 00:0111: A9 80 lda #$80
405 00:0113: 85 24 sta ADDR_S+1
406 EraseLoop:
407 00:0115: A9 AA lda #$aa ; Unlock flash
408 00:0117: 8D 55 D5 sta $8000+$5555
409 00:011A: A9 55 lda #$55
410 00:011C: 8D AA AA sta $8000+$2aaa
411 00:011F: A9 80 lda #$80 ; Signal erase
412 00:0121: 8D 55 D5 sta $8000+$5555
413 00:0124: A9 AA lda #$aa
414 00:0126: 8D 55 D5 sta $8000+$5555
415 00:0129: A9 55 lda #$55
416 00:012B: 8D AA AA sta $8000+$2aaa
417 00:012E: A9 30 lda #$30 ; Sector erase
418 00:0130: 92 23 sta (ADDR_S)
419
420 EraseWait:
421 00:0132: B2 23 lda (ADDR_S) ; Wait for erase to finish
422 00:0134: C9 FF cmp #$FF
423 00:0136: D0 FA bne EraseWait
424
425 00:0138: 18 clc ; Move to next sector
426 00:0139: A5 24 lda ADDR_S+1
427 00:013B: 69 10 adc #$10
428 00:013D: 85 24 sta ADDR_S+1
429 00:013F: 90 D4 bcc EraseLoop ; Repeat until end of memory
430
431 ifdef W65C265SXB
432 00:0141: 68 pla ; Restore mask ROM state
433 00:0142: 8D 40 DF sta BCR
434 endif
435
436 00:0145: 4C xx xx jmp NewCommand ; And start over
437
438 EraseFailed:
439 long_i ; Warn that erase failed
+ 439 00:0148: C2 10 rep #X_FLAG
+ 439 longi on
440 00:014A: A2 xx xx ldx #ERASE_FAILED
441 00:014D: 20 xx xx jsr TxStr
442 longi off
443 00:0150: 4C xx xx jmp NewCommand ; And start over
444 NotEraseBank:
445
446 ;===============================================================================
447 ; F - WDC Mask ROM Enable/Disable
448 ;-------------------------------------------------------------------------------
449
Mon Jun 18 2018 20:56 Page 13
450 ifdef W65C265SXB
451 00:0153: C9 46 cmp #'F'
452 00:0155: D0 20 bne NotMaskROM
453
454 00:0157: 20 xx xx jsr SkipSpaces ; Find first argument
455 00:015A: B0 08 bcs MaskFail ; Success?
456
457 00:015C: C9 30 cmp #'0' ; Check bank is 0..3
458 00:015E: F0 0F beq MaskOff
459 00:0160: C9 31 cmp #'1'
460 00:0162: F0 03 beq MaskOn
461 MaskFail:
462 00:0164: 4C xx xx jmp ShowError
463
464 MaskOn:
465 00:0167: A9 80 lda #$80 ; Enable mask ROM
466 00:0169: 1C 40 DF trb BCR
467 00:016C: 4C xx xx jmp NewCommand
468
469 MaskOff:
470 00:016F: A9 80 lda #$80 ; Disable mask ROM
471 00:0171: 0C 40 DF tsb BCR
472 00:0174: 4C xx xx jmp NewCommand
473
474 NotMaskROM:
475 endif
476
477 ;===============================================================================
478 ; G - Goto
479 ;-------------------------------------------------------------------------------
480
481 00:0177: C9 47 cmp #'G' ; Invoke code
482 00:0179: D0 0D bne NotGoto
483
484 00:017B: A2 23 ldx #ADDR_S ; Parse execution address
485 00:017D: 20 xx xx jsr GetAddr
486 00:0180: B0 03 bcs $+5
487 00:0182: DC 23 00 jmp [ADDR_S] ; Run from address
488 00:0185: 6C FC FF jmp ($FFFC) ; Otherwise reset
489 NotGoto:
490
491 ;===============================================================================
492 ; H - Hunt for RAM
493 ;-------------------------------------------------------------------------------
494
495 00:0188: C9 48 cmp #'H' ; Hunt for RAM
496 00:018A: F0 03 beq $+5
497 00:018C: 4C xx xx jmp NotHunt
498
499 00:018F: 64 23 stz ADDR_S+0 ; Start at $00:0000
500 00:0191: 64 24 stz ADDR_S+1
501 00:0193: 64 25 stz ADDR_S+2
502
503 HuntStart:
504 00:0195: A7 23 lda [ADDR_S] ; Is byte is writeable?
505 00:0197: 48 pha
506 00:0198: 49 FF eor #$ff
507 00:019A: 87 23 sta [ADDR_S]
Mon Jun 18 2018 20:56 Page 14
508 00:019C: C7 23 cmp [ADDR_S]
509 00:019E: F0 11 beq HuntFound ; Yes
510
511 00:01A0: 68 pla
512 00:01A1: 18 clc ; Try the next block
513 00:01A2: A5 24 lda ADDR_S+1
514 00:01A4: 69 10 adc #$10
515 00:01A6: 85 24 sta ADDR_S+1
516 00:01A8: 90 EB bcc HuntStart
517 00:01AA: E6 25 inc ADDR_S+2
518 00:01AC: D0 E7 bne HuntStart
519 00:01AE: 4C xx xx jmp NewCommand ; Reached end of RAM
520
521 HuntFound:
522 00:01B1: 20 xx xx jsr TxCRLF
523 00:01B4: A5 25 lda ADDR_S+2 ; Print start address
524 00:01B6: 20 xx xx jsr TxHex2
525 00:01B9: A9 3A lda #':'
526 00:01BB: 20 xx xx jsr UartTx
527 00:01BE: A5 24 lda ADDR_S+1
528 00:01C0: 20 xx xx jsr TxHex2
529 00:01C3: A5 23 lda ADDR_S+0
530 00:01C5: 20 xx xx jsr TxHex2
531
532 00:01C8: A9 2D lda #'-'
533 00:01CA: 20 xx xx jsr UartTx
534
535 HuntEnd:
536 00:01CD: 68 pla ; Restore memory bytes
537 00:01CE: 87 23 sta [ADDR_S]
538 00:01D0: 18 clc ; Try the next block
539 00:01D1: A5 24 lda ADDR_S+1
540 00:01D3: 69 10 adc #$10
541 00:01D5: 85 24 sta ADDR_S+1
542 00:01D7: 90 04 bcc HuntNext
543 00:01D9: E6 25 inc ADDR_S+2
544 00:01DB: F0 2D beq HuntDone
545
546 HuntNext
547 00:01DD: A7 23 lda [ADDR_S] ; Is byte is writeable?
548 00:01DF: 48 pha
549 00:01E0: 49 FF eor #$ff
550 00:01E2: 87 23 sta [ADDR_S]
551 00:01E4: C7 23 cmp [ADDR_S]
552 00:01E6: F0 E5 beq HuntEnd ; Yes, keep looking
553
554 00:01E8: 68 pla
555 00:01E9: 38 sec ; Print end address
556 00:01EA: A5 23 lda ADDR_S+0
557 00:01EC: E9 01 sbc #1
558 00:01EE: 48 pha
559 00:01EF: A5 24 lda ADDR_S+1
560 00:01F1: E9 00 sbc #0
561 00:01F3: 48 pha
562 00:01F4: A5 25 lda ADDR_S+2
563 00:01F6: E9 00 sbc #0
564 00:01F8: 20 xx xx jsr TxHex2
565 00:01FB: A9 3A lda #':'
Mon Jun 18 2018 20:56 Page 15
566 00:01FD: 20 xx xx jsr UartTx
567 00:0200: 68 pla
568 00:0201: 20 xx xx jsr TxHex2
569 00:0204: 68 pla
570 00:0205: 20 xx xx jsr TxHex2
571 00:0208: 80 8B bra HuntStart
572
573 HuntDone:
574 00:020A: A9 FF lda #$ff ; Pring FF:FFFF
575 00:020C: 48 pha
576 00:020D: 48 pha
577 00:020E: 20 xx xx jsr TxHex2
578 00:0211: A9 3A lda #':'
579 00:0213: 20 xx xx jsr UartTx
580 00:0216: 68 pla
581 00:0217: 20 xx xx jsr TxHex2
582 00:021A: 68 pla
583 00:021B: 20 xx xx jsr TxHex2
584 00:021E: 4C xx xx jmp NewCommand
585 NotHunt:
586
587 ;===============================================================================
588 ; M - Display Memory
589 ;-------------------------------------------------------------------------------
590
591 00:0221: C9 4D cmp #'M' ; Memory display?
592 00:0223: D0 70 bne NotMemoryDisplay
593
594 00:0225: A2 23 ldx #ADDR_S ; Parse start address
595 00:0227: 20 xx xx jsr GetAddr
596 00:022A: 90 03 bcc $+5
597 00:022C: 4C xx xx jmp ShowError
598 00:022F: A2 26 ldx #ADDR_E ; Parse end address
599 00:0231: 20 xx xx jsr GetAddr
600 00:0234: 90 03 bcc $+5
601 00:0236: 4C xx xx jmp ShowError
602
603 DisplayMemory:
604 00:0239: 20 xx xx jsr TxCRLF
605 00:023C: A5 25 lda ADDR_S+2 ; Show memory address
606 00:023E: 20 xx xx jsr TxHex2
607 00:0241: A9 3A lda #':'
608 00:0243: 20 xx xx jsr UartTx
609 00:0246: A5 24 lda ADDR_S+1
610 00:0248: 20 xx xx jsr TxHex2
611 00:024B: A5 23 lda ADDR_S+0
612 00:024D: 20 xx xx jsr TxHex2
613
614 00:0250: A0 00 ldy #0 ; Show sixteen bytes of data
615 00:0252: 20 xx xx ByteLoop: jsr TxSpace
616 00:0255: B7 23 lda [ADDR_S],y
617 00:0257: 20 xx xx jsr TxHex2
618 00:025A: C8 iny
619 00:025B: C0 10 cpy #16
620 00:025D: D0 F3 bne ByteLoop
621
622 00:025F: 20 xx xx jsr TxSpace
623 00:0262: A9 7C lda #'|'
Mon Jun 18 2018 20:56 Page 16
624 00:0264: 20 xx xx jsr UartTx
625 00:0267: A0 00 ldy #0 ; Show sixteen characters
626 00:0269: B7 23 CharLoop: lda [ADDR_S],Y
627 00:026B: 20 xx xx jsr IsPrintable
628 00:026E: B0 02 bcs $+4
629 00:0270: A9 2E lda #'.'
630 00:0272: 20 xx xx jsr UartTx
631 00:0275: C8 iny
632 00:0276: C0 10 cpy #16
633 00:0278: D0 EF bne CharLoop
634 00:027A: A9 7C lda #'|'
635 00:027C: 20 xx xx jsr UartTx
636
637 00:027F: 18 clc ; Bump the display address
638 00:0280: 98 tya
639 00:0281: 65 23 adc ADDR_S+0
640 00:0283: 85 23 sta ADDR_S+0
641 00:0285: 90 02 bcc $+4
642 00:0287: E6 24 inc ADDR_S+1
643
644 00:0289: 38 sec ; Exceeded the end address?
645 00:028A: E5 26 sbc ADDR_E+0
646 00:028C: A5 24 lda ADDR_S+1
647 00:028E: E5 27 sbc ADDR_E+1
648 00:0290: 30 A7 bmi DisplayMemory ; No, show more
649
650 00:0292: 4C xx xx jmp NewCommand
651 NotMemoryDisplay:
652
653 ;===============================================================================
654 ; R - Select ROM Bank
655 ;-------------------------------------------------------------------------------
656
657 00:0295: C9 52 cmp #'R' ; ROM Bank?
658 00:0297: D0 16 bne NotROMBank ; No
659
660 00:0299: 20 xx xx jsr SkipSpaces ; Find first argument
661 00:029C: 90 03 bcc $+5 ; Success?
662 00:029E: 4C xx xx BankFail: jmp ShowError ; No
663
664 00:02A1: C9 30 cmp #'0' ; Check bank is 0..3
665 00:02A3: 90 F9 bcc BankFail
666 00:02A5: C9 34 cmp #'3'+1
667 00:02A7: B0 F5 bcs BankFail
668
669 00:02A9: 20 xx xx jsr RomSelect ; Switch ROM banks
670 00:02AC: 4C xx xx jmp NewCommand ; Done
671 NotROMBank:
672
673 ;===============================================================================
674 ; S - S19 Record
675 ;-------------------------------------------------------------------------------
676
677 00:02AF: C9 53 cmp #'S' ; S19?
678 00:02B1: F0 03 beq $+5
679 00:02B3: 4C xx xx jmp NotS19
680
681 00:02B6: 20 xx xx jsr NextChar ; Get record type
Mon Jun 18 2018 20:56 Page 17
682 00:02B9: B0 79 bcs S19Fail
683 00:02BB: C9 31 cmp #'1' ; Only process type 1
684 00:02BD: D0 72 bne S19Done
685
686 00:02BF: A2 26 ldx #ADDR_E ; Get byte count
687 00:02C1: 20 xx xx jsr GetByte
688 00:02C4: B0 6E bcs S19Fail
689 00:02C6: A5 26 lda ADDR_E ; Use as initial checksum
690 00:02C8: 85 2B sta SUM
691 00:02CA: C6 26 dec ADDR_E
692 00:02CC: F0 66 beq S19Fail
693
694 00:02CE: A2 23 ldx #ADDR_S ; Get address
695 00:02D0: 20 xx xx jsr GetAddr
696 00:02D3: B0 5F bcs S19Fail
697 00:02D5: A5 23 lda ADDR_S+0 ; Add to checksum
698 00:02D7: 65 24 adc ADDR_S+1
699 00:02D9: 18 clc
700 00:02DA: 65 2B adc SUM
701 00:02DC: 85 2B sta SUM
702 00:02DE: C6 26 dec ADDR_E