From a5920f3b2d4426068cfc2ef87fb6740df9fa65ba Mon Sep 17 00:00:00 2001 From: GHA Date: Fri, 27 Sep 2024 11:52:55 +0000 Subject: [PATCH] update 68a1e7be89fc5fb5eb0524aaf93a1aba20237443 --- .buildinfo | 4 + .nojekyll | 0 .../data_hierarchy.json | 1 + .../spec_pwm.json | 1 + .../dataflow.json | 221 +++ .../data_soc.json | 1 + .../specification_hierarchy.json | 420 ++++ .../data_inout.json | 1 + .../dataflow_hierarchy.json | 957 ++++++++++ .../spec_inout.json | 1 + .../data_pwm.json | 1 + .../spec_hierarchy.json | 1 + .../data_hdmi.json | 1 + .../data_user_repository.json | 1 + .../spec_constant.json | 1 + .../specification.json | 224 +++ .../spec_user_repository.json | 1 + .../spec_hdmi.json | 1 + .../data_constant.json | 1 + .../spec_soc.json | 1 + _images/external_port.png | Bin 0 -> 22654 bytes _images/getting_started_project.png | Bin 0 -> 58644 bytes _images/invalid_connection.png | Bin 0 -> 53521 bytes _images/ipconnect.png | Bin 0 -> 71018 bytes _images/kpm_button_fullscreen.png | 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z+uGB-ZSyg(CE6a!=(|34nQUPH3Dw|n?20NhC>|gR+ zY4-U>$v*)Zo{&9>pR7@`%x4DGGOZ$jl*(9l4KD+uG+!T0lmc*pl2=ByKI1Cjqh^9Ao>|K)CZ%d@rnus<1&&#rBZ9H`Ehd~?)FwkaPt>1 z0>?~1@;ci-+zaEtV0gcDe^w@qmkL}({(Bg};%AZyLvuIT-)+U*{7KVYEKtlM=Jz@W z7t=`IUTpq7s(7yqML zq>?9}dr0sntkRhWTO*c<+Fz zp@I|&p%lnt59V5MG0Yh?UPnG|f_@$lIGjhz4f(@z96HIgvP(`) in order to generate yamls from HDL source files and then adjust the yaml to your needs. + +### Port widths + +The width of every port defaults to `1`. +You can specify the width using this notation: + +```yaml +interfaces: + s_axis: + type: AXIStream + mode: slave + signals: + in: + TDATA: [s_axis_tdata, 63, 0] # 64 bits + ... + TVALID: s_axis_tvalid # defaults to 1 bit + +signals: + in: + - [gpio_io_i, 31, 0] # 32 bits +``` + +### Parameterization + +Port widths don't have to be hardcoded - you can use parameters to describe an IP core in a generic way. +Values specified in IP core yamls can be overridden in a design description file (see {ref}`Design Description `). + +```yaml +parameters: + DATA_WIDTH: 8 + KEEP_WIDTH: (DATA_WIDTH+7)/8 + ID_WIDTH: 8 + DEST_WIDTH: 8 + USER_WIDTH: 1 + +interfaces: + s_axis: + type: AXI4Stream + mode: slave + signals: + in: + TDATA: [s_axis_tdata, DATA_WIDTH-1, 0] + TKEEP: [s_axis_tkeep, KEEP_WIDTH-1, 0] + ... + TID: [s_axis_tid, ID_WIDTH-1, 0] + TDEST: [s_axis_tdest, DEST_WIDTH-1, 0] + TUSER: [s_axis_tuser, USER_WIDTH-1, 0] +``` + +Parameters values can be integers or math expressions, which are evaluated using `numexpr.evaluate()`. + +(port-slicing)= + +### Port slicing + +You can also slice a port, to use some bits of the port as a signal that belongs to an interface. +The example below means: + +`Port m_axi_bid of the IP core is 36 bits wide. Use bits 23..12 as the BID signal of AXI master named m_axi_1` + +```yaml +m_axi_1: + type: AXI + mode: master + signals: + in: + BID: [m_axi_bid, 35, 0, 23, 12] +``` + +(interface-description-files)= + +## Interface Description files + +Topwrap can use predefined interfaces described in YAML files that come packaged with the tool. +Currently supported interfaces are AXI4, AXI3, AXI Stream, AXI Lite and Wishbone. + +You can see an example file below: + +```yaml +name: AXI4Stream +port_prefix: AXIS +signals: + # convention assumes the AXI Stream transmitter (master) perspective + required: + out: + TVALID: tvalid + TDATA: tdata + TLAST: tlast + in: + TREADY: tready + optional: + out: + TID: tid + TDEST: tdest + TKEEP: tkeep + TSTRB: tstrb + TUSER: tuser + TWAKEUP: twakeup +``` + +The name of an interface has to be unique. +We also specify a prefix which will be used as a shortened identifier. +Signals are either required or optional. +Their direction is described from the the perspective of master (i.e. directionality of signals in the slave is flipped) - note that clock and reset are not included as these are usually inputs in both master and slave so they're not supported in interface specification. +These distinctions are used when an option to check if all mandatory signals are present is enabled and when parsing an IP core with `topwrap parse` (not all required signals must necessarily be present but it's taken into account). +Every signal is a key-value pair, where the key is a generic signal name (usually from interface specification) and value is a regex that is used to pair the generic name with a concrete signal name in the RTL source when using `topwrap parse`. +This pairing is performed on signal names that are transformed to lowercase and have a common prefix of an interface they belong to removed. +If a regexp occurs in such transformed signal name anywhere, that name is paired with the generic name. +Since this occurs on names that have all characters in lowercase, regex must be written in lowercase as well. diff --git a/_sources/developers_guide/config.md.txt b/_sources/developers_guide/config.md.txt new file mode 100644 index 00000000..1bc31145 --- /dev/null +++ b/_sources/developers_guide/config.md.txt @@ -0,0 +1,19 @@ +# Config + +A {class}`~topwrap.config.Config` object stores configuration values. +A global `topwrap.config.config` object is used throughout the codebase to access topwrap's configuration. +This is created by {class}`~topwrap.config.ConfigManager` that reads config files defined in {attr}`topwrap.config.ConfigManager.DEFAULT_SEARCH_PATHS`, with files most local to the project taking precedence. + +```{eval-rst} +.. autoclass:: topwrap.config.Config + :members: + + .. automethod:: __init__ +``` + +```{eval-rst} +.. autoclass:: topwrap.config.ConfigManager + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/elaboratable_wrapper.md.txt b/_sources/developers_guide/elaboratable_wrapper.md.txt new file mode 100644 index 00000000..68b7605b --- /dev/null +++ b/_sources/developers_guide/elaboratable_wrapper.md.txt @@ -0,0 +1,12 @@ +# ElaboratableWrapper class + +{class}`~topwrap.elaboratable_wrapper.ElaboratableWrapper` encapsulates an Amaranth's Elaboratable and exposes an interface compatible with other wrappers which allows making connections with them. +Supplied elaboratable must contain a `signature` property and a conforming interface as specified by [Amaranth docs](https://amaranth-lang.org/rfcs/0002-interfaces.html). +Ports' directionality, their names and widths are inferred from it. + +```{eval-rst} +.. autoclass:: topwrap.elaboratable_wrapper.ElaboratableWrapper + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/examples.md.txt b/_sources/developers_guide/examples.md.txt new file mode 100644 index 00000000..b85ef58a --- /dev/null +++ b/_sources/developers_guide/examples.md.txt @@ -0,0 +1,17 @@ +# Examples + +:::{note} +Basic usage of examples is explained in the {ref}`getting-started` section. +::: + +Examples provided with this project should cover from very simple designs to complex fully synthesizable cores. +They should be sorted by increasing complexity and number of used features, e.g: +- 101: minimal base design +- 102: introduce user to parameters +- 103: introduce user to slicing +- 104: introduce user to interfaces +- 105: etc. + +Developers are encouraged to create/add new examples in the same spirit. +Simple examples are used to teach how to use this tool and demonstrate its features. +Real-world use cases are also welcome to prove that the implementation is mature enough to handle practical designs. diff --git a/_sources/developers_guide/fusesocbuilder.md.txt b/_sources/developers_guide/fusesocbuilder.md.txt new file mode 100644 index 00000000..464c0c16 --- /dev/null +++ b/_sources/developers_guide/fusesocbuilder.md.txt @@ -0,0 +1,34 @@ +# FuseSocBuilder + +Topwrap has support for generating FuseSoC's core files with {class}`~topwrap.fuse_helper.FuseSocBuilder`. +Such core file contains information about source files and synthesis tools. +Generation is based on a jinja template that defaults to `topwrap/templates/core.yaml.j2` but can be overridden. + +Here's an example of how to generate a simple project: + +```python +from topwrap.fuse_helper import FuseSocBuilder +fuse = FuseSocBuilder() + +# add source of the IPs used in the project +fuse.add_source('DMATop.v', 'verilogSource') + +# add source of the top file +fuse.add_source('top.v', 'verilogSource') + +# specify the names of the Core file and the directory where sources are stored +# generate the project +fuse.build('build/top.core', 'sources') +``` + +:::{warning} +Default template in `topwrap/templates/core.yaml.j2` does not make use of resources added with {meth}`~topwrap.fuse_helper.FuseSocBuilder.add_dependency` or {meth}`~topwrap.fuse_helper.FuseSocBuilder.add_external_ip`, i.e. they won't be present in the generated core file. +::: + + +```{eval-rst} +.. autoclass:: topwrap.fuse_helper.FuseSocBuilder + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/future_enhancements.md.txt b/_sources/developers_guide/future_enhancements.md.txt new file mode 100644 index 00000000..1063013a --- /dev/null +++ b/_sources/developers_guide/future_enhancements.md.txt @@ -0,0 +1,59 @@ +(future-enhancements)= + +# Future enhancements + +(hierarchical-block-designs)= +## Support for hierarchical block design in Pipeline Manager + +Currently topwrap supports creating hierarchical designs only by manually writing the hierarchy in the design description YAML. +Supporting such feature in the Pipeline Manager via its subgraphs would be a huge improvement in terms of organizing complex designs. + +(bus-management)= +## Bus management + +Another goal we'd like to achieve is to enable users to create full-featured designs with processors by providing proper support for bus management. +This should include features such as: + +* ability to specify the address of a peripheral device on the bus +* support for the most popular buses or the ones that we use (AXI, wishbone, Tile-link) + +This will require writing or creating bus arbiters (round-robin, crossbar) and providing a mechanism for connecting master(s) and slave(s) together. +As a result, the user should be able to create complex SoC with Topwrap. + +Currently only experimental support for Wishbone with a round-robin arbiter {ref}`is available `. + +(improve-recreating-design)= +## Improve the process of recreating a design from a YAML file + +One of the main features that are supported by Topwrap and Pipeline Manager is exporting and importing user-created design to or from a design description YAML. However, during these conversions, information about the positions of user-added nodes is not preserved. This is cumbersome in the case of complicated designs since the imported nodes cannot be placed in the optimal positions. + +Therefore, one of our objectives is to provide a convenient way of creating and restoring user-created designs in Pipeline Manager, so that the user doesn't have to worry about node positions when importing a design to Pipeline Manager. + +(systemverilog-parsing)= +## Support for parsing SystemVerilog sources + +Information about IP cores is stored in {ref}`IP core description YAMLs `. These files can be generated automatically from HDL source files - currently Verilog and VHDL are supported. Our goal is to provide the possibility of generating such YAMLs from SystemVerilog too. + +(pm-hdl-parsing)= +## Provide a way to parse HDL sources from the Pipeline Manager level + +Another issue related to HDL parsing is that the user has to manually parse HDL sources to obtain the IP core description YAMLs. Then the files need to be provided as command-line parameters when launching the Topwrap Pipeline Manager client application. Therefore, we aim to provide a way of parsing HDL files and including them in the editor directly from the Pipeline Manager level. + +(toplevel-vhdl)= +## Ability to produce top-level wrappers in VHDL + +Topwrap now uses Amaranth to generate top-level design in Verilog. We would also like to add the ability to produce such designs in VHDL. + +(core-library)= +## Library of open-source cores + +Currently user has to supply all of the cores used in the design manually or semi-manually (e.g. through FuseSoC). +A repository of open-source cores that could be easily reused in topwrap would improve convenience and allow quickly putting together a design from premade hardware blocks. + +(tools-integration)= +## Integrating with other tools + +Topwrap can build the design but testing and synthesis rely on the user - they have to automate this process themselves (e.g. with makefiles). +Ideally the user should be able to write scripts that integrate tools for synthesis, simulation and co-simulation (e.g. with Renode) with topwrap. +Some would come pre-packaged with topwrap (e.g. simulation with verilator, synthesis with vivado). +It should also be possible to invoke these from the Pipeline Manager GUI by using its ability to add custom buttons and integrated terminal. diff --git a/_sources/developers_guide/inline_kpm_howto.md.txt b/_sources/developers_guide/inline_kpm_howto.md.txt new file mode 100644 index 00000000..00d7e9c1 --- /dev/null +++ b/_sources/developers_guide/inline_kpm_howto.md.txt @@ -0,0 +1,61 @@ +# Using KPM iframes inside docs + +It is possible to use the `kpm_iframe` Sphinx directive to embed KPM directly inside a doc. + +## Usage + +```` +```{kpm_iframe} +:spec: +:dataflow: +:preview: +:height: +:alt: +``` +```` + +`URI` can represent either a local file from sources that gets copied into the build directory, or a remote resource. + +All parameters of this directive are optional. + + +## Tests + +### Use remote specification + +:::{note} +The graph below is supposed to be empty. +It doesn't load a dataflow, only a specification that provides IP-cores to the Nodes browser on the sidebar. +::: + +```{kpm_iframe} +:spec: https://raw.githubusercontent.com/antmicro/topwrap/main/tests/data/data_kpm/examples/hdmi/specification_hdmi.json +``` + +### Use local files + +```{kpm_iframe} +:spec: ../../../tests/data/data_kpm/examples/hierarchy/specification_hierarchy.json +:dataflow: ../../../tests/data/data_kpm/examples/hierarchy/dataflow_hierarchy.json +:height: 80vh +``` + +### Open in preview mode + +```{kpm_iframe} +:spec: ../../../tests/data/data_kpm/examples/hierarchy/specification_hierarchy.json +:dataflow: ../../../tests/data/data_kpm/examples/hierarchy/dataflow_hierarchy.json +:preview: true +``` + +### Use custom alt text + +:::{note} +The alternative text is visible instead of the iframe in the PDF version of this documentation. +::: + +```{kpm_iframe} +:spec: ../../../tests/data/data_kpm/examples/hierarchy/specification_hierarchy.json +:dataflow: https://raw.githubusercontent.com/antmicro/topwrap/refs/heads/main/tests/data/data_kpm/examples/hierarchy/dataflow_hierarchy.json +:alt: This diagram showcases the block design of the "hierarchy" example +``` diff --git a/_sources/developers_guide/interface.md.txt b/_sources/developers_guide/interface.md.txt new file mode 100644 index 00000000..03ef37bf --- /dev/null +++ b/_sources/developers_guide/interface.md.txt @@ -0,0 +1,18 @@ +# Interface definition + +Topwrap uses interface definition files for its parsing functionality. +These are used to match a given set of signals that appear in the HDL source with signals in the interface definition. + +{class}`~topwrap.interface.InterfaceDefinition` is defined as a {class}`marshmallow_dataclass.dataclass` - this enables loading YAML structure into Python objects and performs validation (that the YAML has the correct format) and typechecking (that the loaded values are of correct types). + + +```{eval-rst} +.. autoclass:: topwrap.interface.InterfaceDefinition + :members: + + .. automethod:: __init__ +``` + +```{eval-rst} +.. autofunction:: topwrap.interface.get_interface_by_name +``` diff --git a/_sources/developers_guide/ipconnect.md.txt b/_sources/developers_guide/ipconnect.md.txt new file mode 100644 index 00000000..8785b67d --- /dev/null +++ b/_sources/developers_guide/ipconnect.md.txt @@ -0,0 +1,39 @@ +# IPConnect class + +{class}`~topwrap.ipconnect.IPConnect` provides means of connecting ports and interfaces of objects that are subclasses of {class}`~topwrap.wrapper.Wrapper`. +Since {class}`~topwrap.ipconnect.IPConnect` is a subclass of {class}`~topwrap.wrapper.Wrapper` itself, this means that it also has IO - ports and interfaces, and that multiple {class}`~topwrap.ipconnect.IPConnect`s can have their ports and interfaces connected to each other (or other objects that subclass {class}`~topwrap.wrapper.Wrapper`). + +```{image} ../img/ipconnect.png +``` + +Instances of {class}`~topwrap.wrapper.Wrapper` objects can be added to an {class}`~topwrap.ipconnect.IPConnect` using {meth}`~topwrap.ipconnect.IPConnect.add_component` method: + +```python +# create a wrapper for an IP +dma = IPWrapper('DMATop.yaml', ip_name='DMATop', instance_name='DMATop0') +ipc = IPConnect() +ipc.add_component("dma", dma) +``` + +Connections between cores can then be made with {meth}`~topwrap.ipconnect.IPConnect.connect_ports` and {meth}`~topwrap.ipconnect.IPConnect.connect_interfaces` based on names of the components and names of ports/interfaces: + +```python +ipc.connect_ports("comp1_port_name", "comp1_name", "comp2_port_name", "comp2_name") +ipc.connect_interfaces("comp1_interface_name", "comp1_name", "comp2_interface_name", "comp2_name") +``` + +Setting ports or interfaces of a module added to {class}`~topwrap.ipconnect.IPConnect` as external with {meth}`~topwrap.ipconnect.IPConnect._set_port` and {meth}`~topwrap.ipconnect.IPConnect._set_interface` and allows these ports/interfaces to be connected to other {class}`~topwrap.wrapper.Wrapper` instances. +```python +ipc._set_port("comp1_name", "comp1_port_name", "external_port_name") +ipc._set_interface("comp1_name", "comp1_interface_name", "external_interface_name") +``` + +This is done automatically in {meth}`~topwrap.ipconnect.IPConnect.make_connections` method when the design is built based on the data from the YAML design description. + +```{eval-rst} +.. autoclass:: topwrap.ipconnect.IPConnect + :members: + :private-members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/ipwrapper.md.txt b/_sources/developers_guide/ipwrapper.md.txt new file mode 100644 index 00000000..a5ddebcc --- /dev/null +++ b/_sources/developers_guide/ipwrapper.md.txt @@ -0,0 +1,19 @@ +# IPWrapper class + +{class}`~topwrap.ipwrapper.IPWrapper` provides an abstraction over a raw HDL source file. +Instances of this class can be created from a loaded YAML IP-core description. + +Under the hood it will create Amaranth's `Instance` object during elaboration, referencing a particular HDL module and it will appear as a module instantiation in the generated toplevel. +Ports and interfaces (lists of ports) can be retrieved via standard methods of {class}`~topwrap.wrapper.Wrapper`. +These are instances of {class}`~topwrap.amaranth_helpers.WrapperPort`s. + + +```{image} ../img/wrapper.png +``` + +```{eval-rst} +.. autoclass:: topwrap.ipwrapper.IPWrapper + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/parsing.md.txt b/_sources/developers_guide/parsing.md.txt new file mode 100644 index 00000000..3614ea39 --- /dev/null +++ b/_sources/developers_guide/parsing.md.txt @@ -0,0 +1,67 @@ +# Deducing interfaces + +This section describes how inferring interfaces works when using `topwrap parse` with `--iface-deduce`, `--iface` or `--use-yosys` options. + +The problem can be described as follows: given a set of signals, infer what interfaces are present in this set and assign signals to appropriate interfaces. +Interface names and types (AXI4, AXI Stream, Wishbone, etc.) are, in the general case, not given in advance. +Algorithm implemented in topwrap works roughly as follows: + +1. Split the given signal set into disjoint subsets of signals based on common prefixes in their names +2. For a given subset, try to pair each signal name (as it appears in the RTL) with the name of an interface signal (as it is defined in the specification of a particular interface). +This pairing is called "a matching". +Matching with signals from all defined interfaces is tried. +3. For a given subset and matched interface, infer the interface direction (master/slave) based on the direction of some signal in this set. +4. Compute score for each matching, e.g. if signal names contain `cyc`, `stb` and `ack` (and possibly more) it's likely that this set is a Wishbone interface. +Among all interfaces, interface that has the highest matching score is selected. + +## Step 1. - splitting ports into subsets + +First, all ports of a module are grouped into disjoint subsets. Execution of this step differs based on the options supplied to `topwrap parse`: +- with `--iface` the user supplies topwrap with interface names - ports with names starting with a given interface name will be put in the same subset. +- with `--use-yosys` grouping is done by parsing the RTL source with `yosys`, where ports have attributes in the form of `(* interface="interface_name" *)`. +Ports with the same `interface_name` will be put in the same subset. +- with `--iface-deduce` grouping is done by computing longest common prefixes among all ports. +This is done with the help of a [trie](https://en.wikipedia.org/wiki/Trie) and only allows prefixes that would split the port name on an underscore (e.g. in `under_score` valid prefixes are an empty string, `under` and `under_score`) or a camel-case word boundary (e.g. in `wordBoundary` valid prefixes are an empty string, `word` and `wordBoundary`). +As with user-supplied prefixes, ports with names starting with a given prefix will be put in the same subset. + +## Step 2. - matching ports with interface signal names + +Given a subset of ports from a previous step, this step tries to match a regexp from an interface definition YAML for a given interface signal to one of the port names and returns a collection of pairs: RTL port + interface port. +For example, when matching against AXI4, a port named `axi_a_arvalid` should match to an interface port named `ARVALID` in the interface definition YAML. + +This operation is performed for all defined interfaces per a given subset of ports so the overall result of this step is a collection of matchings. +For most interfaces these matching will be poor - e.g. `axi_a_arvalid` or other AXI4 signals won't match to most Wishbone interface signals, but an interface that a human would usually assign to a given set of signals will have the most signals matched. + +## Step 3. - inferring interface direction + +This step picks a representative RTL signal from a single signal matching from the previous step and checks its direction against direction of the corresponding interface signal in interface definition YAML - if it's the same then it's a master interface (since the convention in interface description files is to describe signals from the master's perspective), otherwise it's a slave. + +## Step 4. - computing interface matching score + +This step computes a score for each matching returned by step 2. +This score is based on the number of matched/unmatched optional/required signals in each matching. + +Not matching some signals in a given group (from step 1.) is heavily penalized to encourage selecting interface that "fits" a given group best. +For example, AXI Lite is a subset of AXI4, so a set of signals that should be assigned AXI4 interface could very well fit the description of AXI Lite, but this mechanism discourages selecting such matching in favor of selecting the other. + +Not matching some signals of a given interface (from interface description YAML) is also penalized. +Inverting the previous example, a set of signals that should be assigned AXI Lite interface could very well fit the description of AXI4, but because it's missing a few AXI4 signals so selecting this matching is discouraged in favor of selecting the other. + +### Good scoring function + +A well-behaving scoring function should satisfy some properties to ensure that the best "fitting" interface is selected. +To describe these we introduce the following terminology: +* `>`/`>=`/`==` should be read as "must have a greater/greater or equal/equal score than". +* Partial matching means matching where some rtl signals haven't been matched to interface signals, full matching means matching where all have been matched. + +Current implementation when used with default config values satisfies these properties: + +1. full matching with N+1 signals matched (same type) == full matching with N signals matched (same type) +2. full matching with N signals matched (same type) > partial matching with N signals matched (same type) +3. partial matching with N+1 signals matched (same type) > partial matching with N signals matched (same type) +4. full matching with N+1 required, M+1 optional signals >= full matching with N+1 optional, M optional signals >= full matching with N required, M+1 optional signals >= full matching with N required, M optional signals + +Properties 2-4 generally ensure that interfaces with more signals matched are favored more over those with less signals matched. +Property 1. follows from the current implementation and is not needed in all implementations. + +Full details can be found in the implementation itself. diff --git a/_sources/developers_guide/setup.md.txt b/_sources/developers_guide/setup.md.txt new file mode 100644 index 00000000..2c76d8bf --- /dev/null +++ b/_sources/developers_guide/setup.md.txt @@ -0,0 +1,12 @@ +# Setup + +It is required for developers to keep code style and recommended to frequently run tests. +In order to setup the developer's environment install optional dependency groups `topwrap-parse`, `tests` and `lint` specified in `pyproject.toml` which include `nox` and `pre-commit`: + +```bash +python -m venv venv +source venv/bin/activate +pip install -e ".[topwrap-parse,tests,lint]" +``` + +The `-e` option is for installing in editable mode - meaning changes in the code under development will be immediately visible when using the package. diff --git a/_sources/developers_guide/style.md.txt b/_sources/developers_guide/style.md.txt new file mode 100644 index 00000000..a8f55990 --- /dev/null +++ b/_sources/developers_guide/style.md.txt @@ -0,0 +1,70 @@ +# Code style + +Automatic formatting and linting of the code can be performed with either `nox` or `pre-commit`. + +## Lint with nox + +After successful setup, `nox` sessions can be executed to perform lint checks: + +```bash +nox -s lint +``` + +This runs `isort`, `black`, `flake8` and `codespell` and fixes almost all formatting and linting problems automatically, but a small minority has to be fixed by hand (e.g. unused imports). + +:::{note} +To reuse current virtual environment and avoid long installation time use `-R` option: + +```bash +nox -R -s lint +``` +::: + +:::{note} +pre-commit can also be run from nox: + +```bash +nox -s pre_commit +``` +::: +## Lint with pre-commit + +Alternatively, you can use pre-commit to perform the same job. +`Pre-commit` hooks need to be installed: + +```bash +pre-commit install +``` + +Now, each use of `git commit` in the shell will trigger actions defined in the `.pre-commit-config.yaml` file. +Pre-commit can be easily disabled with a similar command: + +```bash +pre-commit uninstall +``` + +If you wish to run `pre-commit` asynchronously, then use: + +```bash +pre-commit run --all-files +``` + +:::{note} +`pre-commit` by default also runs `nox` with `isort`,`flake8`, `black` and `codespell` sessions +::: + +## Tools + +Tools used in project for maintaining code style: +* `Nox` is a tool, which simplifies management of Python testing. +[Visit nox website](https://nox.thea.codes/en/stable/) +* `Pre-commit` is a framework for managing and maintaining multi-language pre-commit hooks. +[Visit pre-commit website](https://pre-commit.com/) +* `Black` is a code formatter. +[Visit black website](https://black.readthedocs.io/en/stable/) +* `Flake8` is a tool capable of linting, styling fixes and complexity analysis. +[Visit flake8 website](https://flake8.pycqa.org/en/latest/) +* `Isort` is a Python utility to sort imports alphabetically. +[Visit isort website](https://pycqa.github.io/isort/) +* `Codespell` is a Python tool to fix common spelling mistakes in text files +[Visit codespell repository](https://github.com/codespell-project/codespell) diff --git a/_sources/developers_guide/tests.md.txt b/_sources/developers_guide/tests.md.txt new file mode 100644 index 00000000..c91d2db3 --- /dev/null +++ b/_sources/developers_guide/tests.md.txt @@ -0,0 +1,95 @@ +# Tests + +Topwrap functionality is validated with tests, leveraging the `pytest` library. + + +## Test execution + +Tests are located in the `tests` directory. +All tests can be run with `nox` by specifying the `tests` session: + +```bash +nox -s tests +``` + +This only runs tests on python interpreter versions that are available locally. +There is also a session `tests_in_env` that will automatically install all required python versions, provided you have [pyenv](https://github.com/pyenv/pyenv) installed: + +```bash +nox -s tests_in_env +``` + +:::{note} +To reuse existing virtual environment and avoid long installation time use `-R` option: + +```bash +nox -R -s tests_in_env +``` +::: + +To force a specific Python version and avoid running tests for all listed versions, use `-p VERSION` option: + +```bash +nox -p 3.10 -s tests_in_env +``` + +Tests can also be launched without `nox` by executing: +```bash +python -m pytest +``` + +:::{warning} +When running tests by invoking `pytest` directly, tests are ran only on the locally selected python interpreter. +As CI runs them on all supported Python versions it's recommended to run tests with `nox` on all versions before pushing. +::: + +Ignoring particular test can be done with `--ignore=test_path`, e.g: +```bash +python -m pytest --ignore=tests/tests_build/test_interconnect.py +``` + +Sometimes it's useful to see what's being printed by the test for debugging purposes. +Pytest captures all output from the test and displays it when all tests finish. +To see the output immediately, pass `-s` option to pytest: +```bash +python -m pytest -s +``` + +## Test coverage + +Test coverage is automatically generated when running tests with `nox`. +When invoking `pytest` directly it can be generated with `--cov=topwrap` option. +This will generate a summary of coverage displayed in CLI. + +```bash +python -m pytest --cov=topwrap +``` + +Additionally, the summary can be generated in HTML with `--cov=topwrap --cov-report html`, where lines that were not covered by tests can be browsed: + +```bash +python -m pytest --cov=topwrap --cov-report html +``` + +Generated report is available at `htmlcov/index.html` + +## Updating kpm test data + +All kpm data from examples can be generated using nox. +This is useful when changing topwrap functionality related to kpm in order to avoid manually changing every example's test data. +You can either update only one part of examples data like specification or update everything (dataflows, specifications, designs). + +To update everything run: +```bash +nox -s update_test_data +``` + +To update only specifications run: +```bash +nox -s update_test_data -- specification +``` + +Possible options for `update_test_data` session: +* `specification` - updates specifications +* `dataflow` - updates dataflows +* `design` - updates designs diff --git a/_sources/developers_guide/wrapper.md.txt b/_sources/developers_guide/wrapper.md.txt new file mode 100644 index 00000000..7bd6beea --- /dev/null +++ b/_sources/developers_guide/wrapper.md.txt @@ -0,0 +1,11 @@ +# Wrapper + +{class}`~topwrap.wrapper.Wrapper` is an abstraction over entities that have ports - examples include IP cores written in Verilog/VHDL, cores written in Amaranth and hierarchical collections for these that expose some external ports. +Subclasses of this class have to supply implementation of property {meth}`~topwrap.wrapper.Wrapper.get_ports` that has to return a list of all ports of the entity. + +```{eval-rst} +.. autoclass:: topwrap.wrapper.Wrapper + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/wrapper_port.md.txt b/_sources/developers_guide/wrapper_port.md.txt new file mode 100644 index 00000000..fd59289b --- /dev/null +++ b/_sources/developers_guide/wrapper_port.md.txt @@ -0,0 +1,28 @@ +# Wrapper Port + +Class {class}`~topwrap.amaranth_helpers.WrapperPort` is an extension to Amaranth's {class}`Signal`. +It wraps a port, adding a new name and optionally slicing the signal. +It adds these attributes: + +```python +WrapperPort.internal_name # name of the port in internal source to be wrapped +WrapperPort.direction # DIR_FANIN, DIR_FANOUT or DIR_NONE +WrapperPort.interface_name # name of the group of ports (interface) +WrapperPort.bounds # range of bits that belong to the port + # and range which is sliced from the port +``` + +See {ref}`Port slicing ` to know more about `bounds`. + +This is used in {class}`~topwrap.ipwrapper.IPWrapper` class implementation and there should be no need to use {class}`~topwrap.amaranth_helpers.WrapperPort` individually. + +:::{warning} +{class}`~topwrap.amaranth_helpers.WrapperPort` is scheduled to be replaced in favor of plain Amaranth's {class}`Signal` so it should not be used in any new functionality. +::: + +```{eval-rst} +.. autoclass:: topwrap.amaranth_helpers.WrapperPort + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/examples.md.txt b/_sources/examples.md.txt new file mode 100644 index 00000000..d7d7891f --- /dev/null +++ b/_sources/examples.md.txt @@ -0,0 +1,343 @@ +# Example projects + +These example projects show some useful ways in which Topwrap can be used by the end-user. + +:::{admonition} Information about embedded GUI +:class: note + +This section extensively uses an embedded version of Topwrap's GUI, [Kenning Pipeline Manager](kenning-pipeline-manager), to visualize the design of all the examples. + +You can use it to freely explore the entire design, add new blocks, connections, nodes and hierarchies. +You cannot however use features that require direct connection with the Topwrap's backend. +These features include, among others: + +- Saving and loading data from/to `.yaml` files +- Verifying designs +- Building designs +::: + +:::{tip} +Don't forget to use the "Enable fullscreen" button if the viewport feels too small! +```{image} img/kpm_button_fullscreen.png +``` +::: + +## Constant + +[Link to source](https://github.com/antmicro/topwrap/tree/main/examples/constant) + +```{kpm_iframe} +:spec: ../build/kpm_jsons/spec_constant.json +:dataflow: ../build/kpm_jsons/data_constant.json +``` + +There is often a need to pass constant values to input ports of some IP Cores. +This example shows how easy expressing that is in the GUI and correspondingly, in the design description file (`project.yml`). + +:::{tip} +You can find the constant node blueprint in the Nodes browser under the `Metanode` section. +::: + +### Usage + +**Enter the example's directory** +```bash +cd examples/constant +``` + +**Generate HDL source** + +```bash +make generate +``` + + +## Inout + +[Link to source](https://github.com/antmicro/topwrap/tree/main/examples/inout) + +```{kpm_iframe} +:spec: ../build/kpm_jsons/spec_inout.json +:dataflow: ../build/kpm_jsons/data_inout.json +``` + +This example showcases the usage of an inout port and the way it's represented in the GUI. + +:::{tip} +An inout port is denoted in the GUI by a green circle without a directional arrow inside. +::: + +The design consists of 3 modules: input buffer `ibuf`, output buffer `obuf`, and bidirectional buffer `iobuf`. +Their operation can be described as: +* input buffer is a synchronous D-type flip flop with an asynchronous reset +* output buffer is a synchronous D-type flip flop with an asynchronous reset and an `output enable`, which sets output to high impedance state (Hi-Z) +* inout buffer instantiates 1 input and 1 output buffer. Input of the `ibuf` and output of the `obuf` are connected with an inout wire (port). + +### Usage + +**Enter the example's directory** +```bash +cd examples/inout +``` + +:::{admonition} Install required dependencies +:class: note + +```bash +pip install -r requirements.txt +``` +::: + +**Generate bitstream for Zynq** + +```bash +make +``` + +**Generate HDL sources without implementation** + +```bash +make generate +``` + +## User repository + +[Link to source](https://github.com/antmicro/topwrap/tree/main/examples/user_repository) + +```{kpm_iframe} +:spec: ../build/kpm_jsons/spec_user_repository.json +:dataflow: ../build/kpm_jsons/data_user_repository.json +``` + +This example presents a structure of a user repository containing prepackaged IP cores with sources and custom interface definitions, the design file and the config file. +Elements of the `repo` directory can be easily reused in different designs as long as you point to it either in the config file or in the CLI. + +:::{seealso} +For more information about user repositories see [](user_repositories.md). +::: + +:::{tip} +Because other components of the design are automatically imported from the repository, it's possible to load the entire example by specifying just the design file: +```bash +topwrap kpm_client -d project.yml +``` +::: + +### Usage + +Build and run Pipeline Manager server + +```bash +python -m topwrap kpm_build_server +python -m topwrap kpm_run_server +``` + +Navigate to `/examples/user_repository/` directory and run: + +```bash +python -m topwrap kpm_client -d project.yml +``` + +Connect to the web GUI frontend in your browser on `http://127.0.0.1:5000`. + +**Expected result** + +Topwrap will load two cores from the `cores` directory that use an interface from the `interfaces` directory. + +In the Nodes browser under `IPcore`, two loaded cores: `core1` and `core2`, should be visible. + + +## Hierarchy + +[Link to source](https://github.com/antmicro/topwrap/tree/main/examples/hierarchy) + +```{kpm_iframe} +:spec: ../build/kpm_jsons/spec_hierarchy.json +:dataflow: ../build/kpm_jsons/data_hierarchy.json +``` + +This example shows how to create a hierarchical design in Topwrap. +It includes a hierarchy containing some IP cores and other nested hierarchies. + +Check out `project.yml` to learn how does the above design translate to a [design description file](description_files.md) + +:::{seealso} +For more information about hierarchies see [hierarchies docs](hierarchies). +::: + +:::{tip} +Hierarchies are represented in the GUI by nodes with a green header. + +You can display their inner designs by clicking the `Edit subgraph` option from the right click menu. + +To exit from the hierarchy subgraph, find the back arrow button in the top left. + + +To add a new hierarchy node use the `New Graph Node` option in the node browser! +::: + +### Usage +This example contains [user repo](https://antmicro.github.io/topwrap/user_repositories.html) (`repo` directory) and a configuration file for topwrap (`topwrap.yaml`) so it can be loaded by running +``` +python -m topwrap kpm_client -d project.yml +``` +in this example's directory. + + +## PWM + +[Link to source](https://github.com/antmicro/topwrap/tree/main/examples/pwm) + +```{kpm_iframe} +:spec: ../build/kpm_jsons/spec_pwm.json +:dataflow: ../build/kpm_jsons/data_pwm.json +``` + +:::{tip} +The IP Core in the center of the design (`axi_axil_adapter`) showcases how IP Cores with overridable parameters are represented in the GUI. +::: + +This is an example of an AXI-mapped PWM IP Core that can be generated with LiteX being connected to the ZYNQ Processing System. +The Core uses AXILite interface, so a proper `AXI -> AXILite` converter is needed. +You can access its registers starting from address `0x4000000` (that's the base address of `AXI_GP0` on ZYNQ). +The generated signal can be used in FPGA or connected to a physical port on a board. + +:::{note} +To connect the I/O signals to specific FPGA pins, you need proper mappings in a constraints file. See `zynq.xdc` used in the setup and modify it accordingly. +::: + +### Usage + +**Enter the example's directory** +```bash +cd examples/pwm +``` + +:::{admonition} Install required dependencies +:class: note + +```bash +pip install -r requirements.txt +``` + +In order to be able to generate a bitstream you also need to install Vivado and add it to your `PATH`. +::: + +**Generate bitstream for Zynq** + +```bash +make +``` + +**If you wish to generate HDL sources without running Vivado, you can use** + +```bash +make generate +``` + + + +## HDMI + +[Link to source](https://github.com/antmicro/topwrap/tree/main/examples/hdmi) + +```{kpm_iframe} +:spec: ../build/kpm_jsons/spec_hdmi.json +:dataflow: ../build/kpm_jsons/data_hdmi.json +``` + +This is an example on how to use Topwrap to build a complex, synthesizable design. + +### Usage + +**Enter the example's directory** +```bash +cd examples/hdmi +``` + +:::{admonition} Install required dependencies +:class: note + +```bash +pip install -r requirements.txt +``` + +In order to be able to generate a bitstream you also need to install Vivado and add it to your `PATH`. +::: + +**Generate bitstream for desired target** + +Snickerdoodle Black: + +```bash +make snickerdoodle +``` + +Zynq Video Board: + +```bash +make zvb +``` + +**If you wish to generate HDL sources without running Vivado, you can use** + +```bash +make generate +``` + + + +## SoC + +[Link to source](https://github.com/antmicro/topwrap/tree/main/examples/soc) + +```{kpm_iframe} +:spec: ../build/kpm_jsons/spec_soc.json +:dataflow: ../build/kpm_jsons/data_soc.json +``` + +This is an example on how to use Topwrap to build a synthesizable SoC design. +The SoC contains a VexRiscv core, data and instruction memory, UART and interconnect that ties all components together. + +### Usage + +**Enter the example's directory** +```bash +cd examples/soc +``` + +:::{admonition} Install required dependencies +:class: note + +```bash +sudo apt install git make g++ ninja-build gcc-riscv64-unknown-elf bsdextrautils +``` + +To run the simulation you also need: +- verilator + +To create and load bitstream you also need: +- vivado (preferably version 2020.2) +- openFPGALoader ([this branch](https://github.com/antmicro/openFPGALoader/tree/antmicro-ddr-tester-boards)) +::: + + +**Generate HDL sources** + +```bash +make generate +``` + +**Build and run simulation** + +```bash +make sim +``` + +Expected waveform generated by the simulation is shown in `expected-waveform.svg`. + +**Generate bitstream** + +```bash +make bitstream +``` diff --git a/_sources/fusesoc.md.txt b/_sources/fusesoc.md.txt new file mode 100644 index 00000000..023c4f20 --- /dev/null +++ b/_sources/fusesoc.md.txt @@ -0,0 +1,16 @@ +# FuseSoC + +Topwrap uses FuseSoC to automate project generation and build process. +When `topwrap build` is invoked it generates a FuseSoC core file along with the top-level wrapper. + +A template for the core file is bundled with Topwrap (`templates/core.yaml.j2`). +You may need to edit the file to change the backend tool, set additional `Hooks` and change the FPGA part name or other parameters. +By default, {class}`topwrap.fuse_helper.FuseSocBuilder` searches for the template file in the directory you work in, so you should first copy the template into the project's location. + +After generating the core file you can run FuseSoC to generate bitstream and program FPGA: + +```bash +fusesoc --cores-root build run project_1 +``` + +This requires having the suitable backend tool in your `PATH` (Vivado, for example). diff --git a/_sources/getting_started.md.txt b/_sources/getting_started.md.txt new file mode 100644 index 00000000..1a2cb765 --- /dev/null +++ b/_sources/getting_started.md.txt @@ -0,0 +1,220 @@ +(getting-started)= + +# Getting started + +Goal of this chapter is to show step by step how to create simple design with topwrap. + +All necessary files to follow this guide are in `examples/getting_started_demo` directory. + +:::{admonition} Important +:class: attention +This is just an example, if you haven't installed the topwrap yet go to the [Installation chapter](installation.md) and make sure to install additional dependencies for `topwrap parse`. +::: + +## Design overview + +The design we are going to create is visually represented below: + +```{kpm_iframe} +:spec: ../../examples/getting_started_demo/kpm/specification.json +:dataflow: ../../examples/getting_started_demo/kpm/dataflow.json +``` + +It consists of two cores: `simple_core_1` and `simple_core_2` that are connected to each other and to some external metanodes. + +## Parsing verilog files + +First step in creating own designs is to parse verilog files into ip core description yamls that are understood by topwrap. + +In the `verilogs` directory you can find two verilog files which describe `simple_core_1` and `simple_core_2`. + +To generate ip core descriptions from these verilogs run: + +```bash +topwrap parse verilogs/{simple_core_1.v,simple_core_2.v} +``` + +Topwrap will generate two files `gen_simple_core_1.yaml` and `gen_simple_core_2.yaml` that represent corresponding verilogs. + +## Building design with topwrap + +### Creating the design + +Generated ip core yamls can be loaded into GUI. + +1. Build and run gui server +```bash +topwrap kpm_build_server && topwrap kpm_run_server & +``` + +2. Run gui client with the generated ip core yamls +```bash +topwrap kpm_client gen_simple_core_1.yaml gen_simple_core_2.yaml +``` + +Now when you connect to [http://127.0.0.1:5000](http://127.0.0.1:5000) there should be kpm gui. + +Loaded ip cores can be found under IPcore section: + +```{image} img/side_bar_kpm.png +``` + +With these IPcores and default metanodes you can easily create designs by dragging cores and connecting them. + +Let's make the design from the demo that was shown at the beginning of this guide. + +```{image} img/getting_started_project.png +``` + +:::{note} +You can change name of node by right clicking on it and selecting `rename`. +::: + +You can save the project to the [Design Description](description_files.md) format, which is used by topwrap to represent the created design. + +To do this select the graph button and select `Save file`. + +```{image} img/save_graph_kpm.png +``` + +:::{note} +The difference between `Save file` and `Save graph file` lays in which format will be used for saving. + +`Save file` will save the design description in yaml format which topwrap uses. + +`Save graph file` will save the design in graph json format which kpm uses. You should only choose this one if you have some specific custom layout of nodes in design and you want to save it. +::: + +### Generating verilog + +You can generate verilog from design created in previous section. + + +If you have the example running as described in previous section then on the top bar you should see these 4 buttons: + +```{image} img/kpm_buttons.png +``` + +First one is for loading or saving designs. +Second is for toggling node browser. +Third one is for validating the design. +And the fourth is for running the design which will generate the verilog file in `/build` directory of the current example and run the design. + +## Appendix: Command-line flow + +### Creating the design + +Manual creation of designs requires familiarity with [Design Description](description_files.md) format. + +First let's include all the ip core files we will need in the `ips` section. + +```yaml +ips: + simple_core_1: + file: gen_simple_core_1.yaml + simple_core_2: + file: gen_simple_core_2.yaml +``` + +Notice that here we also declare how to node will be named. +Ip core `gen_simple_core_1.yaml` will be named `simple_core_1` in gui. +Now we can start creating the design under the `design` section. +Our design doesn't have any parameters so we can skip this part and go straight into `ports` section. +There we define connections between ip cores. +In demo example there is only one connection - between `gen_simple_core_1` and `gen_simple_core_2`. +In our design it will look like below: + +```yaml +design: + ports: + simple_core_2: + a: + - simple_core_1 + - z +``` + +Notice that we connect `input` to `output`. +All left to do are external connections to metanodes. +We declare them like this: + +```yaml +external: + ports: + in: + - rst + - clk + out: + - Output_y + - Output_c +``` + +Now connect them to ip cores. + +```yaml +design: + ports: + simple_core_1: + clk: clk + rst: rst + simple_core_2: + a: + - simple_core_1 + - z + c: Output_c + y: Output_y +``` + +Final design: + +```yaml +ips: + simple_core_1: + file: gen_simple_core_1.yaml + simple_core_2: + file: gen_simple_core_2.yaml +design: + ports: + simple_core_1: + clk: clk + rst: rst + simple_core_2: + a: + - simple_core_1 + - z + c: Output_c + y: Output_y +external: + ports: + in: + - rst + - clk + out: + - Output_y + - Output_c +``` + +### Generating verilog + +:::{info} +Topwrap uses [Amaranth](https://github.com/amaranth-lang/amaranth) for generating verilog top file. +::: + +To generate top file use `topwrap build` and provide the design. + +Ensure you are in the `examples/getting_started_demo` directory and run: + +```bash +topwrap build --design {design_name.yaml} +``` + +Where the `{design_name.yaml}` is the design saved at the end of previous section. +The generated verilog file can be found in `/build` directory. + +Notice that you will get warning: + +``` +WARNING:root:You did not specify part number. 'None' will be used and thus your implementation may fail. +``` + +It's because we didn't specify any part with `--part` flag since it's just a dummy example that is not for any specific FPGA chip. +For building your designs we recommend specifying the `--part`. diff --git a/_sources/index.md.txt b/_sources/index.md.txt new file mode 100644 index 00000000..ce2fa02e --- /dev/null +++ b/_sources/index.md.txt @@ -0,0 +1,35 @@ +# Welcome to Topwrap! + +```{toctree} +:caption: Documentation +:maxdepth: 2 +introduction +installation +getting_started +examples +description_files +usage +user_repositories +interconnect_gen +fusesoc +``` + +```{toctree} +:caption: Developer's Guide +:maxdepth: 2 +developers_guide/setup +developers_guide/style +developers_guide/tests +developers_guide/wrapper +developers_guide/ipwrapper +developers_guide/ipconnect +developers_guide/elaboratable_wrapper +developers_guide/wrapper_port +developers_guide/fusesocbuilder +developers_guide/interface +developers_guide/config +developers_guide/parsing +developers_guide/examples +developers_guide/future_enhancements +developers_guide/inline_kpm_howto +``` diff --git a/_sources/installation.md.txt b/_sources/installation.md.txt new file mode 100644 index 00000000..d846671a --- /dev/null +++ b/_sources/installation.md.txt @@ -0,0 +1,50 @@ +(installation)= + +# Installation + +1. Install required system packages: + + Debian: + ```bash + apt install -y git g++ make python3 python3-pip antlr4 libantlr4-runtime-dev yosys npm + ``` + + Arch: + ```bash + pacman -Syu git gcc make python3 python-pip antlr4 antlr4-runtime yosys npm + ``` + + Fedora: + ```bash + dnf install git g++ make python3 python3-pip python3-devel antlr4 antlr4-cpp-runtime-devel yosys npm + ``` + +2. Install the Topwrap package (It is highly recommended to run this step in a Python virtual environment, e.g. [venv](https://docs.python.org/3/library/venv.html)): + + ```bash + python3 -m venv venv + source venv/bin/activate + pip install . + ``` + +:::{note} +To use `topwrap parse` command you also need to install optional dependencies: +```bash +pip install ".[topwrap-parse]" +``` +On Arch-based distributions a symlink to antlr4 runtime library needs to created and an environment variable set: +```bash +ln -s /usr/share/java/antlr-complete.jar antlr4-complete.jar +ANTLR_COMPLETE_PATH=`pwd` pip install ".[topwrap-parse]" +``` +On Fedora-based distributions symlinks need to be made inside `/usr/share/java` directory itself: +```bash +sudo ln -s /usr/share/java/stringtemplate4/ST4.jar /usr/share/java/stringtemplate4.jar +sudo ln -s /usr/share/java/antlr4/antlr4.jar /usr/share/java/antlr4.jar +sudo ln -s /usr/share/java/antlr4/antlr4-runtime.jar /usr/share/java/antlr4-runtime.jar +sudo ln -s /usr/share/java/treelayout/org.abego.treelayout.core.jar /usr/share/java/treelayout.jar +pip install ".[topwrap-parse]" +``` +::: + +If you want to contribute to the project please see the [Developer's setup guide](developers_guide/setup.md). diff --git a/_sources/interconnect_gen.md.txt b/_sources/interconnect_gen.md.txt new file mode 100644 index 00000000..a26be4a4 --- /dev/null +++ b/_sources/interconnect_gen.md.txt @@ -0,0 +1,68 @@ +(interconnect-generation)= +# Interconnect generation + +Generating interconnects is an experimental feature of topwrap. +With a specification of which interfaces are masters or slaves and their address ranges, topwrap is able to automatically generate an interconnect conforming to this description. Currently supported interconnect types are: +- Wishbone round-robin + +## Format + +The format for describing interconnects is specified below. `interconnects` key must be a direct descendant of the `design` key in the design description. + +```yaml +interconnects: + {interconnect1_name}: + # specify clock and reset to drive the interconnect with + clock: [{ip_name, clk_port_name}] + reset: [{ip_name, rst_port_name}] + # alternatively you can specify a connection to an external interface: + # clock: ext_clk_port_name + # reset: ext_rst_port_name + + # specify interconnect type + type: {interconnect_type} + + # specify interconnect parameters - interconnect-type-dependent (see "Interconnect params" section): + params: + {param_name1}: param_value1 + ... + + # specify masters and their interfaces connected to the bus + masters: + {master1_name}: + - {master1_iface1_name} + ... + ... + + # specify slaves, their interfaces connected to the bus and their bus parameters + slaves: + {slave1_name}: + {slave1_interface1_name}: + # requests in address range [address, address+size) will be routed to this interface + address: {start_address} + size: {range_size} + ... + ... +``` + +## Interconnect params + +Different interconnect types may provide different configuration options. +This section lists parameter names for available interconnects for use in the `params` section of interconnect specification. + +### Wishbone round-robin + +Corresponds to `type: wishbone_roundrobin` + +- `addr_width` - bit width of the address line (addresses access `data_width`-sized chunks) +- `data_width` - bit width of the data line +- `granularity` - access granularity - smallest unit of data transfer that the interconnect is capable of transferring. Must be one of: 8, 16, 32, 64 +- `features` - optional, list of optional wishbone signals, can contain: `err`, `rty`, `stall`, `lock`, `cti`, `bte` + +## Limitations + +Known limitations currently are: +- only word-sized addressing is supported (in other words - consecutive addresses access word-sized chunks of data) +- crossing clock domains is not supported +- down-converting (initiating multiple transactions on a narrow bus per one transaction on a wider bus) is not supported +- up-converting is not supported diff --git a/_sources/introduction.md.txt b/_sources/introduction.md.txt new file mode 100644 index 00000000..f3f982d4 --- /dev/null +++ b/_sources/introduction.md.txt @@ -0,0 +1,13 @@ +# Introduction + +ASIC and FPGA designs consist of distinct blocks of logic bound together by a top-level design. +To take advantage of this modularity and enable reuse of blocks across designs and so facilitate the shift towards automation in logic design, it is necessary to derive a generic way to aggregate the blocks in various configurations and make the top-level design easy to parse and process automatically. + +Topwrap is an open source command line toolkit for connecting individual HDL modules into full designs of varying complexity. +The toolkit is designed to take advantage of the ever-growing availability of open source digital logic designs and offers a user-friendly graphical interface which lets you mix-and-match GUI-driven design with CLI-based adjustments and present designs in a diagram form thanks to the integration with Antmicro’s [Pipeline Manager](https://github.com/antmicro/kenning-pipeline-manager). + +Topwrap's most notable features are: +* User-friendly GUI +* Parsing HDL design files with automatic recognition of common interfaces +* Simple YAML-based description for command-line use +* Capability to create custom libraries for reuse across projects diff --git a/_sources/usage.md.txt b/_sources/usage.md.txt new file mode 100644 index 00000000..bf7685c9 --- /dev/null +++ b/_sources/usage.md.txt @@ -0,0 +1,155 @@ +# Using topwrap + +(GUI)= +## GUI + +Topwrap can make use of [Kenning Pipeline Manager](https://github.com/antmicro/kenning-pipeline-manager) to visualize the process of creating block design. + +(kenning-pipeline-manager)= + +### Run Topwrap with Pipeline Manager + +1. Build and run Pipeline Manager server + + In order to start creating block design in Pipeline Manager, you need to first build and run a server application - here is a brief instruction on how to achieve this (the process of building and installation of Pipeline Manager is described in detail in its [documentation](https://antmicro.github.io/kenning-pipeline-manager/project-readme.html#building-and-running)): + + ``` + python -m topwrap kpm_build_server + python -m topwrap kpm_run_server + ``` + + After executing the above-mentioned commands, the Pipeline Manager server is waiting for an external application (i.e. Topwrap) to connect on `127.0.0.1:9000` and you can connect to the web GUI frontend in your browser on `http://127.0.0.1:5000`. + +2. Establish connection with Topwrap + + Once the Pipeline Manager server is running, you can now launch Topwrap's client application in order to connect to the server. You need to specify: + * IP address (`127.0.0.1` is default) + * listening port (`9000` is default) + * yamls describing IP cores, that will be used in the block design + * design to load initially (`None` by default) + + An example command, that runs Topwrap's client, may look like this: + ``` + python -m topwrap kpm_client -h 127.0.0.1 -p 9000 \ + topwrap/ips/axi/axi_axil_adapter.yaml \ + examples/pwm/ipcores/{litex_pwm.yml,ps7.yaml} -d examples/pwm/project.yml + ``` +3. Create block design in Pipeline Manager + + Upon successful connection to a Pipeline Manager server, Topwrap will generate and send to the server a specification describing the structure of previously selected IP cores. If the `-d` option was used a design will be shown in gui. From there you can create or modify designs by: + * adding IP core instances to the block design. Each Pipeline Manager's node has `delete` and `rename` options, which make it possible to remove the selected node and change its name respectively. This means that you can create multiple instances of the same IP core. + * adjusting IP cores' parameters values. Each node may have input boxes in which you can enter parameters' values (default parameter values are added while adding an IP core to the block design): + ```{image} img/node_parameters.png + ``` + * connecting IP cores' ports and interfaces. Only connections between ports or interfaces of matching types are allowed. This is automatically checked by Pipeline Manager, as the types of nodes' ports and interfaces are contained in the loaded specification, so Pipeline Manager will prevent you from connecting non-matching interfaces (e.g. *AXI4* with *AXI4Lite* or a port with an interface). A green line will be displayed if a connection is possible to create, or a red line elsewhere: + ```{image} img/invalid_connection.png + ``` + * specifying external ports or interfaces in the top module. This can be done by adding `External Input`, `External Output` or `External Inout` metanodes and creating connections between them and chosen ports or interfaces. Note that you should adjust the name of the external port or interface in a textbox inside selected metanode. In the example below, output port `pwm` of `litex_pwm_top` IP core will be made external in the generated top module and the external port name will be set to `ext_pwm`: + ```{image} img/external_port.png + ``` + Note, that you don't always have to create a new block design by hand - you can use a {ref}`design import ` feature to load an existing block design from a description in Topwrap's yaml format. + + An example block design in Pipeline Manager for the PWM project may look like this: + + ```{image} img/pwm_design.png + ``` + +### Pipeline Manager features + +While creating a custom block design, you can make use of the following Pipeline Manager's features: +* export (save) design to a file +* import (load) design from a file +* validate design +* build design + +(export-design)= + +#### Export design to yaml description file + +Created block design can be saved to a {ref}`design description file ` in yaml format, using Pipeline Manager's `Save file` option. +Target location on the filesystem can then be browsed in a filesystem dialog window. + +(import-design)= + +#### Import design from yaml description file + +Topwrap also supports conversion in the opposite way - block design in Pipeline Manager can be generated from a yaml design description file using `Load file` feature. + +(validate-design)= + +#### Design validation + +Pipeline Manager is capable of performing some basic checks at runtime such as interface type checking while creating a connection. However you can also run more complex tests by using Pipeline Manager's `Validate` option. Topwrap will then respond with a validity confirmation or error messages. The rules you need to follow in order to keep your block design valid are: +* multiple IP cores with the same name are not allowed (except from external metanodes). +* parameters values can be integers of different bases (e.g. `0x28`, `40` or `0b101000`) or arithmetic expressions, that are later evaluated using [numexpr.evaluate()](https://numexpr.readthedocs.io/en/latest/api.html#numexpr.evaluate) function (e.g. `(AXI_DATA_WIDTH+1)/4` is a valid parameter value assuming that a parameter named `AXI_DATA_WIDTH` exists in the same IP core). You can also write a parameter value in a Verilog format (e.g. `8'b00011111` or `8'h1F`) - in such case it will be interpreted as a fixed-width bit vector. +* a single port or interface cannot be external and connected to another IP core at the same time. +* connections between two external metanodes are not allowed. +* all the created external output or inout ports must have unique names. Only multiple input ports of IP cores can be driven be the same external signal. + +Topwrap can also generate warnings if: +* some ports or interfaces remain unconnected. +* multiple ports are connected to an `External Input` metanode with an empty `External Name` property. +* `inout` ports of two modules are connected together (all `inout` ports are required to be directly connected to `External Inout` metanodes) + +If a block design validation returns a warning, it means that the block design can be successfully built, but it is recommended to follow the suggestion and resolve a particular issue. + +(build-design)= + +#### Building design + +Once the design has been created and tested for validity, you can build design using `Run` button. If the design does not contain any errors, this will result in creating a top module in a directory where `topwrap kpm_client` was ran, similarly when using Topwrap's `topwrap build` command. + +## CLI + +Topwrap has a couple CLI only functions that expand gui functionality. + +(generating-ip-yamls)= +### Generating IP core description YAMLs + +You can use Topwrap to generate ip core description yamls from HDL sources to use them in your `project.yml`. +To learn how project and core yamls work check {ref}`design description ` and {ref}`ip description ` + +``` +python -m topwrap parse HDL_FILES +``` + +In HDL source files, ports that belong to the same interface (e.g. wishbone or AXI), +have often a common prefix, which corresponds to the interface name. If such naming +convention is followed in the HDL sources, Topwrap can also divide ports into user-specified +interfaces, or automatically deduce interfaces names when generating yaml file: + +``` +python -m topwrap parse --iface wishbone --iface s_axi HDL_FILES + +python -m topwrap parse --iface-deduce HDL_FILES +``` + +To get help, use: + +``` +python -m topwrap [build|kpm_client|parse] --help +``` + +(building-design)= + +### Building design + +Topwrap can build a synthesizable design from source files connected in a way described by a design file, to do this run: + +``` +python -m topwrap build --design project.yml +``` + +Where `project.yml` should be your file with description of the top module. + +You can specify a directory to be scanned for additional sources: + +``` +python -m topwrap build --sources src --design project.yml +``` + +To implement the design for a specific FPGA chip, provide the part name: + +``` +python -m topwrap build --sources src --design project.yml --part 'xc7z020clg400-3' +``` diff --git a/_sources/user_repositories.md.txt b/_sources/user_repositories.md.txt new file mode 100644 index 00000000..1508eef4 --- /dev/null +++ b/_sources/user_repositories.md.txt @@ -0,0 +1,46 @@ +# Packaging multiple files + +Repositories allow for easy packaging and loading multiple IP-cores and custom interfaces. + +You can specify repositories to be loaded each time topwrap is ran by listing them in a configuration file that should be located in one of the following locations: +``` +topwrap.yaml +~/.config/topwrap/topwrap.yaml +~/.config/topwrap/config.yaml +``` + +Example contents of user config: +``` +force_interface_compliance: true +repositories: + - name: name_of_repo + path: ~/path_to_repo/repo +``` + +Topwrap provides internal API for constructing repositories in python code which can be [found here](https://github.com/antmicro/topwrap/blob/main/topwrap/repo/user_repo.py) + +Structure of repository has to be as follows: +``` +path_to_repository/ +|───cores +| |───someCore1 +| | |───srcs +| | | | file1.v +| | | design.yaml +| | +| |───someCore1 +| |───srcs +| | | file1.v +| | design.yaml +| +|───interfaces(Optional) +| interface1.yaml +| interface2.yaml +``` +Repository has two main directories: `cores` and `interfaces`. + +Inside `cores` each core has it's own directory with it's description file and `srcs` where the verilog/VHDL files are stored. + +The `interfaces` directory is optional, and contains interface description files. + +Example User Repo can be found in [examples/user_repository](https://github.com/antmicro/topwrap/tree/main/examples/user_repository). diff --git a/_static/fonts/0053ba6958e79f26751eabb555bd73d0.woff2 b/_static/fonts/0053ba6958e79f26751eabb555bd73d0.woff2 new file mode 100644 index 0000000000000000000000000000000000000000..ab30100982f087a925abe34641b5909b145516b2 GIT binary patch literal 4728 zcmV-;5{K<~Pew8T0RR9101|ir4gdfE04D$d01_Sm0RR9100000000000000000000 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