From b17d813bcf81334f78ba36484b17dfd367d4b351 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miko=C5=82aj=20Sza=C5=82kowski?= Date: Thu, 10 Oct 2024 14:02:57 +0200 Subject: [PATCH] Regenerate autogenerated YAMLs with inlined fields --- examples/getting_started_demo/project.yml | 4 +- examples/hdmi/project.yml | 299 +++++------------- examples/hierarchy/project.yml | 36 +-- examples/pwm/project.yml | 28 +- examples/user_repository/project.yml | 8 +- tests/data/data_build/clog2/clog2_tester.yaml | 8 +- .../data/data_build/clog2/clog2_tester2.yaml | 8 +- .../conversions/complex/project_complex.yml | 44 +-- .../data_kpm/examples/hdmi/project_hdmi.yml | 299 +++++------------- .../examples/hierarchy/project_hierarchy.yml | 36 +-- .../data_kpm/examples/pwm/project_pwm.yml | 28 +- tests/data/data_parse/axi_axil_adapter.yaml | 222 ++++--------- 12 files changed, 280 insertions(+), 740 deletions(-) diff --git a/examples/getting_started_demo/project.yml b/examples/getting_started_demo/project.yml index 3de4d4c0..70071e7a 100644 --- a/examples/getting_started_demo/project.yml +++ b/examples/getting_started_demo/project.yml @@ -4,9 +4,7 @@ design: clk: clk rst: rst simple_core_2: - a: - - simple_core_1 - - z + a: [simple_core_1, z] c: Output_c y: Output_y external: diff --git a/examples/hdmi/project.yml b/examples/hdmi/project.yml index 76e0f631..32c0a4cb 100644 --- a/examples/hdmi/project.yml +++ b/examples/hdmi/project.yml @@ -1,52 +1,28 @@ design: interfaces: axi_bridge_disp: - s_axi: - - axi_interconnect0 - - m_axi_2 + s_axi: [axi_interconnect0, m_axi_2] axi_bridge_dma: - s_axi: - - axi_interconnect0 - - m_axi_1 + s_axi: [axi_interconnect0, m_axi_1] axi_bridge_mmcm: - s_axi: - - axi_interconnect0 - - m_axi_0 + s_axi: [axi_interconnect0, m_axi_0] axi_interconnect0: - s_axi_0: - - ps7 - - M_AXI_GP0 + s_axi_0: [ps7, M_AXI_GP0] axi_protocol_converter0: - S_AXI: - - dma - - m_axi + S_AXI: [dma, m_axi] axis_clock_converter: - s_axis: - - dma - - m_axis + s_axis: [dma, m_axis] axis_dwidth_converter: - s_axis: - - axis_clock_converter - - m_axis + s_axis: [axis_clock_converter, m_axis] disp: - S00_AXI: - - axi_bridge_disp - - m_axi - S_AXIS: - - axis_dwidth_converter - - m_axis + S00_AXI: [axi_bridge_disp, m_axi] + S_AXIS: [axis_dwidth_converter, m_axis] dma: - s_axi: - - axi_bridge_dma - - m_axi + s_axi: [axi_bridge_dma, m_axi] mmcm: - axi: - - axi_bridge_mmcm - - m_axi + axi: [axi_bridge_mmcm, m_axi] ps7: - S_AXI_HP0: - - axi_protocol_converter0 - - M_AXI + S_AXI_HP0: [axi_protocol_converter0, M_AXI] parameters: axi_bridge_disp: ADDR_WIDTH: 32 @@ -100,109 +76,47 @@ design: OUT_DATA_WIDTH: 32 ports: axi_bridge_disp: - clk: - - ps7 - - FCLK0 - rst: - - reset0 - - bus_struct_reset + clk: [ps7, FCLK0] + rst: [reset0, bus_struct_reset] axi_bridge_dma: - clk: - - ps7 - - FCLK0 - rst: - - reset0 - - bus_struct_reset + clk: [ps7, FCLK0] + rst: [reset0, bus_struct_reset] axi_bridge_mmcm: - clk: - - ps7 - - FCLK0 - rst: - - reset0 - - bus_struct_reset + clk: [ps7, FCLK0] + rst: [reset0, bus_struct_reset] axi_interconnect0: - clk: - - ps7 - - FCLK0 - rst: - - reset0 - - bus_struct_reset + clk: [ps7, FCLK0] + rst: [reset0, bus_struct_reset] axi_protocol_converter0: - aclk: - - ps7 - - FCLK0 - aresetn: - - reset0 - - interconnect_aresetn + aclk: [ps7, FCLK0] + aresetn: [reset0, interconnect_aresetn] axis_clock_converter: - async_rst: - - reset0 - - bus_struct_reset - m_clk: - - mmcm - - clkgen_out0 - s_clk: - - ps7 - - FCLK0 + async_rst: [reset0, bus_struct_reset] + m_clk: [mmcm, clkgen_out0] + s_clk: [ps7, FCLK0] axis_dwidth_converter: - aclk: - - mmcm - - clkgen_out0 - aresetn: - - reset1 - - interconnect_aresetn + aclk: [mmcm, clkgen_out0] + aresetn: [reset1, interconnect_aresetn] clock_crossing: - A: - - disp - - FSYNC_O - clkA: - - mmcm - - clkgen_out0 - clkB: - - ps7 - - FCLK0 + A: [disp, FSYNC_O] + clkA: [mmcm, clkgen_out0] + clkB: [ps7, FCLK0] disp: - LOCKED_I: - - mmcm - - clkgen_locked - S_AXIS_ACLK: - - mmcm - - clkgen_out0 - s00_axi_aclk: - - ps7 - - FCLK0 - s00_axi_aresetn: - - reset0 - - peripheral_aresetn + LOCKED_I: [mmcm, clkgen_locked] + S_AXIS_ACLK: [mmcm, clkgen_out0] + s00_axi_aclk: [ps7, FCLK0] + s00_axi_aresetn: [reset0, peripheral_aresetn] dma: - clock: - - ps7 - - FCLK0 - io_sync_readerSync: - - clock_crossing - - B - io_sync_writerSync: - - clock_crossing - - B - reset: - - reset0 - - peripheral_reset + clock: [ps7, FCLK0] + io_sync_readerSync: [clock_crossing, B] + io_sync_writerSync: [clock_crossing, B] + reset: [reset0, peripheral_reset] hdmi: - CTL: - - disp - - CTL_O - DATA_I: - - disp - - DATA_O - DGUARD: - - disp - - DGUARD_O - DIEN: - - disp - - DIEN_O - DIH: - - disp - - DIH_O + CTL: [disp, CTL_O] + DATA_I: [disp, DATA_O] + DGUARD: [disp, DGUARD_O] + DIEN: [disp, DIEN_O] + DIH: [disp, DIH_O] HDMI_CLK_N: HDMI_CLK_N HDMI_CLK_P: HDMI_CLK_P HDMI_D0_N: HDMI_D0_N @@ -211,111 +125,58 @@ design: HDMI_D1_P: HDMI_D1_P HDMI_D2_N: HDMI_D2_N HDMI_D2_P: HDMI_D2_P - LOCKED_I: - - mmcm - - clkgen_locked - PXLCLK_5X_I: - - mmcm - - clkgen_out1 - PXLCLK_I: - - mmcm - - clkgen_out0 - VGA_DE: - - disp - - DE_O - VGA_HS: - - disp - - HSYNC_O - VGA_VS: - - disp - - VSYNC_O - VGUARD: - - disp - - VGUARD_O + LOCKED_I: [mmcm, clkgen_locked] + PXLCLK_5X_I: [mmcm, clkgen_out1] + PXLCLK_I: [mmcm, clkgen_out0] + VGA_DE: [disp, DE_O] + VGA_HS: [disp, HSYNC_O] + VGA_VS: [disp, VSYNC_O] + VGUARD: [disp, VGUARD_O] mmcm: - clkgen_ref: - - ps7 - - FCLK1 - sys_clk: - - ps7 - - FCLK0 - sys_rst: - - reset0 - - peripheral_reset + clkgen_ref: [ps7, FCLK1] + sys_clk: [ps7, FCLK0] + sys_rst: [reset0, peripheral_reset] ps7: - IRQ_F2P_0: - - dma - - io_irq_readerDone - IRQ_F2P_1: - - dma - - io_irq_writerDone - MAXIGP0ACLK: - - ps7 - - FCLK0 - SAXIHP0ACLK: - - ps7 - - FCLK0 + IRQ_F2P_0: [dma, io_irq_readerDone] + IRQ_F2P_1: [dma, io_irq_writerDone] + MAXIGP0ACLK: [ps7, FCLK0] + SAXIHP0ACLK: [ps7, FCLK0] reset0: aux_reset_in: 0 dcm_locked: 1 ext_reset_in: 0 mb_debug_sys_rst: 0 - slowest_sync_clk: - - ps7 - - FCLK0 + slowest_sync_clk: [ps7, FCLK0] reset1: aux_reset_in: 0 dcm_locked: 1 ext_reset_in: 0 mb_debug_sys_rst: 0 - slowest_sync_clk: - - mmcm - - clkgen_out0 + slowest_sync_clk: [mmcm, clkgen_out0] external: ports: inout: - - - ps7 - - ddr_addr - - - ps7 - - ddr_bankaddr - - - ps7 - - ddr_cas_n - - - ps7 - - ddr_cke - - - ps7 - - ddr_clk - - - ps7 - - ddr_clk_n - - - ps7 - - ddr_cs_n - - - ps7 - - ddr_dm - - - ps7 - - ddr_dq - - - ps7 - - ddr_dqs - - - ps7 - - ddr_dqs_n - - - ps7 - - ddr_drstb - - - ps7 - - ddr_odt - - - ps7 - - ddr_ras_n - - - ps7 - - ddr_vr_n - - - ps7 - - ddr_vr - - - ps7 - - ddr_web - - - ps7 - - ps_mio - - - ps7 - - ps_clk - - - ps7 - - ps_porb - - - ps7 - - ps_srstb + - [ps7, ddr_addr] + - [ps7, ddr_bankaddr] + - [ps7, ddr_cas_n] + - [ps7, ddr_cke] + - [ps7, ddr_clk] + - [ps7, ddr_clk_n] + - [ps7, ddr_cs_n] + - [ps7, ddr_dm] + - [ps7, ddr_dq] + - [ps7, ddr_dqs] + - [ps7, ddr_dqs_n] + - [ps7, ddr_drstb] + - [ps7, ddr_odt] + - [ps7, ddr_ras_n] + - [ps7, ddr_vr_n] + - [ps7, ddr_vr] + - [ps7, ddr_web] + - [ps7, ps_mio] + - [ps7, ps_clk] + - [ps7, ps_porb] + - [ps7, ps_srstb] out: - HDMI_CLK_P - HDMI_CLK_N diff --git a/examples/hierarchy/project.yml b/examples/hierarchy/project.yml index ed039c52..2eb56093 100644 --- a/examples/hierarchy/project.yml +++ b/examples/hierarchy/project.yml @@ -14,14 +14,10 @@ design: cs_s1_f_mod_in_1: cs_s1_mod_in_1 s1_mod_2: cs_s1_f_int_out_1: cs_s1_int_out_1 - cs_s1_mint_in_1: - - s1_mod_1 - - cs_s1_mint_out_1 + cs_s1_mint_in_1: [s1_mod_1, cs_s1_mint_out_1] s1_mod_3: cs_s1_f_int_out_2: cs_s1_int_out_2 - cs_s1_mint_in_2: - - s1_mod_1 - - cs_s1_mint_out_1 + cs_s1_mint_in_2: [s1_mod_1, cs_s1_mint_out_1] external: ports: in: @@ -47,12 +43,8 @@ design: cs_s2_f_int_in_2: cs_s2_int_in_2 s2_mod_2: cs_s2_f_mod_out_1: cs_s2_mod_out_1 - cs_s2_mint_in_1: - - s2_mod_1 - - cs_s2_mint_out_1 - cs_s2_mint_in_2: - - s2_mod_1 - - cs_s2_mint_out_2 + cs_s2_mint_in_1: [s2_mod_1, cs_s2_mint_out_1] + cs_s2_mint_in_2: [s2_mod_1, cs_s2_mint_out_2] external: ports: in: @@ -70,12 +62,8 @@ design: cs_s1_int_const_in: 1 cs_s1_mod_in_1: cs_in_1 sub_2: - cs_s2_int_in_1: - - sub_1 - - cs_s1_int_out_1 - cs_s2_int_in_2: - - sub_1 - - cs_s1_int_out_2 + cs_s2_int_in_1: [sub_1, cs_s1_int_out_1] + cs_s2_int_in_2: [sub_1, cs_s1_int_out_2] cs_s2_mod_out_1: cs_out_1 external: ports: @@ -96,12 +84,8 @@ design: c_mod_in_2: c_in_2 c_mod_3: c_int_const_in: 1 - c_int_in_1: - - c_mod_2 - - c_int_out_2 - c_int_in_2: - - c_mod_1 - - c_int_out_1 + c_int_in_1: [c_mod_2, c_int_out_2] + c_int_in_2: [c_mod_1, c_int_out_1] c_mod_out_1: c_out_1 external: ports: @@ -119,9 +103,7 @@ design: file: repo/cores/c_mod_3/c_mod_3.yaml ports: complex_sub: - cs_in_1: - - counter - - c_out_1 + cs_in_1: [counter, c_out_1] cs_out_1: ex_in_1 counter: c_in_1: ex_out_1 diff --git a/examples/pwm/project.yml b/examples/pwm/project.yml index f7cbbb86..f178eb6e 100644 --- a/examples/pwm/project.yml +++ b/examples/pwm/project.yml @@ -1,13 +1,9 @@ design: interfaces: axi_bridge: - s_axi: - - ps7 - - M_AXI_GP0 + s_axi: [ps7, M_AXI_GP0] litex_pwm_top: - s_axi: - - axi_bridge - - m_axi + s_axi: [axi_bridge, m_axi] parameters: axi_bridge: ADDR_WIDTH: 32 @@ -18,24 +14,14 @@ design: AXI_STRB_WIDTH: AXI_DATA_WIDTH/8 ports: axi_bridge: - clk: - - ps7 - - FCLK0 - rst: - - ps7 - - FCLK_RESET0_N + clk: [ps7, FCLK0] + rst: [ps7, FCLK_RESET0_N] litex_pwm_top: pwm: pwm - sys_clk: - - ps7 - - FCLK0 - sys_rst: - - ps7 - - FCLK_RESET0_N + sys_clk: [ps7, FCLK0] + sys_rst: [ps7, FCLK_RESET0_N] ps7: - MAXIGP0ACLK: - - ps7 - - FCLK0 + MAXIGP0ACLK: [ps7, FCLK0] external: ports: out: diff --git a/examples/user_repository/project.yml b/examples/user_repository/project.yml index c452d4b7..61a096c3 100644 --- a/examples/user_repository/project.yml +++ b/examples/user_repository/project.yml @@ -1,18 +1,14 @@ design: interfaces: core2: - inter_2: - - core1 - - inter_1 + inter_2: [core1, inter_1] ports: core1: in_1: ex_in_1 in_2: ex_in_1 in_3: ex_in_2 core2: - in_1: - - core1 - - out_1 + in_1: [core1, out_1] in_2: ex_in_2 out_1: ex_out_1 external: diff --git a/tests/data/data_build/clog2/clog2_tester.yaml b/tests/data/data_build/clog2/clog2_tester.yaml index 1d2f8f4c..639207bb 100644 --- a/tests/data/data_build/clog2/clog2_tester.yaml +++ b/tests/data/data_build/clog2/clog2_tester.yaml @@ -5,11 +5,7 @@ parameters: w: 1 signals: in: + - [i_waddr, (clog2(depth)-1), 0] - i_clk - - - i_waddr - - (clog2(depth)-1) - - 0 out: - - - o_waddr - - (clog2(depth)-1) - - 0 + - [o_waddr, (clog2(depth)-1), 0] diff --git a/tests/data/data_build/clog2/clog2_tester2.yaml b/tests/data/data_build/clog2/clog2_tester2.yaml index 68b8d144..a6cd57e5 100644 --- a/tests/data/data_build/clog2/clog2_tester2.yaml +++ b/tests/data/data_build/clog2/clog2_tester2.yaml @@ -5,11 +5,7 @@ parameters: w: 1 signals: in: + - [i_waddr, (clog2(depth*2)-2), 0] - i_clk - - - i_waddr - - (clog2(depth*2)-2) - - 0 out: - - - o_waddr - - (clog2(depth*2)-2) - - 0 + - [o_waddr, (clog2(depth*2)-2), 0] diff --git a/tests/data/data_kpm/conversions/complex/project_complex.yml b/tests/data/data_kpm/conversions/complex/project_complex.yml index 20bdf6ea..b88c2346 100644 --- a/tests/data/data_kpm/conversions/complex/project_complex.yml +++ b/tests/data/data_kpm/conversions/complex/project_complex.yml @@ -4,6 +4,11 @@ design: design: hierarchies: BETWEEN: + design: + ports: + c_mod_2: + c_int_out_2: exposed + c_mod_in_2: 666 external: ports: out: @@ -11,11 +16,6 @@ design: ips: c_mod_2: file: examples/hierarchy/repo/cores/c_mod_2/c_mod_2.yaml - design: - ports: - c_mod_2: - c_mod_in_2: 666 - c_int_out_2: exposed SUB: design: parameters: @@ -25,12 +25,8 @@ design: SUB_VALUE: 18 ports: s1_mod_3: - cs_s1_f_int_out_2: - - s1_mod_3_2 - - cs_s1_mint_in_2 - cs_s1_mint_in_2: - - s1_mod_3_2 - - cs_s1_f_int_out_2 + cs_s1_f_int_out_2: [s1_mod_3_2, cs_s1_mint_in_2] + cs_s1_mint_in_2: [s1_mod_3_2, cs_s1_f_int_out_2] s1_mod_3_2: cs_s1_mint_in_2: cs_s1_mint_in_2 s2_mod_1: @@ -55,16 +51,12 @@ design: SUBEMPTY: {} ports: SUB: - cs_s1_mint_in_2: - - BETWEEN - - exposed + cs_s1_mint_in_2: [BETWEEN, exposed] cs_s2_f_int_in_2: customized_ext_name_port - s1_mod_2_2: - cs_s1_mint_in_1: - - s1_mod_2 - - cs_s1_f_int_out_1 s1_mod_2: cs_s1_mint_in_1: legacy_external_type + s1_mod_2_2: + cs_s1_mint_in_1: [s1_mod_2, cs_s1_f_int_out_1] external: ports: in: @@ -86,29 +78,23 @@ design: SUB: customized_ext_name_port: c_unt_in s1_mod_3: - cs_s1_mint_in_2: - - s2_mod_1 - - cs_s2_mint_out_2 + cs_s1_mint_in_2: [s2_mod_1, cs_s2_mint_out_2] s1_mod_3_2: - cs_s1_mint_in_2: - - s1_mod_3 - - cs_s1_f_int_out_2 + cs_s1_mint_in_2: [s1_mod_3, cs_s1_f_int_out_2] s1_mod_3_3: cs_s1_f_int_out_2: cs_s1_f_int_out_2 s2_mod_1: - cs_s2_f_int_in_2: - - s1_mod_3_2 - - cs_s1_f_int_out_2 + cs_s2_f_int_in_2: [s1_mod_3_2, cs_s1_f_int_out_2] external: ports: in: - c_unt_in - cin + inout: + - [SUB, legacy_external_type] out: - cs_s1_f_int_out_2 - cout - inout: - - [SUB, legacy_external_type] ips: s1_mod_3: file: examples/hierarchy/repo/cores/s1_mod_3/s1_mod_3.yaml diff --git a/tests/data/data_kpm/examples/hdmi/project_hdmi.yml b/tests/data/data_kpm/examples/hdmi/project_hdmi.yml index 63e58b40..010ffda7 100644 --- a/tests/data/data_kpm/examples/hdmi/project_hdmi.yml +++ b/tests/data/data_kpm/examples/hdmi/project_hdmi.yml @@ -1,52 +1,28 @@ design: interfaces: axi_bridge_disp: - s_axi: - - axi_interconnect0 - - m_axi_2 + s_axi: [axi_interconnect0, m_axi_2] axi_bridge_dma: - s_axi: - - axi_interconnect0 - - m_axi_1 + s_axi: [axi_interconnect0, m_axi_1] axi_bridge_mmcm: - s_axi: - - axi_interconnect0 - - m_axi_0 + s_axi: [axi_interconnect0, m_axi_0] axi_interconnect0: - s_axi_0: - - ps7 - - M_AXI_GP0 + s_axi_0: [ps7, M_AXI_GP0] axi_protocol_converter0: - S_AXI: - - dma - - m_axi + S_AXI: [dma, m_axi] axis_clock_converter: - s_axis: - - dma - - m_axis + s_axis: [dma, m_axis] axis_dwidth_converter: - s_axis: - - axis_clock_converter - - m_axis + s_axis: [axis_clock_converter, m_axis] disp: - S00_AXI: - - axi_bridge_disp - - m_axi - S_AXIS: - - axis_dwidth_converter - - m_axis + S00_AXI: [axi_bridge_disp, m_axi] + S_AXIS: [axis_dwidth_converter, m_axis] dma: - s_axi: - - axi_bridge_dma - - m_axi + s_axi: [axi_bridge_dma, m_axi] mmcm: - axi: - - axi_bridge_mmcm - - m_axi + axi: [axi_bridge_mmcm, m_axi] ps7: - S_AXI_HP0: - - axi_protocol_converter0 - - M_AXI + S_AXI_HP0: [axi_protocol_converter0, M_AXI] parameters: axi_bridge_disp: ADDR_WIDTH: 32 @@ -100,109 +76,47 @@ design: OUT_DATA_WIDTH: 32 ports: axi_bridge_disp: - clk: - - ps7 - - FCLK0 - rst: - - reset0 - - bus_struct_reset + clk: [ps7, FCLK0] + rst: [reset0, bus_struct_reset] axi_bridge_dma: - clk: - - ps7 - - FCLK0 - rst: - - reset0 - - bus_struct_reset + clk: [ps7, FCLK0] + rst: [reset0, bus_struct_reset] axi_bridge_mmcm: - clk: - - ps7 - - FCLK0 - rst: - - reset0 - - bus_struct_reset + clk: [ps7, FCLK0] + rst: [reset0, bus_struct_reset] axi_interconnect0: - clk: - - ps7 - - FCLK0 - rst: - - reset0 - - bus_struct_reset + clk: [ps7, FCLK0] + rst: [reset0, bus_struct_reset] axi_protocol_converter0: - aclk: - - ps7 - - FCLK0 - aresetn: - - reset0 - - interconnect_aresetn + aclk: [ps7, FCLK0] + aresetn: [reset0, interconnect_aresetn] axis_clock_converter: - async_rst: - - reset0 - - bus_struct_reset - m_clk: - - mmcm - - clkgen_out0 - s_clk: - - ps7 - - FCLK0 + async_rst: [reset0, bus_struct_reset] + m_clk: [mmcm, clkgen_out0] + s_clk: [ps7, FCLK0] axis_dwidth_converter: - aclk: - - mmcm - - clkgen_out0 - aresetn: - - reset1 - - interconnect_aresetn + aclk: [mmcm, clkgen_out0] + aresetn: [reset1, interconnect_aresetn] clock_crossing: - A: - - disp - - FSYNC_O - clkA: - - mmcm - - clkgen_out0 - clkB: - - ps7 - - FCLK0 + A: [disp, FSYNC_O] + clkA: [mmcm, clkgen_out0] + clkB: [ps7, FCLK0] disp: - LOCKED_I: - - mmcm - - clkgen_locked - S_AXIS_ACLK: - - mmcm - - clkgen_out0 - s00_axi_aclk: - - ps7 - - FCLK0 - s00_axi_aresetn: - - reset0 - - peripheral_aresetn + LOCKED_I: [mmcm, clkgen_locked] + S_AXIS_ACLK: [mmcm, clkgen_out0] + s00_axi_aclk: [ps7, FCLK0] + s00_axi_aresetn: [reset0, peripheral_aresetn] dma: - clock: - - ps7 - - FCLK0 - io_sync_readerSync: - - clock_crossing - - B - io_sync_writerSync: - - clock_crossing - - B - reset: - - reset0 - - peripheral_reset + clock: [ps7, FCLK0] + io_sync_readerSync: [clock_crossing, B] + io_sync_writerSync: [clock_crossing, B] + reset: [reset0, peripheral_reset] hdmi: - CTL: - - disp - - CTL_O - DATA_I: - - disp - - DATA_O - DGUARD: - - disp - - DGUARD_O - DIEN: - - disp - - DIEN_O - DIH: - - disp - - DIH_O + CTL: [disp, CTL_O] + DATA_I: [disp, DATA_O] + DGUARD: [disp, DGUARD_O] + DIEN: [disp, DIEN_O] + DIH: [disp, DIH_O] HDMI_CLK_N: HDMI_CLK_N HDMI_CLK_P: HDMI_CLK_P HDMI_D0_N: HDMI_D0_N @@ -211,111 +125,58 @@ design: HDMI_D1_P: HDMI_D1_P HDMI_D2_N: HDMI_D2_N HDMI_D2_P: HDMI_D2_P - LOCKED_I: - - mmcm - - clkgen_locked - PXLCLK_5X_I: - - mmcm - - clkgen_out1 - PXLCLK_I: - - mmcm - - clkgen_out0 - VGA_DE: - - disp - - DE_O - VGA_HS: - - disp - - HSYNC_O - VGA_VS: - - disp - - VSYNC_O - VGUARD: - - disp - - VGUARD_O + LOCKED_I: [mmcm, clkgen_locked] + PXLCLK_5X_I: [mmcm, clkgen_out1] + PXLCLK_I: [mmcm, clkgen_out0] + VGA_DE: [disp, DE_O] + VGA_HS: [disp, HSYNC_O] + VGA_VS: [disp, VSYNC_O] + VGUARD: [disp, VGUARD_O] mmcm: - clkgen_ref: - - ps7 - - FCLK1 - sys_clk: - - ps7 - - FCLK0 - sys_rst: - - reset0 - - peripheral_reset + clkgen_ref: [ps7, FCLK1] + sys_clk: [ps7, FCLK0] + sys_rst: [reset0, peripheral_reset] ps7: - IRQ_F2P_0: - - dma - - io_irq_readerDone - IRQ_F2P_1: - - dma - - io_irq_writerDone - MAXIGP0ACLK: - - ps7 - - FCLK0 - SAXIHP0ACLK: - - ps7 - - FCLK0 + IRQ_F2P_0: [dma, io_irq_readerDone] + IRQ_F2P_1: [dma, io_irq_writerDone] + MAXIGP0ACLK: [ps7, FCLK0] + SAXIHP0ACLK: [ps7, FCLK0] reset0: aux_reset_in: 0 dcm_locked: 1 ext_reset_in: 0 mb_debug_sys_rst: 0 - slowest_sync_clk: - - ps7 - - FCLK0 + slowest_sync_clk: [ps7, FCLK0] reset1: aux_reset_in: 0 dcm_locked: 1 ext_reset_in: 0 mb_debug_sys_rst: 0 - slowest_sync_clk: - - mmcm - - clkgen_out0 + slowest_sync_clk: [mmcm, clkgen_out0] external: ports: inout: - - - ps7 - - ddr_addr - - - ps7 - - ddr_bankaddr - - - ps7 - - ddr_cas_n - - - ps7 - - ddr_cke - - - ps7 - - ddr_clk - - - ps7 - - ddr_clk_n - - - ps7 - - ddr_cs_n - - - ps7 - - ddr_dm - - - ps7 - - ddr_dq - - - ps7 - - ddr_dqs - - - ps7 - - ddr_dqs_n - - - ps7 - - ddr_drstb - - - ps7 - - ddr_odt - - - ps7 - - ddr_ras_n - - - ps7 - - ddr_vr_n - - - ps7 - - ddr_vr - - - ps7 - - ddr_web - - - ps7 - - ps_mio - - - ps7 - - ps_clk - - - ps7 - - ps_porb - - - ps7 - - ps_srstb + - [ps7, ddr_addr] + - [ps7, ddr_bankaddr] + - [ps7, ddr_cas_n] + - [ps7, ddr_cke] + - [ps7, ddr_clk] + - [ps7, ddr_clk_n] + - [ps7, ddr_cs_n] + - [ps7, ddr_dm] + - [ps7, ddr_dq] + - [ps7, ddr_dqs] + - [ps7, ddr_dqs_n] + - [ps7, ddr_drstb] + - [ps7, ddr_odt] + - [ps7, ddr_ras_n] + - [ps7, ddr_vr_n] + - [ps7, ddr_vr] + - [ps7, ddr_web] + - [ps7, ps_mio] + - [ps7, ps_clk] + - [ps7, ps_porb] + - [ps7, ps_srstb] out: - HDMI_CLK_N - HDMI_CLK_P diff --git a/tests/data/data_kpm/examples/hierarchy/project_hierarchy.yml b/tests/data/data_kpm/examples/hierarchy/project_hierarchy.yml index 6836d92b..2708ab4f 100644 --- a/tests/data/data_kpm/examples/hierarchy/project_hierarchy.yml +++ b/tests/data/data_kpm/examples/hierarchy/project_hierarchy.yml @@ -14,14 +14,10 @@ design: cs_s1_f_mod_in_1: cs_s1_mod_in_1 s1_mod_2: cs_s1_f_int_out_1: cs_s1_int_out_1 - cs_s1_mint_in_1: - - s1_mod_1 - - cs_s1_mint_out_1 + cs_s1_mint_in_1: [s1_mod_1, cs_s1_mint_out_1] s1_mod_3: cs_s1_f_int_out_2: cs_s1_int_out_2 - cs_s1_mint_in_2: - - s1_mod_1 - - cs_s1_mint_out_1 + cs_s1_mint_in_2: [s1_mod_1, cs_s1_mint_out_1] external: ports: in: @@ -47,12 +43,8 @@ design: cs_s2_f_int_in_2: cs_s2_int_in_2 s2_mod_2: cs_s2_f_mod_out_1: cs_s2_mod_out_1 - cs_s2_mint_in_1: - - s2_mod_1 - - cs_s2_mint_out_1 - cs_s2_mint_in_2: - - s2_mod_1 - - cs_s2_mint_out_2 + cs_s2_mint_in_1: [s2_mod_1, cs_s2_mint_out_1] + cs_s2_mint_in_2: [s2_mod_1, cs_s2_mint_out_2] external: ports: in: @@ -70,12 +62,8 @@ design: cs_s1_int_const_in: 1 cs_s1_mod_in_1: cs_in_1 sub_2: - cs_s2_int_in_1: - - sub_1 - - cs_s1_int_out_1 - cs_s2_int_in_2: - - sub_1 - - cs_s1_int_out_2 + cs_s2_int_in_1: [sub_1, cs_s1_int_out_1] + cs_s2_int_in_2: [sub_1, cs_s1_int_out_2] cs_s2_mod_out_1: cs_out_1 external: ports: @@ -96,12 +84,8 @@ design: c_mod_in_2: c_in_2 c_mod_3: c_int_const_in: 1 - c_int_in_1: - - c_mod_2 - - c_int_out_2 - c_int_in_2: - - c_mod_1 - - c_int_out_1 + c_int_in_1: [c_mod_2, c_int_out_2] + c_int_in_2: [c_mod_1, c_int_out_1] c_mod_out_1: c_out_1 external: ports: @@ -119,9 +103,7 @@ design: file: examples/hierarchy/repo/cores/c_mod_3/c_mod_3.yaml ports: complex_sub: - cs_in_1: - - counter - - c_out_1 + cs_in_1: [counter, c_out_1] cs_out_1: ex_in_1 counter: c_in_1: ex_out_1 diff --git a/tests/data/data_kpm/examples/pwm/project_pwm.yml b/tests/data/data_kpm/examples/pwm/project_pwm.yml index 8565d0c8..7b02c93e 100644 --- a/tests/data/data_kpm/examples/pwm/project_pwm.yml +++ b/tests/data/data_kpm/examples/pwm/project_pwm.yml @@ -1,13 +1,9 @@ design: interfaces: axi_bridge: - s_axi: - - ps7 - - M_AXI_GP0 + s_axi: [ps7, M_AXI_GP0] litex_pwm_top: - s_axi: - - axi_bridge - - m_axi + s_axi: [axi_bridge, m_axi] parameters: axi_bridge: ADDR_WIDTH: 32 @@ -18,24 +14,14 @@ design: AXI_STRB_WIDTH: AXI_DATA_WIDTH/8 ports: axi_bridge: - clk: - - ps7 - - FCLK0 - rst: - - ps7 - - FCLK_RESET0_N + clk: [ps7, FCLK0] + rst: [ps7, FCLK_RESET0_N] litex_pwm_top: pwm: pwm - sys_clk: - - ps7 - - FCLK0 - sys_rst: - - ps7 - - FCLK_RESET0_N + sys_clk: [ps7, FCLK0] + sys_rst: [ps7, FCLK_RESET0_N] ps7: - MAXIGP0ACLK: - - ps7 - - FCLK0 + MAXIGP0ACLK: [ps7, FCLK0] external: ports: out: diff --git a/tests/data/data_parse/axi_axil_adapter.yaml b/tests/data/data_parse/axi_axil_adapter.yaml index 994e6df0..bc5f5f60 100644 --- a/tests/data/data_parse/axi_axil_adapter.yaml +++ b/tests/data/data_parse/axi_axil_adapter.yaml @@ -1,171 +1,81 @@ -name: axi_axil_adapter -parameters: - ADDR_WIDTH: 32 - AXI_DATA_WIDTH: 32 - AXI_STRB_WIDTH: (AXI_DATA_WIDTH/8) - AXI_ID_WIDTH: 8 - AXIL_DATA_WIDTH: 32 - AXIL_STRB_WIDTH: (AXIL_DATA_WIDTH/8) - CONVERT_BURST: 1 - CONVERT_NARROW_BURST: 0 -signals: - in: - - clk - - rst interfaces: + m_axil: + mode: master + signals: + in: + ARREADY: m_axil_arready + AWREADY: m_axil_awready + BRESP: [m_axil_bresp, 1, 0] + BVALID: m_axil_bvalid + RDATA: [m_axil_rdata, (AXIL_DATA_WIDTH-1), 0] + RRESP: [m_axil_rresp, 1, 0] + RVALID: m_axil_rvalid + WREADY: m_axil_wready + out: + ARADDR: [m_axil_araddr, (ADDR_WIDTH-1), 0] + ARPROT: [m_axil_arprot, 2, 0] + ARVALID: m_axil_arvalid + AWADDR: [m_axil_awaddr, (ADDR_WIDTH-1), 0] + AWPROT: [m_axil_awprot, 2, 0] + AWVALID: m_axil_awvalid + BREADY: m_axil_bready + RREADY: m_axil_rready + WDATA: [m_axil_wdata, (AXIL_DATA_WIDTH-1), 0] + WSTRB: [m_axil_wstrb, (AXIL_STRB_WIDTH-1), 0] + WVALID: m_axil_wvalid + type: AXI4Lite s_axi: + mode: slave signals: in: - ARCACHE: - - s_axi_arcache - - 3 - - 0 - ARBURST: - - s_axi_arburst - - 1 - - 0 - AWBURST: - - s_axi_awburst - - 1 - - 0 + ARADDR: [s_axi_araddr, (ADDR_WIDTH-1), 0] + ARBURST: [s_axi_arburst, 1, 0] + ARCACHE: [s_axi_arcache, 3, 0] + ARID: [s_axi_arid, (AXI_ID_WIDTH-1), 0] + ARLEN: [s_axi_arlen, 7, 0] + ARLOCK: s_axi_arlock + ARPROT: [s_axi_arprot, 2, 0] + ARSIZE: [s_axi_arsize, 2, 0] ARVALID: s_axi_arvalid - AWCACHE: - - s_axi_awcache - - 3 - - 0 + AWADDR: [s_axi_awaddr, (ADDR_WIDTH-1), 0] + AWBURST: [s_axi_awburst, 1, 0] + AWCACHE: [s_axi_awcache, 3, 0] + AWID: [s_axi_awid, (AXI_ID_WIDTH-1), 0] + AWLEN: [s_axi_awlen, 7, 0] + AWLOCK: s_axi_awlock + AWPROT: [s_axi_awprot, 2, 0] + AWSIZE: [s_axi_awsize, 2, 0] AWVALID: s_axi_awvalid - ARPROT: - - s_axi_arprot - - 2 - - 0 - AWPROT: - - s_axi_awprot - - 2 - - 0 BREADY: s_axi_bready - ARLOCK: s_axi_arlock RREADY: s_axi_rready - ARSIZE: - - s_axi_arsize - - 2 - - 0 - ARADDR: - - s_axi_araddr - - (ADDR_WIDTH-1) - - 0 - AWSIZE: - - s_axi_awsize - - 2 - - 0 - AWADDR: - - s_axi_awaddr - - (ADDR_WIDTH-1) - - 0 - WVALID: s_axi_wvalid - AWLOCK: s_axi_awlock - AWLEN: - - s_axi_awlen - - 7 - - 0 - WDATA: - - s_axi_wdata - - (AXI_DATA_WIDTH-1) - - 0 + WDATA: [s_axi_wdata, (AXI_DATA_WIDTH-1), 0] WLAST: s_axi_wlast - WSTRB: - - s_axi_wstrb - - (AXI_STRB_WIDTH-1) - - 0 - ARLEN: - - s_axi_arlen - - 7 - - 0 - AWID: - - s_axi_awid - - (AXI_ID_WIDTH-1) - - 0 - ARID: - - s_axi_arid - - (AXI_ID_WIDTH-1) - - 0 + WSTRB: [s_axi_wstrb, (AXI_STRB_WIDTH-1), 0] + WVALID: s_axi_wvalid out: ARREADY: s_axi_arready AWREADY: s_axi_awready - WREADY: s_axi_wready - RVALID: s_axi_rvalid + BID: [s_axi_bid, (AXI_ID_WIDTH-1), 0] + BRESP: [s_axi_bresp, 1, 0] BVALID: s_axi_bvalid + RDATA: [s_axi_rdata, (AXI_DATA_WIDTH-1), 0] + RID: [s_axi_rid, (AXI_ID_WIDTH-1), 0] RLAST: s_axi_rlast - RDATA: - - s_axi_rdata - - (AXI_DATA_WIDTH-1) - - 0 - RRESP: - - s_axi_rresp - - 1 - - 0 - BRESP: - - s_axi_bresp - - 1 - - 0 - RID: - - s_axi_rid - - (AXI_ID_WIDTH-1) - - 0 - BID: - - s_axi_bid - - (AXI_ID_WIDTH-1) - - 0 + RRESP: [s_axi_rresp, 1, 0] + RVALID: s_axi_rvalid + WREADY: s_axi_wready type: AXI3 - mode: slave - m_axil: - signals: - in: - ARREADY: m_axil_arready - AWREADY: m_axil_awready - WREADY: m_axil_wready - RVALID: m_axil_rvalid - BVALID: m_axil_bvalid - RDATA: - - m_axil_rdata - - (AXIL_DATA_WIDTH-1) - - 0 - RRESP: - - m_axil_rresp - - 1 - - 0 - BRESP: - - m_axil_bresp - - 1 - - 0 - out: - ARVALID: m_axil_arvalid - AWVALID: m_axil_awvalid - AWPROT: - - m_axil_awprot - - 2 - - 0 - BREADY: m_axil_bready - WVALID: m_axil_wvalid - ARADDR: - - m_axil_araddr - - (ADDR_WIDTH-1) - - 0 - AWADDR: - - m_axil_awaddr - - (ADDR_WIDTH-1) - - 0 - RREADY: m_axil_rready - ARPROT: - - m_axil_arprot - - 2 - - 0 - WDATA: - - m_axil_wdata - - (AXIL_DATA_WIDTH-1) - - 0 - WSTRB: - - m_axil_wstrb - - (AXIL_STRB_WIDTH-1) - - 0 - type: AXI4Lite - mode: master +name: axi_axil_adapter +parameters: + ADDR_WIDTH: 32 + AXIL_DATA_WIDTH: 32 + AXIL_STRB_WIDTH: (AXIL_DATA_WIDTH/8) + AXI_DATA_WIDTH: 32 + AXI_ID_WIDTH: 8 + AXI_STRB_WIDTH: (AXI_DATA_WIDTH/8) + CONVERT_BURST: 1 + CONVERT_NARROW_BURST: 0 +signals: + in: + - clk + - rst