From ecc30b8f8def5fcd05d93869d66b84ed748ab846 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Krzysztof=20Ob=C5=82onczek?=
 <koblonczek@internships.antmicro.com>
Date: Tue, 9 Jan 2024 01:39:22 +0100
Subject: [PATCH] Fix compatibility with Python 3.8
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

- Change cache decorator to lru_cache, as cache decorator is only available
since Python 3.9 and is an alias for lru_cache(maxsize=None)
- Change Python 3.9-style type annotations to older Python 3.8-style - using
(lowercase) list or tuple with subscript type wasn't supported until Python 3.9
- Replace | dict operator that isn't available until Python 3.9 with .update()

Internal-tag: [#53526]
Signed-off-by: Krzysztof Obłonczek <koblonczek@internships.antmicro.com>
---
 fpga_topwrap/elaboratable_wrapper.py          | 22 +++++++++++--------
 .../tests_build/test_elaboratable_wrapper.py  | 15 +++++++------
 2 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/fpga_topwrap/elaboratable_wrapper.py b/fpga_topwrap/elaboratable_wrapper.py
index 92fedbb7..fa43be02 100644
--- a/fpga_topwrap/elaboratable_wrapper.py
+++ b/fpga_topwrap/elaboratable_wrapper.py
@@ -1,8 +1,8 @@
 # Copyright (C) 2023 Antmicro
 # SPDX-License-Identifier: Apache-2.0
 
-from functools import cache
-from typing import Iterable, Mapping, Union
+from functools import lru_cache
+from typing import Iterable, List, Mapping, Union
 
 from amaranth import *
 from amaranth.build import Platform
@@ -35,7 +35,7 @@ def __init__(self, name: str, elaboratable: Elaboratable) -> None:
             port_width=1, port_flow=wiring.In, name="rst", port_name="rst", iface_name=""
         )
 
-    def get_ports(self) -> list[WrapperPort]:
+    def get_ports(self) -> List[WrapperPort]:
         """Return a list of external ports."""
         return self._flatten_hier(self.get_ports_hier())
 
@@ -43,12 +43,16 @@ def get_ports_hier(self) -> SignalMapping:
         """Maps elaboratable's Signature to a nested dictionary of WrapperPorts.
         See _gather_signature_ports for more details.
         """
-        return self._gather_signature_ports(self.elaboratable.signature) | {
-            "clk": self.clk,
-            "rst": self.rst,
-        }
+        ports = self._gather_signature_ports(self.elaboratable.signature)
+        ports.update(
+            {
+                "clk": self.clk,
+                "rst": self.rst,
+            }
+        )
+        return ports
 
-    @cache
+    @lru_cache(maxsize=None)
     def _cached_wrapper(
         self, port_width: int, port_flow: wiring.Flow, name: str, port_name: str, iface_name: str
     ) -> WrapperPort:
@@ -136,7 +140,7 @@ def _flatten_hier(self, hier: SignalMapping) -> Iterable[Signal]:
             ports += [hier]
         return ports
 
-    def _connect_ports(self, ports: SignalMapping, iface: InterfaceLike) -> list[Assign]:
+    def _connect_ports(self, ports: SignalMapping, iface: InterfaceLike) -> List[Assign]:
         """Returns a list of amaranth assignments between the wrapped elaboratable and external ports.
 
         :param ports: nested dictionary of WrapperPorts mirroring that of iface's signature
diff --git a/tests/tests_build/test_elaboratable_wrapper.py b/tests/tests_build/test_elaboratable_wrapper.py
index f43873c4..40fbb992 100644
--- a/tests/tests_build/test_elaboratable_wrapper.py
+++ b/tests/tests_build/test_elaboratable_wrapper.py
@@ -3,7 +3,7 @@
 # Copyright (C) 2023 Antmicro
 # SPDX-License-Identifier: Apache-2.0
 
-from typing import Callable, Union
+from typing import Callable, List, Tuple, Union
 
 import pytest
 from amaranth import *
@@ -115,7 +115,7 @@ def nested_signature_mapping() -> SignalMapping:
 
 
 @pytest.fixture
-def flattened_nested_signature_mapping() -> list[WrapperPort]:
+def flattened_nested_signature_mapping() -> List[WrapperPort]:
     return [
         WrapperPort(
             bounds=[15, 0, 15, 0],
@@ -217,7 +217,7 @@ def clock_domain_signals(elaboratable_wrapper: ElaboratableWrapper) -> SignalMap
 @pytest.fixture
 def interface_connections(
     elaboratable: Elaboratable, nested_signature_mapping: SignalMapping
-) -> list[tuple[Signal, Signal]]:
+) -> List[Tuple[Signal, Signal]]:
     m = elaboratable
     d = nested_signature_mapping
     return [
@@ -269,7 +269,7 @@ def test_flatten_hier(
         self,
         elaboratable_wrapper: ElaboratableWrapper,
         nested_signature_mapping: SignalMapping,
-        flattened_nested_signature_mapping: list[WrapperPort],
+        flattened_nested_signature_mapping: List[WrapperPort],
     ) -> None:
         def ordering(p):
             return p.name
@@ -299,12 +299,13 @@ def test_get_ports_hier(
         clock_domain_signals: SignalMapping,
     ) -> None:
         hier_ports = elaboratable_wrapper.get_ports_hier()
-        assert signal_mapping_eq(hier_ports, nested_signature_mapping | clock_domain_signals)
+        nested_signature_mapping.update(clock_domain_signals)
+        assert signal_mapping_eq(hier_ports, nested_signature_mapping)
 
     def test_get_ports(
         self,
         elaboratable_wrapper: ElaboratableWrapper,
-        flattened_nested_signature_mapping: list[WrapperPort],
+        flattened_nested_signature_mapping: List[WrapperPort],
         clock_domain_signals: SignalMapping,
     ) -> None:
         def ordering(p):
@@ -322,7 +323,7 @@ def test_connect_ports(
         elaboratable_wrapper: ElaboratableWrapper,
         nested_signature_mapping: SignalMapping,
         elaboratable: Elaboratable,
-        interface_connections: list[tuple[Signal, Signal]],
+        interface_connections: List[Tuple[Signal, Signal]],
     ) -> None:
         conns_test = sorted(
             elaboratable_wrapper._connect_ports(nested_signature_mapping, elaboratable),