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Build and run Pipeline Manager server application. + +``` +python -m topwrap kpm_build_server +python -m topwrap kpm_run_server +``` + +2. Run Topwrap's client application, that will connect to a running Pipeline Manager server app. + +``` +python -m topwrap kpm_client [-h ip_addr] [-p port] [-d FILE] FILES +``` + +Topwrap will then try to connect to the server running on `ip_addr:port` and send a specification generated from `FILES`, which should be IP core description yamls. + +If `-h` or `-p` options are not specified, ip address `127.0.0.1` and port `9000` will be chosen by default. + +If `-d` option is specified, kpm will start with specified design file loaded. + +(generating-ip-yamls)= + +## Generating IP core description YAMLs + +You can also use Topwrap to generate ip core description yamls from HDL sources, +that can be later used in your `project.yml`: + +``` +python -m topwrap parse HDL_FILES +``` + +In HDL source files, ports that belong to the same interface (e.g. wishbone or AXI), +have often a common prefix, which corresponds to the interface name. If such naming +convention is followed in the HDL sources, Topwrap can also divide ports into user-specified +interfaces, or automatically deduce interfaces names when generating yaml file: + +``` +python -m topwrap parse --iface wishbone --iface s_axi HDL_FILES + +python -m topwrap parse --iface-deduce HDL_FILES +``` + +To get help, use: + +``` +python -m topwrap [build|kpm_client|parse] --help +``` diff --git a/_sources/description_files.md.txt b/_sources/description_files.md.txt new file mode 100644 index 00000000..a97566f1 --- /dev/null +++ b/_sources/description_files.md.txt @@ -0,0 +1,256 @@ +(description-files)= + +# Description files + +(design-description)= + +## Design Description + +To create a complete, fully synthesizable design, a proper design file is needed. +It's used to specify interconnects, IP cores, set their parameters' values, describe hierarchies for the project, +connect the IPs and hierarchies, and pick external ports (those which will be connected to physical I/O). + +You can see example design files in `examples` directory. The structure is as below: + +```yaml +ips: + # specify relations between IPs names in the design yaml + # and IP cores description yamls and modules + {ip_instance_name}: + file: {path_to_yaml_file_of_the_ip} + module: {name_of_the_HDL_module} + ... + +design: + name: {design_name} # optional name of the toplevel + hierarchies: + # see "Hierarchies" page for a detailed description of the format + ... + parameters: # specify IPs parameter values to be overridden + {ip_instance_name}: + {param_name} : {param_value} + ... + + ports: + # specify incoming ports connections of an IP named `ip1_name` + {ip1_name}: + {port1_name} : [{ip2_name}, {port2_name}] + ... + # specify incoming ports connections of a hierarchy named `hier_name` + {hier_name}: + {port1_name} : [{ip_name}, {port2_name}] + ... + # specify external ports connections + {ip_instance_name}: + {port_name} : ext_port_name + ... + + interfaces: + # specify incoming interfaces connections of `ip1_name` IP + {ip1_name}: + {iface1_name} : [{ip2_name}, {iface2_name}] + ... + # specify incoming interfaces connections of `hier_name` hierarchy + {hier_name}: + {iface1_name} : [{ip_name}, {iface2_name}] + ... + # specify external interfaces connections + {ip_instance_name}: + {iface_name} : ext_iface_name + ... + + interconnects: + # see "Interconnect generation" page for a detailed description of the format + ... + +external: # specify names of external ports and interfaces of the top module + ports: + out: + - {ext_port_name} + inout: + - [{ip_name/hierarchy_name, port_name}] + interfaces: + in: + - {ext_iface_name} + # note that `inout:` is invalid in the interfaces section +``` + +`inout` ports are handled differently than `in` and `out` ports. When any IP has an inout port or when a hierarchy has an inout port specified in its `external.ports.inout` section, it must be included in `external.ports.inout` section of the parent design by specifying the name of the IP/hierarchy and port name that contains it. Name of the external port will be identical to the one in the IP core. In case of duplicate names a suffix `$n` is added (where `n` is a natural number) to the name of the second and subsequent duplicate names. `inout` ports cannot be connected to each other. + +The design description yaml format allows creating hierarchical designs. In order to create a hierarchy, it suffices to add its name as a key in the `design` section and describe the hierarchy design "recursively" by using the same keys and values (`ports`, `parameters` etc.) as in the top-level design (see above). Hierarchies can be nested recursively, which means that you can create a hierarchy inside another one. + +Note that IPs and hierarchies names cannot be duplicated on the same hierarchy level. For example, the `design` section cannot contain two identical keys, but it's correct to have `ip_name` key in this section and `ip_name` in the `design` section of some hierarchy. + +(ip-description)= + +## IP description files + +Every IP wrapped by Topwrap needs a description file in YAML format. + +The ports of an IP should be placed in global `signals` node, followed by the direction of `in`, `out` or `inout`. +Here's an example description of ports of Clock Crossing IP: + +```yaml +# file: clock_crossing.yaml +signals: + in: + - clkA + - A + - clkB + out: + - B +``` + +The previous example is enough to make use of any IP. However, in order to benefit from connecting whole interfaces at once, ports must belong to a named interface like in this example: + +```yaml +#file: axis_width_converter.yaml +interfaces: + s_axis: + type: AXIStream + mode: slave + signals: + in: + TDATA: [s_axis_tdata, 63, 0] + TKEEP: [s_axis_tkeep, 7, 0] + TVALID: s_axis_tvalid + TLAST: s_axis_tlast + TID: [s_axis_tid, 7, 0] + TDEST: [s_axis_tdest, 7, 0] + TUSER: s_axis_tuser + out: + TREADY: s_axis_tready + + m_axis: + type: AXIStream + mode: master + signals: + in: + TREADY: m_axis_tready + out: + TDATA: [m_axis_tdata, 31, 0] + TKEEP: [m_axis_tkeep, 3, 0] + TVALID: m_axis_tvalid + TLAST: m_axis_tlast + TID: [m_axis_tid, 7, 0] + TDEST: [m_axis_tdest, 7, 0] + TUSER: m_axis_tuser +signals: # These ports don't belong to any interface + in: + - clk + - rst +``` + +Names `s_axis` and `m_axis` will be used to group the selected ports. +Each signal in an interface has a name which must match with the signal it's supposed to be connected to, for example `TDATA: port_name` will be connected to `TDATA: other_port_name`. + +Note that you don't have to write IP core description yamls by hand. You can use Topwrap's `parse` command (see {ref}`Generating IP core description YAMLs `) in order to generate yamls from HDL source files and then adjust the yaml to your needs. + +### Port widths + +The width of every port defaults to `1`. +You can specify the width using this notation: + +```yaml +interfaces: + s_axis: + type: AXIStream + mode: slave + signals: + in: + TDATA: [s_axis_tdata, 63, 0] # 64 bits + ... + TVALID: s_axis_tvalid # defaults to 1 bit + +signals: + in: + - [gpio_io_i, 31, 0] # 32 bits +``` + +### Parameterization + +Port widths don't have to be hardcoded - you can use parameters to describe an IP core in a generic way. +Values specified in IP core yamls can be overridden in a design description file (see {ref}`Design Description `). + +```yaml +parameters: + DATA_WIDTH: 8 + KEEP_WIDTH: (DATA_WIDTH+7)/8 + ID_WIDTH: 8 + DEST_WIDTH: 8 + USER_WIDTH: 1 + +interfaces: + s_axis: + type: AXI4Stream + mode: slave + signals: + in: + TDATA: [s_axis_tdata, DATA_WIDTH-1, 0] + TKEEP: [s_axis_tkeep, KEEP_WIDTH-1, 0] + ... + TID: [s_axis_tid, ID_WIDTH-1, 0] + TDEST: [s_axis_tdest, DEST_WIDTH-1, 0] + TUSER: [s_axis_tuser, USER_WIDTH-1, 0] +``` + +Parameters values can be integers or math expressions, which are evaluated using `numexpr.evaluate()`. + +(port-slicing)= + +### Port slicing + +You can also slice a port, to use some bits of the port as a signal that belongs to an interface. +The example below means: + +`Port m_axi_bid of the IP core is 36 bits wide. Use bits 23..12 as the BID signal of AXI master named m_axi_1` + +```yaml +m_axi_1: + type: AXI + mode: master + signals: + in: + BID: [m_axi_bid, 35, 0, 23, 12] +``` + +(interface-description-files)= + +## Interface Description files + +Topwrap can use predefined interfaces described in YAML files that come packaged with the tool. +Currently supported interfaces are AXI4, AXI3, AXI Stream, AXI Lite and Wishbone. + +You can see an example file below: + +```yaml +name: AXI4Stream +port_prefix: AXIS +signals: + # convention assumes the AXI Stream transmitter (master) perspective + required: + out: + TVALID: tvalid + TDATA: tdata + TLAST: tlast + in: + TREADY: tready + optional: + out: + TID: tid + TDEST: tdest + TKEEP: tkeep + TSTRB: tstrb + TUSER: tuser + TWAKEUP: twakeup +``` + +The name of an interface has to be unique. +We also specify a prefix which will be used as a shortened identifier. +Signals are either required or optional. +Their direction is described from the the perspective of master (i.e. directionality of signals in the slave is flipped) - note that clock and reset are not included as these are usually inputs in both master and slave so they're not supported in interface specification. +These distinctions are used when an option to check if all mandatory signals are present is enabled and when parsing an IP core with `topwrap parse` (not all required signals must necessarily be present but it's taken into account). +Every signal is a key-value pair, where the key is a generic signal name (usually from interface specification) and value is a regex that is used to pair the generic name with a concrete signal name in the RTL source when using `topwrap parse`. +This pairing is performed on signal names that are transformed to lowercase and have a common prefix of an interface they belong to removed. +If a regexp occurs in such transformed signal name anywhere, that name is paired with the generic name. +Since this occurs on names that have all characters in lowercase, regex must be written in lowercase as well. diff --git a/_sources/developers_guide/config.md.txt b/_sources/developers_guide/config.md.txt new file mode 100644 index 00000000..1bc31145 --- /dev/null +++ b/_sources/developers_guide/config.md.txt @@ -0,0 +1,19 @@ +# Config + +A {class}`~topwrap.config.Config` object stores configuration values. +A global `topwrap.config.config` object is used throughout the codebase to access topwrap's configuration. +This is created by {class}`~topwrap.config.ConfigManager` that reads config files defined in {attr}`topwrap.config.ConfigManager.DEFAULT_SEARCH_PATHS`, with files most local to the project taking precedence. + +```{eval-rst} +.. autoclass:: topwrap.config.Config + :members: + + .. automethod:: __init__ +``` + +```{eval-rst} +.. autoclass:: topwrap.config.ConfigManager + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/elaboratable_wrapper.md.txt b/_sources/developers_guide/elaboratable_wrapper.md.txt new file mode 100644 index 00000000..68b7605b --- /dev/null +++ b/_sources/developers_guide/elaboratable_wrapper.md.txt @@ -0,0 +1,12 @@ +# ElaboratableWrapper class + +{class}`~topwrap.elaboratable_wrapper.ElaboratableWrapper` encapsulates an Amaranth's Elaboratable and exposes an interface compatible with other wrappers which allows making connections with them. +Supplied elaboratable must contain a `signature` property and a conforming interface as specified by [Amaranth docs](https://amaranth-lang.org/rfcs/0002-interfaces.html). +Ports' directionality, their names and widths are inferred from it. + +```{eval-rst} +.. autoclass:: topwrap.elaboratable_wrapper.ElaboratableWrapper + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/examples.md.txt b/_sources/developers_guide/examples.md.txt new file mode 100644 index 00000000..b85ef58a --- /dev/null +++ b/_sources/developers_guide/examples.md.txt @@ -0,0 +1,17 @@ +# Examples + +:::{note} +Basic usage of examples is explained in the {ref}`getting-started` section. +::: + +Examples provided with this project should cover from very simple designs to complex fully synthesizable cores. +They should be sorted by increasing complexity and number of used features, e.g: +- 101: minimal base design +- 102: introduce user to parameters +- 103: introduce user to slicing +- 104: introduce user to interfaces +- 105: etc. + +Developers are encouraged to create/add new examples in the same spirit. +Simple examples are used to teach how to use this tool and demonstrate its features. +Real-world use cases are also welcome to prove that the implementation is mature enough to handle practical designs. diff --git a/_sources/developers_guide/fusesocbuilder.md.txt b/_sources/developers_guide/fusesocbuilder.md.txt new file mode 100644 index 00000000..464c0c16 --- /dev/null +++ b/_sources/developers_guide/fusesocbuilder.md.txt @@ -0,0 +1,34 @@ +# FuseSocBuilder + +Topwrap has support for generating FuseSoC's core files with {class}`~topwrap.fuse_helper.FuseSocBuilder`. +Such core file contains information about source files and synthesis tools. +Generation is based on a jinja template that defaults to `topwrap/templates/core.yaml.j2` but can be overridden. + +Here's an example of how to generate a simple project: + +```python +from topwrap.fuse_helper import FuseSocBuilder +fuse = FuseSocBuilder() + +# add source of the IPs used in the project +fuse.add_source('DMATop.v', 'verilogSource') + +# add source of the top file +fuse.add_source('top.v', 'verilogSource') + +# specify the names of the Core file and the directory where sources are stored +# generate the project +fuse.build('build/top.core', 'sources') +``` + +:::{warning} +Default template in `topwrap/templates/core.yaml.j2` does not make use of resources added with {meth}`~topwrap.fuse_helper.FuseSocBuilder.add_dependency` or {meth}`~topwrap.fuse_helper.FuseSocBuilder.add_external_ip`, i.e. they won't be present in the generated core file. +::: + + +```{eval-rst} +.. autoclass:: topwrap.fuse_helper.FuseSocBuilder + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/future_enhancements.md.txt b/_sources/developers_guide/future_enhancements.md.txt new file mode 100644 index 00000000..1063013a --- /dev/null +++ b/_sources/developers_guide/future_enhancements.md.txt @@ -0,0 +1,59 @@ +(future-enhancements)= + +# Future enhancements + +(hierarchical-block-designs)= +## Support for hierarchical block design in Pipeline Manager + +Currently topwrap supports creating hierarchical designs only by manually writing the hierarchy in the design description YAML. +Supporting such feature in the Pipeline Manager via its subgraphs would be a huge improvement in terms of organizing complex designs. + +(bus-management)= +## Bus management + +Another goal we'd like to achieve is to enable users to create full-featured designs with processors by providing proper support for bus management. +This should include features such as: + +* ability to specify the address of a peripheral device on the bus +* support for the most popular buses or the ones that we use (AXI, wishbone, Tile-link) + +This will require writing or creating bus arbiters (round-robin, crossbar) and providing a mechanism for connecting master(s) and slave(s) together. +As a result, the user should be able to create complex SoC with Topwrap. + +Currently only experimental support for Wishbone with a round-robin arbiter {ref}`is available `. + +(improve-recreating-design)= +## Improve the process of recreating a design from a YAML file + +One of the main features that are supported by Topwrap and Pipeline Manager is exporting and importing user-created design to or from a design description YAML. However, during these conversions, information about the positions of user-added nodes is not preserved. This is cumbersome in the case of complicated designs since the imported nodes cannot be placed in the optimal positions. + +Therefore, one of our objectives is to provide a convenient way of creating and restoring user-created designs in Pipeline Manager, so that the user doesn't have to worry about node positions when importing a design to Pipeline Manager. + +(systemverilog-parsing)= +## Support for parsing SystemVerilog sources + +Information about IP cores is stored in {ref}`IP core description YAMLs `. These files can be generated automatically from HDL source files - currently Verilog and VHDL are supported. Our goal is to provide the possibility of generating such YAMLs from SystemVerilog too. + +(pm-hdl-parsing)= +## Provide a way to parse HDL sources from the Pipeline Manager level + +Another issue related to HDL parsing is that the user has to manually parse HDL sources to obtain the IP core description YAMLs. Then the files need to be provided as command-line parameters when launching the Topwrap Pipeline Manager client application. Therefore, we aim to provide a way of parsing HDL files and including them in the editor directly from the Pipeline Manager level. + +(toplevel-vhdl)= +## Ability to produce top-level wrappers in VHDL + +Topwrap now uses Amaranth to generate top-level design in Verilog. We would also like to add the ability to produce such designs in VHDL. + +(core-library)= +## Library of open-source cores + +Currently user has to supply all of the cores used in the design manually or semi-manually (e.g. through FuseSoC). +A repository of open-source cores that could be easily reused in topwrap would improve convenience and allow quickly putting together a design from premade hardware blocks. + +(tools-integration)= +## Integrating with other tools + +Topwrap can build the design but testing and synthesis rely on the user - they have to automate this process themselves (e.g. with makefiles). +Ideally the user should be able to write scripts that integrate tools for synthesis, simulation and co-simulation (e.g. with Renode) with topwrap. +Some would come pre-packaged with topwrap (e.g. simulation with verilator, synthesis with vivado). +It should also be possible to invoke these from the Pipeline Manager GUI by using its ability to add custom buttons and integrated terminal. diff --git a/_sources/developers_guide/interface.md.txt b/_sources/developers_guide/interface.md.txt new file mode 100644 index 00000000..03ef37bf --- /dev/null +++ b/_sources/developers_guide/interface.md.txt @@ -0,0 +1,18 @@ +# Interface definition + +Topwrap uses interface definition files for its parsing functionality. +These are used to match a given set of signals that appear in the HDL source with signals in the interface definition. + +{class}`~topwrap.interface.InterfaceDefinition` is defined as a {class}`marshmallow_dataclass.dataclass` - this enables loading YAML structure into Python objects and performs validation (that the YAML has the correct format) and typechecking (that the loaded values are of correct types). + + +```{eval-rst} +.. autoclass:: topwrap.interface.InterfaceDefinition + :members: + + .. automethod:: __init__ +``` + +```{eval-rst} +.. autofunction:: topwrap.interface.get_interface_by_name +``` diff --git a/_sources/developers_guide/ipconnect.md.txt b/_sources/developers_guide/ipconnect.md.txt new file mode 100644 index 00000000..8785b67d --- /dev/null +++ b/_sources/developers_guide/ipconnect.md.txt @@ -0,0 +1,39 @@ +# IPConnect class + +{class}`~topwrap.ipconnect.IPConnect` provides means of connecting ports and interfaces of objects that are subclasses of {class}`~topwrap.wrapper.Wrapper`. +Since {class}`~topwrap.ipconnect.IPConnect` is a subclass of {class}`~topwrap.wrapper.Wrapper` itself, this means that it also has IO - ports and interfaces, and that multiple {class}`~topwrap.ipconnect.IPConnect`s can have their ports and interfaces connected to each other (or other objects that subclass {class}`~topwrap.wrapper.Wrapper`). + +```{image} ../img/ipconnect.png +``` + +Instances of {class}`~topwrap.wrapper.Wrapper` objects can be added to an {class}`~topwrap.ipconnect.IPConnect` using {meth}`~topwrap.ipconnect.IPConnect.add_component` method: + +```python +# create a wrapper for an IP +dma = IPWrapper('DMATop.yaml', ip_name='DMATop', instance_name='DMATop0') +ipc = IPConnect() +ipc.add_component("dma", dma) +``` + +Connections between cores can then be made with {meth}`~topwrap.ipconnect.IPConnect.connect_ports` and {meth}`~topwrap.ipconnect.IPConnect.connect_interfaces` based on names of the components and names of ports/interfaces: + +```python +ipc.connect_ports("comp1_port_name", "comp1_name", "comp2_port_name", "comp2_name") +ipc.connect_interfaces("comp1_interface_name", "comp1_name", "comp2_interface_name", "comp2_name") +``` + +Setting ports or interfaces of a module added to {class}`~topwrap.ipconnect.IPConnect` as external with {meth}`~topwrap.ipconnect.IPConnect._set_port` and {meth}`~topwrap.ipconnect.IPConnect._set_interface` and allows these ports/interfaces to be connected to other {class}`~topwrap.wrapper.Wrapper` instances. +```python +ipc._set_port("comp1_name", "comp1_port_name", "external_port_name") +ipc._set_interface("comp1_name", "comp1_interface_name", "external_interface_name") +``` + +This is done automatically in {meth}`~topwrap.ipconnect.IPConnect.make_connections` method when the design is built based on the data from the YAML design description. + +```{eval-rst} +.. autoclass:: topwrap.ipconnect.IPConnect + :members: + :private-members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/ipwrapper.md.txt b/_sources/developers_guide/ipwrapper.md.txt new file mode 100644 index 00000000..a5ddebcc --- /dev/null +++ b/_sources/developers_guide/ipwrapper.md.txt @@ -0,0 +1,19 @@ +# IPWrapper class + +{class}`~topwrap.ipwrapper.IPWrapper` provides an abstraction over a raw HDL source file. +Instances of this class can be created from a loaded YAML IP-core description. + +Under the hood it will create Amaranth's `Instance` object during elaboration, referencing a particular HDL module and it will appear as a module instantiation in the generated toplevel. +Ports and interfaces (lists of ports) can be retrieved via standard methods of {class}`~topwrap.wrapper.Wrapper`. +These are instances of {class}`~topwrap.amaranth_helpers.WrapperPort`s. + + +```{image} ../img/wrapper.png +``` + +```{eval-rst} +.. autoclass:: topwrap.ipwrapper.IPWrapper + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/parsing.md.txt b/_sources/developers_guide/parsing.md.txt new file mode 100644 index 00000000..3614ea39 --- /dev/null +++ b/_sources/developers_guide/parsing.md.txt @@ -0,0 +1,67 @@ +# Deducing interfaces + +This section describes how inferring interfaces works when using `topwrap parse` with `--iface-deduce`, `--iface` or `--use-yosys` options. + +The problem can be described as follows: given a set of signals, infer what interfaces are present in this set and assign signals to appropriate interfaces. +Interface names and types (AXI4, AXI Stream, Wishbone, etc.) are, in the general case, not given in advance. +Algorithm implemented in topwrap works roughly as follows: + +1. Split the given signal set into disjoint subsets of signals based on common prefixes in their names +2. For a given subset, try to pair each signal name (as it appears in the RTL) with the name of an interface signal (as it is defined in the specification of a particular interface). +This pairing is called "a matching". +Matching with signals from all defined interfaces is tried. +3. For a given subset and matched interface, infer the interface direction (master/slave) based on the direction of some signal in this set. +4. Compute score for each matching, e.g. if signal names contain `cyc`, `stb` and `ack` (and possibly more) it's likely that this set is a Wishbone interface. +Among all interfaces, interface that has the highest matching score is selected. + +## Step 1. - splitting ports into subsets + +First, all ports of a module are grouped into disjoint subsets. Execution of this step differs based on the options supplied to `topwrap parse`: +- with `--iface` the user supplies topwrap with interface names - ports with names starting with a given interface name will be put in the same subset. +- with `--use-yosys` grouping is done by parsing the RTL source with `yosys`, where ports have attributes in the form of `(* interface="interface_name" *)`. +Ports with the same `interface_name` will be put in the same subset. +- with `--iface-deduce` grouping is done by computing longest common prefixes among all ports. +This is done with the help of a [trie](https://en.wikipedia.org/wiki/Trie) and only allows prefixes that would split the port name on an underscore (e.g. in `under_score` valid prefixes are an empty string, `under` and `under_score`) or a camel-case word boundary (e.g. in `wordBoundary` valid prefixes are an empty string, `word` and `wordBoundary`). +As with user-supplied prefixes, ports with names starting with a given prefix will be put in the same subset. + +## Step 2. - matching ports with interface signal names + +Given a subset of ports from a previous step, this step tries to match a regexp from an interface definition YAML for a given interface signal to one of the port names and returns a collection of pairs: RTL port + interface port. +For example, when matching against AXI4, a port named `axi_a_arvalid` should match to an interface port named `ARVALID` in the interface definition YAML. + +This operation is performed for all defined interfaces per a given subset of ports so the overall result of this step is a collection of matchings. +For most interfaces these matching will be poor - e.g. `axi_a_arvalid` or other AXI4 signals won't match to most Wishbone interface signals, but an interface that a human would usually assign to a given set of signals will have the most signals matched. + +## Step 3. - inferring interface direction + +This step picks a representative RTL signal from a single signal matching from the previous step and checks its direction against direction of the corresponding interface signal in interface definition YAML - if it's the same then it's a master interface (since the convention in interface description files is to describe signals from the master's perspective), otherwise it's a slave. + +## Step 4. - computing interface matching score + +This step computes a score for each matching returned by step 2. +This score is based on the number of matched/unmatched optional/required signals in each matching. + +Not matching some signals in a given group (from step 1.) is heavily penalized to encourage selecting interface that "fits" a given group best. +For example, AXI Lite is a subset of AXI4, so a set of signals that should be assigned AXI4 interface could very well fit the description of AXI Lite, but this mechanism discourages selecting such matching in favor of selecting the other. + +Not matching some signals of a given interface (from interface description YAML) is also penalized. +Inverting the previous example, a set of signals that should be assigned AXI Lite interface could very well fit the description of AXI4, but because it's missing a few AXI4 signals so selecting this matching is discouraged in favor of selecting the other. + +### Good scoring function + +A well-behaving scoring function should satisfy some properties to ensure that the best "fitting" interface is selected. +To describe these we introduce the following terminology: +* `>`/`>=`/`==` should be read as "must have a greater/greater or equal/equal score than". +* Partial matching means matching where some rtl signals haven't been matched to interface signals, full matching means matching where all have been matched. + +Current implementation when used with default config values satisfies these properties: + +1. full matching with N+1 signals matched (same type) == full matching with N signals matched (same type) +2. full matching with N signals matched (same type) > partial matching with N signals matched (same type) +3. partial matching with N+1 signals matched (same type) > partial matching with N signals matched (same type) +4. full matching with N+1 required, M+1 optional signals >= full matching with N+1 optional, M optional signals >= full matching with N required, M+1 optional signals >= full matching with N required, M optional signals + +Properties 2-4 generally ensure that interfaces with more signals matched are favored more over those with less signals matched. +Property 1. follows from the current implementation and is not needed in all implementations. + +Full details can be found in the implementation itself. diff --git a/_sources/developers_guide/setup.md.txt b/_sources/developers_guide/setup.md.txt new file mode 100644 index 00000000..2c76d8bf --- /dev/null +++ b/_sources/developers_guide/setup.md.txt @@ -0,0 +1,12 @@ +# Setup + +It is required for developers to keep code style and recommended to frequently run tests. +In order to setup the developer's environment install optional dependency groups `topwrap-parse`, `tests` and `lint` specified in `pyproject.toml` which include `nox` and `pre-commit`: + +```bash +python -m venv venv +source venv/bin/activate +pip install -e ".[topwrap-parse,tests,lint]" +``` + +The `-e` option is for installing in editable mode - meaning changes in the code under development will be immediately visible when using the package. diff --git a/_sources/developers_guide/style.md.txt b/_sources/developers_guide/style.md.txt new file mode 100644 index 00000000..a8f55990 --- /dev/null +++ b/_sources/developers_guide/style.md.txt @@ -0,0 +1,70 @@ +# Code style + +Automatic formatting and linting of the code can be performed with either `nox` or `pre-commit`. + +## Lint with nox + +After successful setup, `nox` sessions can be executed to perform lint checks: + +```bash +nox -s lint +``` + +This runs `isort`, `black`, `flake8` and `codespell` and fixes almost all formatting and linting problems automatically, but a small minority has to be fixed by hand (e.g. unused imports). + +:::{note} +To reuse current virtual environment and avoid long installation time use `-R` option: + +```bash +nox -R -s lint +``` +::: + +:::{note} +pre-commit can also be run from nox: + +```bash +nox -s pre_commit +``` +::: +## Lint with pre-commit + +Alternatively, you can use pre-commit to perform the same job. +`Pre-commit` hooks need to be installed: + +```bash +pre-commit install +``` + +Now, each use of `git commit` in the shell will trigger actions defined in the `.pre-commit-config.yaml` file. +Pre-commit can be easily disabled with a similar command: + +```bash +pre-commit uninstall +``` + +If you wish to run `pre-commit` asynchronously, then use: + +```bash +pre-commit run --all-files +``` + +:::{note} +`pre-commit` by default also runs `nox` with `isort`,`flake8`, `black` and `codespell` sessions +::: + +## Tools + +Tools used in project for maintaining code style: +* `Nox` is a tool, which simplifies management of Python testing. +[Visit nox website](https://nox.thea.codes/en/stable/) +* `Pre-commit` is a framework for managing and maintaining multi-language pre-commit hooks. +[Visit pre-commit website](https://pre-commit.com/) +* `Black` is a code formatter. +[Visit black website](https://black.readthedocs.io/en/stable/) +* `Flake8` is a tool capable of linting, styling fixes and complexity analysis. +[Visit flake8 website](https://flake8.pycqa.org/en/latest/) +* `Isort` is a Python utility to sort imports alphabetically. +[Visit isort website](https://pycqa.github.io/isort/) +* `Codespell` is a Python tool to fix common spelling mistakes in text files +[Visit codespell repository](https://github.com/codespell-project/codespell) diff --git a/_sources/developers_guide/tests.md.txt b/_sources/developers_guide/tests.md.txt new file mode 100644 index 00000000..3a9a9131 --- /dev/null +++ b/_sources/developers_guide/tests.md.txt @@ -0,0 +1,74 @@ +# Tests + +Topwrap functionality is validated with tests, leveraging the `pytest` library. + + +## Test execution + +Tests are located in the `tests` directory. +All tests can be run with `nox` by specifying the `tests` session: + +```bash +nox -s tests +``` + +This only runs tests on python interpreter versions that are available locally. +There is also a session `tests_in_env` that will automatically install all required python versions, provided you have [pyenv](https://github.com/pyenv/pyenv) installed: + +```bash +nox -s tests_in_env +``` + +:::{note} +To reuse existing virtual environment and avoid long installation time use `-R` option: + +```bash +nox -R -s tests_in_env +``` +::: + +To force a specific Python version and avoid running tests for all listed versions, use `-p VERSION` option: + +```bash +nox -p 3.10 -s tests_in_env +``` + +Tests can also be launched without `nox` by executing: +```bash +python -m pytest +``` + +:::{warning} +When running tests by invoking `pytest` directly, tests are ran only on the locally selected python interpreter. +As CI runs them on all supported Python versions it's recommended to run tests with `nox` on all versions before pushing. +::: + +Ignoring particular test can be done with `--ignore=test_path`, e.g: +```bash +python -m pytest --ignore=tests/tests_build/test_interconnect.py +``` + +Sometimes it's useful to see what's being printed by the test for debugging purposes. +Pytest captures all output from the test and displays it when all tests finish. +To see the output immediately, pass `-s` option to pytest: +```bash +python -m pytest -s +``` + +## Test coverage + +Test coverage is automatically generated when running tests with `nox`. +When invoking `pytest` directly it can be generated with `--cov=topwrap` option. +This will generate a summary of coverage displayed in CLI. + +```bash +python -m pytest --cov=topwrap +``` + +Additionally, the summary can be generated in HTML with `--cov=topwrap --cov-report html`, where lines that were not covered by tests can be browsed: + +```bash +python -m pytest --cov=topwrap --cov-report html +``` + +Generated report is available at `htmlcov/index.html` diff --git a/_sources/developers_guide/wrapper.md.txt b/_sources/developers_guide/wrapper.md.txt new file mode 100644 index 00000000..7bd6beea --- /dev/null +++ b/_sources/developers_guide/wrapper.md.txt @@ -0,0 +1,11 @@ +# Wrapper + +{class}`~topwrap.wrapper.Wrapper` is an abstraction over entities that have ports - examples include IP cores written in Verilog/VHDL, cores written in Amaranth and hierarchical collections for these that expose some external ports. +Subclasses of this class have to supply implementation of property {meth}`~topwrap.wrapper.Wrapper.get_ports` that has to return a list of all ports of the entity. + +```{eval-rst} +.. autoclass:: topwrap.wrapper.Wrapper + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/developers_guide/wrapper_port.md.txt b/_sources/developers_guide/wrapper_port.md.txt new file mode 100644 index 00000000..fd59289b --- /dev/null +++ b/_sources/developers_guide/wrapper_port.md.txt @@ -0,0 +1,28 @@ +# Wrapper Port + +Class {class}`~topwrap.amaranth_helpers.WrapperPort` is an extension to Amaranth's {class}`Signal`. +It wraps a port, adding a new name and optionally slicing the signal. +It adds these attributes: + +```python +WrapperPort.internal_name # name of the port in internal source to be wrapped +WrapperPort.direction # DIR_FANIN, DIR_FANOUT or DIR_NONE +WrapperPort.interface_name # name of the group of ports (interface) +WrapperPort.bounds # range of bits that belong to the port + # and range which is sliced from the port +``` + +See {ref}`Port slicing ` to know more about `bounds`. + +This is used in {class}`~topwrap.ipwrapper.IPWrapper` class implementation and there should be no need to use {class}`~topwrap.amaranth_helpers.WrapperPort` individually. + +:::{warning} +{class}`~topwrap.amaranth_helpers.WrapperPort` is scheduled to be replaced in favor of plain Amaranth's {class}`Signal` so it should not be used in any new functionality. +::: + +```{eval-rst} +.. autoclass:: topwrap.amaranth_helpers.WrapperPort + :members: + + .. automethod:: __init__ +``` diff --git a/_sources/fusesoc.md.txt b/_sources/fusesoc.md.txt new file mode 100644 index 00000000..023c4f20 --- /dev/null +++ b/_sources/fusesoc.md.txt @@ -0,0 +1,16 @@ +# FuseSoC + +Topwrap uses FuseSoC to automate project generation and build process. +When `topwrap build` is invoked it generates a FuseSoC core file along with the top-level wrapper. + +A template for the core file is bundled with Topwrap (`templates/core.yaml.j2`). +You may need to edit the file to change the backend tool, set additional `Hooks` and change the FPGA part name or other parameters. +By default, {class}`topwrap.fuse_helper.FuseSocBuilder` searches for the template file in the directory you work in, so you should first copy the template into the project's location. + +After generating the core file you can run FuseSoC to generate bitstream and program FPGA: + +```bash +fusesoc --cores-root build run project_1 +``` + +This requires having the suitable backend tool in your `PATH` (Vivado, for example). diff --git a/_sources/getting_started.md.txt b/_sources/getting_started.md.txt new file mode 100644 index 00000000..3fd590e5 --- /dev/null +++ b/_sources/getting_started.md.txt @@ -0,0 +1,223 @@ +(getting-started)= + +# Getting started + +## Installation + +1. Install required system packages: + + Debian: + ```bash + apt install -y git g++ make python3 python3-pip antlr4 libantlr4-runtime-dev yosys npm + ``` + + Arch: + ```bash + pacman -Syu git gcc make python3 python-pip antlr4 antlr4-runtime yosys npm + ``` + + Fedora: + ```bash + dnf install git g++ make python3 python3-pip python3-devel antlr4 antlr4-cpp-runtime-devel yosys npm + ``` + +2. Install the Topwrap package (It is highly recommended to run this step in a Python virtual environment, e.g. [venv](https://docs.python.org/3/library/venv.html)): + + ```bash + pip install . + ``` + +:::{note} +To use `topwrap parse` command you also need to install optional dependencies: +```bash +pip install ".[topwrap-parse]" +``` +On Arch-based distributions a symlink to antlr4 runtime library needs to created and an environment variable set: +```bash +ln -s /usr/share/java/antlr-complete.jar antlr4-complete.jar +ANTLR_COMPLETE_PATH=`pwd` pip install ".[topwrap-parse]" +``` +On Fedora-based distributions symlinks need to be made inside `/usr/share/java` directory itself: +```bash +sudo ln -s /usr/share/java/stringtemplate4/ST4.jar /usr/share/java/stringtemplate4.jar +sudo ln -s /usr/share/java/antlr4/antlr4.jar /usr/share/java/antlr4.jar +sudo ln -s /usr/share/java/antlr4/antlr4-runtime.jar /usr/share/java/antlr4-runtime.jar +sudo ln -s /usr/share/java/treelayout/org.abego.treelayout.core.jar /usr/share/java/treelayout.jar +pip install ".[topwrap-parse]" +``` +::: + +(example-usage)= + +## Example usage + +This section demonstrates the basic usage of Topwrap to generate IP wrappers and a top module. + +1. Create {ref}`IP core description ` file for every IP Core you want to use or let {ref}`topwrap parse ` handle this for you. This file describes the ports, parameters and interfaces of an IP core. + +As an example, Verilog module such as: + +```verilog +module ibuf ( + input wire clk, + input wire rst, + input wire a, + output reg z +); + // ... +endmodule +``` + +Needs this corresponding description: + +```yaml +signals: + in: + - clk + - rst + - a + out: + - z +``` + +2. Create a {ref}`design description ` file where you can specify all instances of IP cores and connections between them (`project.yaml` in this example) + +- Create instances of IP cores: + +```yaml +ips: + vexriscv_instance: + file: ipcores/gen_VexRiscv.yaml + module: VexRiscv + wb_ram_data_instance: + file: ipcores/gen_mem.yaml + module: mem + wb_ram_instr_instance: + file: ipcores/gen_mem.yaml + module: mem + +``` + +`file` and `module` are mandatory fields providing the IP description file and the name of the HDL module as it appears in the source. + +- (Optional) Set parameters for IP core instances: + +```yaml +parameters: + wb_ram_data_instance: + depth: 0x1000 + memfile: "top_sram.init" + wb_ram_instr_instance: + depth: 0xA000 + memfile: "bios.init" +``` + +- Connect desired ports of the IP cores: + +```yaml +ports: + wb_ram_data_instance: + clk: [some_other_ip, clk_out] + rst: [reset_core, reset0] + wb_ram_instr_instance: + clk: [some_other_ip, clk_out] + rst: [reset_core, reset0] + vexriscv_instance: + softwareInterrupt: [some_other_ip, sw_interrupt] + ... +``` + +Connections only need to be written once, i.e. if A connects to B, then only a connection A: B has to be specified (B: A is redundant). + +- Connect desired interfaces of the IP cores: + +```yaml +interfaces: + vexriscv_instance: + iBusWishbone: [wb_ram_instr_instance, mem_bus] + dBusWishbone: [wb_ram_data_instance, mem_bus] +``` + +- Specify external ports or interfaces of the top module and connect them with chosen IP cores' ports or interfaces: + +```yaml +ports: + vexriscv_instance: + timerInterrupt: ext_timer_interrupt + +... + +external: + ports: + out: + - ext_timer_interrupt + interfaces: + ... +``` + +3. Create a Core file template for FuseSoC, or use a default one bundled with Topwrap. + +You may want to modify the file to add dependencies, source files, or change the target board. +The file should be named `core.yaml.j2`. You can find an example template in `examples/hdmi` directory of the project. +If you don't create any template a default template bundled with Topwrap will be used (stored in `templates` directory). + +4. Place any additional source files in a directory (`sources` in this example). + +5. Run Topwrap: + + ``` + python -m topwrap build --design project.yaml --sources sources + ``` + +### Example PWM design + +There's an example setup in `examples/pwm`. + +In order to generate the top module, run: + +``` +make generate +``` + +In order to generate bitstream, add Vivado to your path and run: + +``` +make +``` + +The FPGA design utilizes an AXI-mapped PWM IP Core. +You can access its registers starting from address `0x4000000` (that's the base address of `AXI_GP0` on ZYNQ). +Each IP Core used in the project is declared in `ips` section in `project.yml` file. +`ports` section allows to connect individual ports of IP Cores, and `interfaces` is used analogously for connecting whole interfaces. +Finally, you can specify which ports will be used as external I/O in `external` section. + +To connect the I/O signals to specific FPGA pins, you need proper mappings in a constraints file. See `zynq.xdc` used in the setup and modify it accordingly. + +```{image} img/pwm.png +``` + +### Example HDMI design + +There's an example setup stored in `examples/hdmi`. + +You can generate bitstream for desired target: + +> - Snickerdoodle Black: +> +> ``` +> make snickerdoodle +> ``` +> +> - Zynq Video Board: +> +> ``` +> make zvb +> ``` + +If you wish to generate HDL sources without running Vivado, you can use: + +``` +make generate +``` + +You can find more information in README of the example setup. diff --git a/_sources/hierarchies.md.txt b/_sources/hierarchies.md.txt new file mode 100644 index 00000000..980cef99 --- /dev/null +++ b/_sources/hierarchies.md.txt @@ -0,0 +1,44 @@ +# Hierarchies + +Hierarchies allow for creating designs with subgraphs in them. +Subgraphs can contain multiple IP-cores and other subgraphs. +This allows creating nested designs in topwrap. + +## Format + +All information about hierarchies is specified in [design description](description_files.md). +`hierarchies` key must be a direct descendant of the `design` key. +Format is as follows: + +```yaml +hierarchies: + {hierarchy_name_1}: + ips: # ips that are used on this hierarchy level + {ip_name}: + ... + + design: + parameters: + ... + ports: # ports connections internal to this hierarchy + # note that also you have to connect port to it's external port equivalent (if exists) + {ip1_name}: + {port1_name} : [{ip2_name}, {port2_name}] + {port2_name} : {port2_external_equivalent} # connection to external port equivalent. Note that it has to be to the parent port + ... + hierarchies: + {nested_hierarchy_name}: + # structure here will be the same as for {hierarchy_name_1} + ... + external: + # external ports and/or interfaces of this hierarchy; these can be + # referenced in the upper-level `ports`, `interfaces` or `external` section + ports: + in: + - {port2_external_equivalent} + ... + {hierarchy_name_2}: + ... +``` + +More complex hierarchy example can be found in [examples/hierarchy](https://github.com/antmicro/topwrap/tree/main/examples/hierarchy). diff --git a/_sources/index.md.txt b/_sources/index.md.txt new file mode 100644 index 00000000..34144f88 --- /dev/null +++ b/_sources/index.md.txt @@ -0,0 +1,34 @@ +# Welcome to Topwrap! + +```{toctree} +:caption: Documentation +:maxdepth: 2 +introduction +getting_started +description_files +interconnect_gen +cli +user_repositories +hierarchies +pipeline_manager +fusesoc +``` + +```{toctree} +:caption: Developer's Guide +:maxdepth: 2 +developers_guide/setup +developers_guide/style +developers_guide/tests +developers_guide/wrapper +developers_guide/ipwrapper +developers_guide/ipconnect +developers_guide/elaboratable_wrapper +developers_guide/wrapper_port +developers_guide/fusesocbuilder +developers_guide/interface +developers_guide/config +developers_guide/parsing +developers_guide/examples +developers_guide/future_enhancements +``` diff --git a/_sources/interconnect_gen.md.txt b/_sources/interconnect_gen.md.txt new file mode 100644 index 00000000..a26be4a4 --- /dev/null +++ b/_sources/interconnect_gen.md.txt @@ -0,0 +1,68 @@ +(interconnect-generation)= +# Interconnect generation + +Generating interconnects is an experimental feature of topwrap. +With a specification of which interfaces are masters or slaves and their address ranges, topwrap is able to automatically generate an interconnect conforming to this description. Currently supported interconnect types are: +- Wishbone round-robin + +## Format + +The format for describing interconnects is specified below. `interconnects` key must be a direct descendant of the `design` key in the design description. + +```yaml +interconnects: + {interconnect1_name}: + # specify clock and reset to drive the interconnect with + clock: [{ip_name, clk_port_name}] + reset: [{ip_name, rst_port_name}] + # alternatively you can specify a connection to an external interface: + # clock: ext_clk_port_name + # reset: ext_rst_port_name + + # specify interconnect type + type: {interconnect_type} + + # specify interconnect parameters - interconnect-type-dependent (see "Interconnect params" section): + params: + {param_name1}: param_value1 + ... + + # specify masters and their interfaces connected to the bus + masters: + {master1_name}: + - {master1_iface1_name} + ... + ... + + # specify slaves, their interfaces connected to the bus and their bus parameters + slaves: + {slave1_name}: + {slave1_interface1_name}: + # requests in address range [address, address+size) will be routed to this interface + address: {start_address} + size: {range_size} + ... + ... +``` + +## Interconnect params + +Different interconnect types may provide different configuration options. +This section lists parameter names for available interconnects for use in the `params` section of interconnect specification. + +### Wishbone round-robin + +Corresponds to `type: wishbone_roundrobin` + +- `addr_width` - bit width of the address line (addresses access `data_width`-sized chunks) +- `data_width` - bit width of the data line +- `granularity` - access granularity - smallest unit of data transfer that the interconnect is capable of transferring. Must be one of: 8, 16, 32, 64 +- `features` - optional, list of optional wishbone signals, can contain: `err`, `rty`, `stall`, `lock`, `cti`, `bte` + +## Limitations + +Known limitations currently are: +- only word-sized addressing is supported (in other words - consecutive addresses access word-sized chunks of data) +- crossing clock domains is not supported +- down-converting (initiating multiple transactions on a narrow bus per one transaction on a wider bus) is not supported +- up-converting is not supported diff --git a/_sources/introduction.md.txt b/_sources/introduction.md.txt new file mode 100644 index 00000000..8439715c --- /dev/null +++ b/_sources/introduction.md.txt @@ -0,0 +1,13 @@ +# Introduction + +ASIC and FPGA designs consist of distinct blocks of logic bound together by a top-level design. +To take advantage of this modularity and enable reuse of blocks across designs and so facilitate the shift towards automation in logic design, it is necessary to derive a generic way to aggregate the blocks in various configurations and make the top-level design easy to parse and process automatically. + +Topwrap is an open source command line toolkit for connecting individual HDL modules into full designs of varying complexity. +The toolkit is designed to take advantage of the ever-growing availability of open source digital logic designs and offers a user-friendly graphical interface which lets you mix-and-match GUI-driven design with CLI-based adjustments and present designs in a diagram form thanks to the integration with Antmicro’s [Pipeline Manager](https://github.com/antmicro/kenning-pipeline-manager). + +Topwrap's most notable features are: +* Parsing HDL design files with automatic recognition of common interfaces +* Simple YAML-based description for command-line use +* Capability to create a custom libraries for reuse across projects +* User-friendly GUI powered by [Kenning Pipeline Manager](https://github.com/antmicro/kenning-pipeline-manager). diff --git a/_sources/pipeline_manager.md.txt b/_sources/pipeline_manager.md.txt new file mode 100644 index 00000000..156ee7c7 --- /dev/null +++ b/_sources/pipeline_manager.md.txt @@ -0,0 +1,98 @@ +(kenning-pipeline-manager)= + +# Kenning Pipeline Manager + +Topwrap can make use of [Kenning Pipeline Manager](https://github.com/antmicro/kenning-pipeline-manager) to visualize the process of creating block design. + +## Run Topwrap with Pipeline Manager + +1. Build and run Pipeline Manager server + + In order to start creating block design in Pipeline Manager, you need to first build and run a server application - here is a brief instruction on how to achieve this (the process of building and installation of Pipeline Manager is described in detail in its [documentation](https://antmicro.github.io/kenning-pipeline-manager/project-readme.html#building-and-running)): + + ``` + python -m topwrap kpm_build_server + python -m topwrap kpm_run_server + ``` + + After executing the above-mentioned commands, the Pipeline Manager server is waiting for an external application (i.e. Topwrap) to connect on `127.0.0.1:9000` and you can connect to the web GUI frontend in your browser on `http://127.0.0.1:5000`. + +2. Establish connection with Topwrap + + Once the Pipeline Manager server is running, you can now launch Topwrap's client application in order to connect to the server. You need to specify: + * IP address (`127.0.0.1` is default) + * listening port (`9000` is default) + * yamls describing IP cores, that will be used in the block design + * design to load initially (`None` by default) + + An example command, that runs Topwrap's client, may look like this: + ``` + python -m topwrap kpm_client -h 127.0.0.1 -p 9000 \ + topwrap/ips/axi/axi_axil_adapter.yaml \ + examples/pwm/ipcores/{litex_pwm.yml,ps7.yaml} -d examples/pwm/project.yml + ``` + +3. Create block design in Pipeline Manager + + Upon successful connection to a Pipeline Manager server, Topwrap will generate and send to the server a specification describing the structure of previously selected IP cores. After that, you are free to create a custom block design by means of: + * adding IP core instances to the block design. Each Pipeline Manager's node has `delete` and `rename` options, which make it possible to remove the selected node and change its name respectively. This means that you can create multiple instances of the same IP core. + * adjusting IP cores' parameters values. Each node may have input boxes in which you can enter parameters' values (default parameter values are added while adding an IP core to the block design): + ```{image} img/node_parameters.png + ``` + * connecting IP cores' ports and interfaces. Only connections between ports or interfaces of matching types are allowed. This is automatically checked by Pipeline Manager, as the types of nodes' ports and interfaces are contained in the loaded specification, so Pipeline Manager will prevent you from connecting non-matching interfaces (e.g. *AXI4* with *AXI4Lite* or a port with an interface). A green line will be displayed if a connection is possible to create, or a red line elsewhere: + ```{image} img/invalid_connection.png + ``` + * specifying external ports or interfaces in the top module. This can be done by adding `External Input`, `External Output` or `External Inout` metanodes and creating connections between them and chosen ports or interfaces. Note that you should adjust the name of the external port or interface in a textbox inside selected metanode. In the example below, output port `pwm` of `litex_pwm_top` IP core will be made external in the generated top module and the external port name will be set to `ext_pwm`: + ```{image} img/external_port.png + ``` + Note, that you don't always have to create a new block design by hand - you can use a {ref}`design import ` feature to load an existing block design from a description in Topwrap's yaml format. + + An example block design in Pipeline Manager for the PWM project may look like this: + + ```{image} img/pwm_design.png + ``` + +## Pipeline Manager features + +While creating a custom block design, you can make use of the following Pipeline Manager's features: +* export (save) design to a file +* import (load) design from a file +* validate design +* build design + +(export-design)= + +### Export design to yaml description file + +Created block design can be saved to a {ref}`design description file ` in yaml format, using Pipeline Manager's `Save file` option. +Target location on the filesystem can then be browsed in a filesystem dialog window. + +(import-design)= + +### Import design from yaml description file + +Topwrap also supports conversion in the opposite way - block design in Pipeline Manager can be generated from a yaml design description file using `Load file` feature. + +(validate-design)= + +### Design validation + +Pipeline Manager is capable of performing some basic checks at runtime such as interface type checking while creating a connection. However you can also run more complex tests by using Pipeline Manager's `Validate` option. Topwrap will then respond with a validity confirmation or error messages. The rules you need to follow in order to keep your block design valid are: +* multiple IP cores with the same name are not allowed (except from external metanodes). +* parameters values can be integers of different bases (e.g. `0x28`, `40` or `0b101000`) or arithmetic expressions, that are later evaluated using [numexpr.evaluate()](https://numexpr.readthedocs.io/en/latest/api.html#numexpr.evaluate) function (e.g. `(AXI_DATA_WIDTH+1)/4` is a valid parameter value assuming that a parameter named `AXI_DATA_WIDTH` exists in the same IP core). You can also write a parameter value in a Verilog format (e.g. `8'b00011111` or `8'h1F`) - in such case it will be interpreted as a fixed-width bit vector. +* a single port or interface cannot be external and connected to another IP core at the same time. +* connections between two external metanodes are not allowed. +* all the created external output or inout ports must have unique names. Only multiple input ports of IP cores can be driven be the same external signal. + +Topwrap can also generate warnings if: +* some ports or interfaces remain unconnected. +* multiple ports are connected to an `External Input` metanode with an empty `External Name` property. +* `inout` ports of two modules are connected together (all `inout` ports are required to be directly connected to `External Inout` metanodes) + +If a block design validation returns a warning, it means that the block design can be successfully built, but it is recommended to follow the suggestion and resolve a particular issue. + +(build-design)= + +### Building design + +Once the design has been created and tested for validity, you can build design using `Run` button. If the design does not contain any errors, this will result in creating a top module in a directory where `topwrap kpm_client` was ran, similarly when using Topwrap's `topwrap build` command. diff --git a/_sources/user_repositories.md.txt b/_sources/user_repositories.md.txt new file mode 100644 index 00000000..f6a289a6 --- /dev/null +++ b/_sources/user_repositories.md.txt @@ -0,0 +1,45 @@ +# User repositories +Repositories allow for easy loading packages with IP-cores. + +You can add repositories to be loaded each time topwrap is ran by specifying them in configuration file. + +It has to be located in one of the following locations: +``` +topwrap.yaml +~/.config/topwrap/topwrap.yaml +~/.config/topwrap/config.yaml +``` + +Example contents of user config: +``` +force_interface_compliance: true +repositories: + - name: name of repo + path: ~/path_to_repo/repo +``` + +Topwrap provides internal API for constructing repositories in python code which can be [found here](https://github.com/antmicro/topwrap/blob/main/topwrap/repo/user_repo.py#L144) + +Structure of repository has to be as follows: +``` +path_to_repository/ +|───cores +| |───someCore1 +| | |───srcs +| | | | file1.v +| | | design.yaml +| | +| |───someCore1 +| |───srcs +| | | file1.v +| | design.yaml +| +|───interfaces(Optional) +| interface1.yaml +| interface2.yaml +``` +Repository has two main catalogs: `cores` and `interfaces`. Inside `cores` each core has it's own catalog with it's design file and `srcs` where are stored verilog/VHDL files. + +There is optional interfaces catalog where can be stored interfaces for cores. + +Example User Repo can be found in [examples/user_repository](https://github.com/antmicro/topwrap/tree/main/examples/user_repository). diff --git a/_static/fonts/0053ba6958e79f26751eabb555bd73d0.woff2 b/_static/fonts/0053ba6958e79f26751eabb555bd73d0.woff2 new file mode 100644 index 00000000..ab301009 Binary files /dev/null and b/_static/fonts/0053ba6958e79f26751eabb555bd73d0.woff2 differ diff --git a/_static/fonts/029e176ad602329b4434892101db9cf3.woff2 b/_static/fonts/029e176ad602329b4434892101db9cf3.woff2 new file mode 100644 index 00000000..09e03c95 Binary files /dev/null and b/_static/fonts/029e176ad602329b4434892101db9cf3.woff2 differ diff --git a/_static/fonts/07ff82964967feebb9c96288e0e0df05.woff2 b/_static/fonts/07ff82964967feebb9c96288e0e0df05.woff2 new file mode 100644 index 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b/_static/language_data.js @@ -0,0 +1,199 @@ +/* + * language_data.js + * ~~~~~~~~~~~~~~~~ + * + * This script contains the language-specific data used by searchtools.js, + * namely the list of stopwords, stemmer, scorer and splitter. + * + * :copyright: Copyright 2007-2024 by the Sphinx team, see AUTHORS. + * :license: BSD, see LICENSE for details. + * + */ + +var stopwords = ["a", "and", "are", "as", "at", "be", "but", "by", "for", "if", "in", "into", "is", "it", "near", "no", "not", "of", "on", "or", "such", "that", "the", "their", "then", "there", "these", "they", "this", "to", "was", "will", "with"]; + + +/* Non-minified version is copied as a separate JS file, if available */ + +/** + * Porter Stemmer + */ +var Stemmer = function() { + + var step2list = { + ational: 'ate', + tional: 'tion', + enci: 'ence', + anci: 'ance', + izer: 'ize', + bli: 'ble', + alli: 'al', + entli: 'ent', + eli: 'e', + ousli: 'ous', + ization: 'ize', + ation: 'ate', + ator: 'ate', + alism: 'al', + iveness: 'ive', + fulness: 'ful', + ousness: 'ous', + aliti: 'al', + iviti: 'ive', + biliti: 'ble', + logi: 'log' + }; + + var step3list = { + icate: 'ic', + ative: '', + alize: 'al', + iciti: 'ic', + ical: 'ic', + ful: '', + ness: '' + }; + + var c = "[^aeiou]"; // consonant + var v = "[aeiouy]"; // vowel + var C = c + "[^aeiouy]*"; // consonant sequence + var V = v + "[aeiou]*"; // vowel sequence + + var mgr0 = "^(" + C + ")?" + V + C; // [C]VC... is m>0 + var meq1 = "^(" + C + ")?" + V + C + "(" + V + ")?$"; // [C]VC[V] is m=1 + var mgr1 = "^(" + C + ")?" + V + C + V + C; // [C]VCVC... is m>1 + var s_v = "^(" + C + ")?" + v; // vowel in stem + + this.stemWord = function (w) { + var stem; + var suffix; + var firstch; + var origword = w; + + if (w.length < 3) + return w; + + var re; + var re2; + var re3; + var re4; + + firstch = w.substr(0,1); + if (firstch == "y") + w = firstch.toUpperCase() + w.substr(1); + + // Step 1a + re = /^(.+?)(ss|i)es$/; + re2 = /^(.+?)([^s])s$/; + + if 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/^(.+?)(ational|tional|enci|anci|izer|bli|alli|entli|eli|ousli|ization|ation|ator|alism|iveness|fulness|ousness|aliti|iviti|biliti|logi)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step2list[suffix]; + } + + // Step 3 + re = /^(.+?)(icate|ative|alize|iciti|ical|ful|ness)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step3list[suffix]; + } + + // Step 4 + re = /^(.+?)(al|ance|ence|er|ic|able|ible|ant|ement|ment|ent|ou|ism|ate|iti|ous|ive|ize)$/; + re2 = /^(.+?)(s|t)(ion)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + if (re.test(stem)) + w = stem; + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1] + fp[2]; + re2 = new RegExp(mgr1); + if (re2.test(stem)) + w = stem; + } + + // Step 5 + re = /^(.+?)e$/; + if (re.test(w)) { + var fp = re.exec(w); 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f=Tt(o);r.hidden=c.x<16,n.hidden=c.x>f.width-s.width-16}),P(x(r,"click").pipe(d(()=>-1)),x(n,"click").pipe(d(()=>1))).pipe(te(a)).subscribe(c=>{let{width:s}=Se(o);o.scrollBy({left:s*c,behavior:"smooth"})}),Z("content.tabs.link")&&i.pipe(Pe(1),me(t)).subscribe(([{active:c},{offset:s}])=>{let f=c.innerText.trim();if(c.hasAttribute("data-md-switching"))c.removeAttribute("data-md-switching");else{let u=e.offsetTop-s.y;for(let p of D("[data-tabs]"))for(let m of D(":scope > input",p)){let h=B(`label[for="${m.id}"]`);if(h!==c&&h.innerText.trim()===f){h.setAttribute("data-md-switching",""),m.click();break}}window.scrollTo({top:e.offsetTop-u});let l=__md_get("__tabs")||[];__md_set("__tabs",[...new Set([f,...l])])}}),ws(e).pipe(M(c=>i.next(c)),R(()=>i.complete()),d(c=>V({ref:e},c)))}).pipe(Ze(se))}function gi(e,{viewport$:t,target$:r,print$:n}){return P(...D("pre:not(.mermaid) > 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I(()=>G([de(e),Ss(t)])).pipe(d(([{height:r},n])=>({height:r,hidden:n})),Q((r,n)=>r.height===n.height&&r.hidden===n.hidden),X(1))}function wi(e,{header$:t,main$:r}){return I(()=>{let n=new L,o=n.pipe(ue(1));return n.pipe(J("active"),St(t)).subscribe(([{active:i},{hidden:a}])=>{e.classList.toggle("md-header--shadow",i&&!a),e.hidden=a}),r.subscribe(n),t.pipe(te(o),d(i=>V({ref:e},i)))})}function Os(e,{viewport$:t,header$:r}){return mr(e,{viewport$:t,header$:r}).pipe(d(({offset:{y:n}})=>{let{height:o}=Se(e);return{active:n>=o}}),J("active"))}function Ei(e,t){return I(()=>{let r=new L;r.subscribe(({active:o})=>{e.classList.toggle("md-header__title--active",o)});let n=ie("article h1, .objdesc > dt .descname");return typeof n=="undefined"?k:Os(n,t).pipe(M(o=>r.next(o)),R(()=>r.complete()),d(o=>V({ref:e},o)))})}function Si(e,{viewport$:t,header$:r}){let n=r.pipe(d(({height:i})=>i),Q()),o=n.pipe(_(()=>de(e).pipe(d(({height:i})=>({top:e.offsetTop,bottom:e.offsetTop+i})),J("bottom"))));return G([n,o,t]).pipe(d(([i,{top:a,bottom:c},{offset:{y:s},size:{height:f}}])=>(f=Math.max(0,f-Math.max(0,a-s,i)-Math.max(0,f+s-c)),{offset:a-i,height:f,active:a-i<=s})),Q((i,a)=>i.offset===a.offset&&i.height===a.height&&i.active===a.active))}function _s(e){let t=__md_get("__palette")||{index:e.findIndex(r=>matchMedia(r.getAttribute("data-md-color-media")).matches)};return C(...e).pipe(oe(r=>x(r,"change").pipe(d(()=>r))),z(e[Math.max(0,t.index)]),d(r=>({index:e.indexOf(r),color:{scheme:r.getAttribute("data-md-color-scheme"),primary:r.getAttribute("data-md-color-primary"),accent:r.getAttribute("data-md-color-accent")}})),X(1))}function Oi(e){return I(()=>{let t=new L;t.subscribe(n=>{document.body.setAttribute("data-md-color-switching","");for(let[o,i]of Object.entries(n.color))document.body.setAttribute(`data-md-color-${o}`,i);for(let o=0;o{document.body.removeAttribute("data-md-color-switching")});let r=D("input",e);return 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Us(e,{query$:t}){return t.pipe(d(({value:r})=>{let n=Oe();return n.hash="",n.searchParams.delete("h"),n.searchParams.set("q",r),{url:n}}))}function Ci(e,t){let r=new L;return r.subscribe(({url:n})=>{e.setAttribute("data-clipboard-text",e.href),e.href=`${n}`}),x(e,"click").subscribe(n=>n.preventDefault()),Us(e,t).pipe(M(n=>r.next(n)),R(()=>r.complete()),d(n=>V({ref:e},n)))}function Ri(e,{keyboard$:t}){let r=_e("search-query");return t.pipe(A(({mode:n})=>n==="search")).subscribe(n=>{switch(n.type){case"ArrowRight":e.innerText.length&&r.selectionStart===r.value.length&&(r.value=e.innerText);break}}),C()}function Hi(e,{keyboard$:t}){try{let r=_e("search-query",e),n=_e("search-result",e);t.pipe(A(({mode:a})=>a==="search")).subscribe(a=>{let c=Fe();switch(a.type){case"Enter":if(c===r){let s=new Map;for(let f of D(":first-child [href]",n)){let u=f.firstElementChild;s.set(f,parseFloat(u.getAttribute("data-md-score")))}if(s.size){let[[f]]=[...s].sort(([,u],[,l])=>l-u);f.click()}a.claim()}break;case"Escape":case"Tab":Ye("search",!1),r.blur();break;case"ArrowUp":case"ArrowDown":if(typeof c=="undefined")r.focus();else{let s=[r,...D(":not(details) > [href], summary, details[open] [href]",n)],f=Math.max(0,(Math.max(0,s.indexOf(c))+s.length+(a.type==="ArrowUp"?-1:1))%s.length);s[f].focus()}a.claim();break;default:r!==Fe()&&r.focus()}}),t.pipe(A(({mode:a})=>a==="global")).subscribe(a=>{switch(a.type){case"f":case"s":case"/":r.focus(),r.select(),a.claim();break}});let o=_i(r),i=Ai(n,{query$:o});return P(o,i).pipe(tt(...ee("search-share",e).map(a=>Ci(a,{query$:o})),...ee("search-suggest",e).map(a=>Ri(a,{keyboard$:t}))))}catch(r){return e.hidden=!0,je}}var cn=Je(Qr());function Vs(e){e.setAttribute("data-md-copying","");let t=e.innerText;return e.removeAttribute("data-md-copying"),t}function ki({alert$:e}){cn.default.isSupported()&&new U(t=>{new cn.default("[data-clipboard-target], [data-clipboard-text]",{text:r=>r.getAttribute("data-clipboard-text")||Vs(B(r.getAttribute("data-clipboard-target")))}).on("success",r=>t.next(r))}).pipe(M(t=>{t.trigger.focus()}),d(()=>ae("clipboard.copied"))).subscribe(e)}function Ns(e){if(e.length<2)return[""];let[t,r]=[...e].sort((o,i)=>o.length-i.length).map(o=>o.replace(/[^/]+$/,"")),n=0;if(t===r)n=t.length;else for(;t.charCodeAt(n)===r.charCodeAt(n);)n++;return e.map(o=>o.replace(t.slice(0,n),""))}function hr(e){let t=__md_get("__sitemap",sessionStorage,e);if(t)return C(t);{let r=ce();return zo(new URL("sitemap.xml",e||r.base)).pipe(d(n=>Ns(D("loc",n).map(o=>o.textContent))),le(()=>k),De([]),M(n=>__md_set("__sitemap",n,sessionStorage,e)))}}function Pi({document$:e,location$:t,viewport$:r}){let n=ce();if(location.protocol==="file:")return;"scrollRestoration"in history&&(history.scrollRestoration="manual",x(window,"beforeunload").subscribe(()=>{history.scrollRestoration="auto"}));let o=ie("link[rel=icon]");typeof o!="undefined"&&(o.href=o.href);let i=hr().pipe(d(l=>l.map(p=>`${new URL(p,n.base)}`)),_(l=>x(document.body,"click").pipe(A(p=>!p.metaKey&&!p.ctrlKey),_(p=>{if(p.target instanceof Element){let m=p.target.closest("a");if(m&&!m.target){let h=new URL(m.href);if(h.search="",h.hash="",h.pathname!==location.pathname&&l.includes(h.toString()))return p.preventDefault(),C({url:new URL(m.href)})}}return je}))),pe()),a=x(window,"popstate").pipe(A(l=>l.state!==null),d(l=>({url:new URL(location.href),offset:l.state})),pe());P(i,a).pipe(Q((l,p)=>l.url.href===p.url.href),d(({url:l})=>l)).subscribe(t);let c=t.pipe(J("pathname"),_(l=>pr(l.href).pipe(le(()=>(lr(l),je)))),pe());i.pipe(rr(c)).subscribe(({url:l})=>{history.pushState({},"",`${l}`)});let s=new DOMParser;c.pipe(_(l=>l.text()),d(l=>s.parseFromString(l,"text/html"))).subscribe(e);let f=new Set,u=new Set;for(let l of D("script",document))l.src?f.add(new URL(l.src,document.baseURI).toString()):u.add(l.outerHTML);e.pipe(Pe(1),mt(l=>ze(this,null,function*(){var p;for(let m of["title","link[rel=canonical]","meta[name=author]","meta[name=description]","[data-md-component=announce]","[data-md-component=container]","[data-md-component=header-topic]","[data-md-component=outdated]","[data-md-component=logo]","[data-md-component=skip]",...Z("navigation.tabs.sticky")?["[data-md-component=tabs]"]:[]]){let h=ie(m),b=ie(m,l);typeof h!="undefined"&&typeof b!="undefined"&&h.replaceWith(b)}((p=window.MathJax)==null?void 0:p.typesetPromise)!==void 0&&(yield window.MathJax.typesetPromise());for(let m of D("script",l))if(m.src){let h=new URL(m.src,document.baseURI).toString();if(!f.has(h)){let b=document.createElement("script");for(let q of m.getAttributeNames())b.setAttribute(q,m.getAttribute(q));let w;b.src=h,b.async||(w=new Promise(q=>b.addEventListener("load",()=>q()))),document.body.appendChild(b),f.add(h),w!==void 0&&(yield w)}}else{let h=m.outerHTML;if(!u.has(h)){let b=document.createElement("script");for(let w of m.getAttributeNames())b.setAttribute(w,m.getAttribute(w));b.textContent=m.textContent,document.body.appendChild(b),u.add(h)}}}))).subscribe(),e.pipe(Pe(1),d(()=>_e("container")),_(l=>D("script",l)),mt(l=>{let p=O("script");if(l.src){for(let m of l.getAttributeNames())p.setAttribute(m,l.getAttribute(m));return l.replaceWith(p),new U(m=>{p.onload=()=>m.complete()})}else return p.textContent=l.textContent,l.replaceWith(p),k})).subscribe(),P(i,a).pipe(rr(e)).subscribe(({url:l,offset:p})=>{l.hash&&!p?No(l.hash):window.scrollTo(0,(p==null?void 0:p.y)||0)}),r.pipe(Wr(i),He(250),J("offset")).subscribe(({offset:l})=>{history.replaceState(l,"")}),P(i,a).pipe(Ne(2,1),A(([l,p])=>l.url.pathname===p.url.pathname),d(([,l])=>l)).subscribe(({offset:l})=>{window.scrollTo(0,(l==null?void 0:l.y)||0)})}var $i=Je(rn());function Ii(e,t){let r=new RegExp(e.separator,"img"),n=(o,i,a)=>`${i}${a}`;return o=>{o=o.replace(/[\s*+\-:~^]+/g," ").trim();let i=new RegExp(`(^|${e.separator})(${o.replace(/[|\\{}()[\]^$+*?.-]/g,"\\$&").replace(r,"|")})`,"img");return a=>(t?(0,$i.default)(a):a).replace(i,n).replace(/<\/mark>(\s+)]*>/img,"$1")}}function ji({document$:e}){var a;let t=ce(),r=t.version.staticVersions?C(t.version.staticVersions):Ge(new URL((a=t.version.versionPath)!=null?a:"../versions.json",t.base)),n=new URL("..",t.base),o=c=>new URL(c,n).toString().replace(/\/*$/,""),i=r.pipe(d(c=>{let s=t.base.toString().replace(/\/*$/,"");return c.find(({version:f,aliases:u})=>o(f)===s||u.find(l=>o(l)===s))||c[0]}));r.pipe(d(c=>new Map(c.map(s=>[`${new URL(`../${s.version}/`,t.base)}`,s]))),_(c=>x(document.body,"click").pipe(A(s=>!s.metaKey&&!s.ctrlKey),me(i),_(([s,f])=>{if(s.target instanceof Element){let u=s.target.closest("a");if(u&&!u.target&&c.has(u.href)){let l=u.href;return!s.target.closest(".md-version")&&c.get(l)===f?k:(s.preventDefault(),C(l))}}return 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format('woff2');unicode-range: U+0100-02AF, U+0304, U+0308, U+0329, U+1E00-1E9F, U+1EF2-1EFF, U+2020, U+20A0-20AB, U+20AD-20CF, U+2113, U+2C60-2C7F, U+A720-A7FF;}@font-face {font-family: 'Roboto Mono';font-style: italic;font-weight: 700;src: url(fonts/5ce47d5195e59af38114d0b70217baf2.woff2) format('woff2');unicode-range: U+0000-00FF, U+0131, U+0152-0153, U+02BB-02BC, U+02C6, U+02DA, U+02DC, U+0304, U+0308, U+0329, U+2000-206F, U+2074, U+20AC, U+2122, U+2191, U+2193, U+2212, U+2215, U+FEFF, U+FFFD;} +:root{--si-icon--material_alert-circle:url('data:image/svg+xml;charset=utf-8,');--si-icon--material_delete:url('data:image/svg+xml;charset=utf-8,');}.md-typeset .si-icon-inline.material_alert-circle::before{-webkit-mask-image:var(--si-icon--material_alert-circle);mask-image:var(--si-icon--material_alert-circle);}.md-typeset .si-icon-inline.material_delete::before{-webkit-mask-image:var(--si-icon--material_delete);mask-image:var(--si-icon--material_delete);}.md-typeset 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.deprecated>.admonition-title::before{background-color:rgb(203,70,83);-webkit-mask-image:var(--si-icon--material_delete);mask-image:var(--si-icon--material_delete);} diff --git a/_static/white.svg b/_static/white.svg new file mode 100644 index 00000000..d80d1492 --- /dev/null +++ b/_static/white.svg @@ -0,0 +1,54 @@ + + \ No newline at end of file diff --git a/cli.html b/cli.html new file mode 100644 index 00000000..4c7905b1 --- /dev/null +++ b/cli.html @@ -0,0 +1,881 @@ + + + + + + + + + + + + + + + + Command-line Interface - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Command-line Interface

+

Building design

+

To run Topwrap, use:

+
python -m topwrap build --design project.yml
+
+
+

Where project.yml should be your file with description of the top module.

+

You can specify a directory to be scanned for additional sources:

+
python -m topwrap build --sources src --design project.yml
+
+
+

To implement the design for a specific FPGA chip, provide the part name:

+
python -m topwrap build --sources src --design project.yml --part 'xc7z020clg400-3'
+
+
+

Connect Topwrap to Pipeline Manager

+

If you want to use Pipeline Manager as a UI for creating block design, you need to:

+
    +

  1. Build and run Pipeline Manager server application.

    2. +
+
python -m topwrap kpm_build_server
+python -m topwrap kpm_run_server
+
+
+
    +

  1. Run Topwrap’s client application, that will connect to a running Pipeline Manager server app.

    2. +
+
python -m topwrap kpm_client [-h ip_addr] [-p port] [-d FILE] FILES
+
+
+

Topwrap will then try to connect to the server running on ip_addr:port and send a specification generated from FILES, which should be IP core description yamls.

+

If -h or -p options are not specified, ip address 127.0.0.1 and port 9000 will be chosen by default.

+

If -d option is specified, kpm will start with specified design file loaded.

+

Generating IP core description YAMLs

+

You can also use Topwrap to generate ip core description yamls from HDL sources, +that can be later used in your project.yml:

+
python -m topwrap parse HDL_FILES
+
+
+

In HDL source files, ports that belong to the same interface (e.g. wishbone or AXI), +have often a common prefix, which corresponds to the interface name. If such naming +convention is followed in the HDL sources, Topwrap can also divide ports into user-specified +interfaces, or automatically deduce interfaces names when generating yaml file:

+
python -m topwrap parse --iface wishbone --iface s_axi HDL_FILES
+
+python -m topwrap parse --iface-deduce HDL_FILES
+
+
+

To get help, use:

+
python -m topwrap [build|kpm_client|parse] --help
+
+
+ + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
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+ + + + + + + + \ No newline at end of file diff --git a/description_files.html b/description_files.html new file mode 100644 index 00000000..62386a70 --- /dev/null +++ b/description_files.html @@ -0,0 +1,1071 @@ + + + + + + + + + + + + + + + + Description files - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Description files

+

Design Description

+

To create a complete, fully synthesizable design, a proper design file is needed. +It’s used to specify interconnects, IP cores, set their parameters’ values, describe hierarchies for the project, +connect the IPs and hierarchies, and pick external ports (those which will be connected to physical I/O).

+

You can see example design files in examples directory. The structure is as below:

+
ips:
+  # specify relations between IPs names in the design yaml
+  # and IP cores description yamls and modules
+  {ip_instance_name}:
+    file: {path_to_yaml_file_of_the_ip}
+    module: {name_of_the_HDL_module}
+  ...
+
+design:
+  name: {design_name} # optional name of the toplevel
+  hierarchies:
+      # see "Hierarchies" page for a detailed description of the format
+      ...
+  parameters: # specify IPs parameter values to be overridden
+    {ip_instance_name}:
+      {param_name} : {param_value}
+      ...
+
+  ports:
+    # specify incoming ports connections of an IP named `ip1_name`
+    {ip1_name}:
+      {port1_name} : [{ip2_name}, {port2_name}]
+      ...
+    # specify incoming ports connections of a hierarchy named `hier_name`
+    {hier_name}:
+      {port1_name} : [{ip_name}, {port2_name}]
+      ...
+    # specify external ports connections
+    {ip_instance_name}:
+      {port_name} : ext_port_name
+    ...
+
+  interfaces:
+    # specify incoming interfaces connections of `ip1_name` IP
+    {ip1_name}:
+      {iface1_name} : [{ip2_name}, {iface2_name}]
+      ...
+    # specify incoming interfaces connections of `hier_name` hierarchy
+    {hier_name}:
+      {iface1_name} : [{ip_name}, {iface2_name}]
+      ...
+    # specify external interfaces connections
+    {ip_instance_name}:
+      {iface_name} : ext_iface_name
+    ...
+
+  interconnects:
+    # see "Interconnect generation" page for a detailed description of the format
+    ...
+
+external: # specify names of external ports and interfaces of the top module
+  ports:
+    out:
+      - {ext_port_name}
+    inout:
+      - [{ip_name/hierarchy_name, port_name}]
+  interfaces:
+    in:
+      - {ext_iface_name}
+    # note that `inout:` is invalid in the interfaces section
+
+
+

inout ports are handled differently than in and out ports. When any IP has an inout port or when a hierarchy has an inout port specified in its external.ports.inout section, it must be included in external.ports.inout section of the parent design by specifying the name of the IP/hierarchy and port name that contains it. Name of the external port will be identical to the one in the IP core. In case of duplicate names a suffix $n is added (where n is a natural number) to the name of the second and subsequent duplicate names. inout ports cannot be connected to each other.

+

The design description yaml format allows creating hierarchical designs. In order to create a hierarchy, it suffices to add its name as a key in the design section and describe the hierarchy design “recursively” by using the same keys and values (ports, parameters etc.) as in the top-level design (see above). Hierarchies can be nested recursively, which means that you can create a hierarchy inside another one.

+

Note that IPs and hierarchies names cannot be duplicated on the same hierarchy level. For example, the design section cannot contain two identical keys, but it’s correct to have ip_name key in this section and ip_name in the design section of some hierarchy.

+

IP description files

+

Every IP wrapped by Topwrap needs a description file in YAML format.

+

The ports of an IP should be placed in global signals node, followed by the direction of in, out or inout. +Here’s an example description of ports of Clock Crossing IP:

+
# file: clock_crossing.yaml
+signals:
+    in:
+        - clkA
+        - A
+        - clkB
+    out:
+        - B
+
+
+

The previous example is enough to make use of any IP. However, in order to benefit from connecting whole interfaces at once, ports must belong to a named interface like in this example:

+
#file: axis_width_converter.yaml
+interfaces:
+    s_axis:
+        type: AXIStream
+        mode: slave
+        signals:
+            in:
+                TDATA: [s_axis_tdata, 63, 0]
+                TKEEP: [s_axis_tkeep, 7, 0]
+                TVALID: s_axis_tvalid
+                TLAST: s_axis_tlast
+                TID: [s_axis_tid, 7, 0]
+                TDEST: [s_axis_tdest, 7, 0]
+                TUSER: s_axis_tuser
+            out:
+                TREADY: s_axis_tready
+
+    m_axis:
+        type: AXIStream
+        mode: master
+        signals:
+            in:
+                TREADY: m_axis_tready
+            out:
+                TDATA: [m_axis_tdata, 31, 0]
+                TKEEP: [m_axis_tkeep, 3, 0]
+                TVALID: m_axis_tvalid
+                TLAST: m_axis_tlast
+                TID: [m_axis_tid, 7, 0]
+                TDEST: [m_axis_tdest, 7, 0]
+                TUSER: m_axis_tuser
+signals: # These ports don't belong to any interface
+    in:
+        - clk
+        - rst
+
+
+

Names s_axis and m_axis will be used to group the selected ports. +Each signal in an interface has a name which must match with the signal it’s supposed to be connected to, for example TDATA: port_name will be connected to TDATA: other_port_name.

+

Note that you don’t have to write IP core description yamls by hand. You can use Topwrap’s parse command (see Generating IP core description YAMLs) in order to generate yamls from HDL source files and then adjust the yaml to your needs.

+

Port widths

+

The width of every port defaults to 1. +You can specify the width using this notation:

+
interfaces:
+    s_axis:
+        type: AXIStream
+        mode: slave
+        signals:
+            in:
+                TDATA: [s_axis_tdata, 63, 0] # 64 bits
+                ...
+                TVALID: s_axis_tvalid # defaults to 1 bit
+
+signals:
+    in:
+        - [gpio_io_i, 31, 0] # 32 bits
+
+
+

Parameterization

+

Port widths don’t have to be hardcoded - you can use parameters to describe an IP core in a generic way. +Values specified in IP core yamls can be overridden in a design description file (see Design Description).

+
parameters:
+    DATA_WIDTH: 8
+    KEEP_WIDTH: (DATA_WIDTH+7)/8
+    ID_WIDTH: 8
+    DEST_WIDTH: 8
+    USER_WIDTH: 1
+
+interfaces:
+    s_axis:
+        type: AXI4Stream
+        mode: slave
+        signals:
+            in:
+                TDATA: [s_axis_tdata, DATA_WIDTH-1, 0]
+                TKEEP: [s_axis_tkeep, KEEP_WIDTH-1, 0]
+                ...
+                TID: [s_axis_tid, ID_WIDTH-1, 0]
+                TDEST: [s_axis_tdest, DEST_WIDTH-1, 0]
+                TUSER: [s_axis_tuser, USER_WIDTH-1, 0]
+
+
+

Parameters values can be integers or math expressions, which are evaluated using numexpr.evaluate().

+

Port slicing

+

You can also slice a port, to use some bits of the port as a signal that belongs to an interface. +The example below means:

+

Port m_axi_bid of the IP core is 36 bits wide. Use bits 23..12 as the BID signal of AXI master named m_axi_1

+
m_axi_1:
+    type: AXI
+    mode: master
+    signals:
+        in:
+            BID: [m_axi_bid, 35, 0, 23, 12]
+
+
+

Interface Description files

+

Topwrap can use predefined interfaces described in YAML files that come packaged with the tool. +Currently supported interfaces are AXI4, AXI3, AXI Stream, AXI Lite and Wishbone.

+

You can see an example file below:

+
name: AXI4Stream
+port_prefix: AXIS
+signals:
+    # convention assumes the AXI Stream transmitter (master) perspective
+    required:
+        out:
+            TVALID: tvalid
+            TDATA: tdata
+            TLAST: tlast
+        in:
+            TREADY: tready
+    optional:
+        out:
+            TID: tid
+            TDEST: tdest
+            TKEEP: tkeep
+            TSTRB: tstrb
+            TUSER: tuser
+            TWAKEUP: twakeup
+
+
+

The name of an interface has to be unique. +We also specify a prefix which will be used as a shortened identifier. +Signals are either required or optional. +Their direction is described from the the perspective of master (i.e. directionality of signals in the slave is flipped) - note that clock and reset are not included as these are usually inputs in both master and slave so they’re not supported in interface specification. +These distinctions are used when an option to check if all mandatory signals are present is enabled and when parsing an IP core with topwrap parse (not all required signals must necessarily be present but it’s taken into account). +Every signal is a key-value pair, where the key is a generic signal name (usually from interface specification) and value is a regex that is used to pair the generic name with a concrete signal name in the RTL source when using topwrap parse. +This pairing is performed on signal names that are transformed to lowercase and have a common prefix of an interface they belong to removed. +If a regexp occurs in such transformed signal name anywhere, that name is paired with the generic name. +Since this occurs on names that have all characters in lowercase, regex must be written in lowercase as well.

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+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/config.html b/developers_guide/config.html new file mode 100644 index 00000000..48d6e81b --- /dev/null +++ b/developers_guide/config.html @@ -0,0 +1,895 @@ + + + + + + + + + + + + + + + + Config - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ + + + + + +
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+ + + + +
+
+ + + + + + + + +

Config

+

A Config object stores configuration values. +A global topwrap.config.config object is used throughout the codebase to access topwrap’s configuration. +This is created by ConfigManager that reads config files defined in topwrap.config.ConfigManager.DEFAULT_SEARCH_PATHS, with files most local to the project taking precedence.

+
+
+class Config(force_interface_compliance: bool | None = False, repositories: ~typing.List[~topwrap.config.RepositoryEntry] | None = <factory>)
+

Global topwrap configuration

+
+
+__init__(force_interface_compliance: bool | None = False, repositories: ~typing.List[~topwrap.config.RepositoryEntry] | None = <factory>)
+
+ +
+
+Schema
+

alias of Config

+
+ +
+ +
+
+class ConfigManager(search_paths: List[PathLike] | None = None)
+

Manager used to load topwrap’s configuration from files.

+

The configuration files are loaded in a specific order, which also +determines the priority of settings that are defined differently +in the files. The list of default search paths is defined in +the DEFAULT_SEARCH_PATH class variable. Configuration files that +are specified earlier in the list have higher priority and can +overwrite the settings from the files that follow. The default list of +search paths can be changed by passing a different list to +the ConfigManager constructor.

+
+
+__init__(search_paths: List[PathLike] | None = None)
+
+ +
+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/elaboratable_wrapper.html b/developers_guide/elaboratable_wrapper.html new file mode 100644 index 00000000..f3c01c68 --- /dev/null +++ b/developers_guide/elaboratable_wrapper.html @@ -0,0 +1,914 @@ + + + + + + + + + + + + + + + + ElaboratableWrapper class - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ +
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+
+ + + +
+
+
+ + + + + + +
+
+
+ + + + +
+
+ + + + + + + + +

ElaboratableWrapper class

+

ElaboratableWrapper encapsulates an Amaranth’s Elaboratable and exposes an interface compatible with other wrappers which allows making connections with them. +Supplied elaboratable must contain a signature property and a conforming interface as specified by Amaranth docs. +Ports’ directionality, their names and widths are inferred from it.

+
+
+class ElaboratableWrapper(*args, src_loc_at=0, **kwargs)
+

Allows connecting an Amaranth’s Elaboratable with other +classes derived from Wrapper.

+
+
+__init__(name: str, elaboratable: Elaboratable)
+
+
Parameters:
+
+
name: str

name of this wrapper

+
+
elaboratable: Elaboratable

Amaranth’s Elaboratable object to wrap

+
+
+
+
+
+ +
+
+get_ports() → List[WrapperPort]
+

Return a list of external ports.

+
+ +
+
+get_ports_hier() → Mapping[str, Signal | Mapping[str, Signal | SignalMapping]]
+

Maps elaboratable’s Signature to a nested dictionary of WrapperPorts. +See _gather_signature_ports for more details.

+
+ +
+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/examples.html b/developers_guide/examples.html new file mode 100644 index 00000000..1dcb7725 --- /dev/null +++ b/developers_guide/examples.html @@ -0,0 +1,802 @@ + + + + + + + + + + + + + + + + Examples - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ +
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+ + + + + + +
+
+
+ + + + +
+
+ + + + + + + + +

Examples

+
+

Note

+

Basic usage of examples is explained in the Getting started section.

+
+

Examples provided with this project should cover from very simple designs to complex fully synthesizable cores. +They should be sorted by increasing complexity and number of used features, e.g:

+
    +

  • 101: minimal base design

    • +

  • 102: introduce user to parameters

    • +

  • 103: introduce user to slicing

    • +

  • 104: introduce user to interfaces

    • +

  • 105: etc.

    • +
+

Developers are encouraged to create/add new examples in the same spirit. +Simple examples are used to teach how to use this tool and demonstrate its features. +Real-world use cases are also welcome to prove that the implementation is mature enough to handle practical designs.

+ + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/fusesocbuilder.html b/developers_guide/fusesocbuilder.html new file mode 100644 index 00000000..d8f83212 --- /dev/null +++ b/developers_guide/fusesocbuilder.html @@ -0,0 +1,974 @@ + + + + + + + + + + + + + + + + FuseSocBuilder - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+
+ +
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+ + + +
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+ + + + +
+
+ + + + + + + + +

FuseSocBuilder

+

Topwrap has support for generating FuseSoC’s core files with FuseSocBuilder. +Such core file contains information about source files and synthesis tools. +Generation is based on a jinja template that defaults to topwrap/templates/core.yaml.j2 but can be overridden.

+

Here’s an example of how to generate a simple project:

+
from topwrap.fuse_helper import FuseSocBuilder
+fuse = FuseSocBuilder()
+
+# add source of the IPs used in the project
+fuse.add_source('DMATop.v', 'verilogSource')
+
+# add source of the top file
+fuse.add_source('top.v', 'verilogSource')
+
+# specify the names of the Core file and the directory where sources are stored
+# generate the project
+fuse.build('build/top.core', 'sources')
+
+
+
+

Warning

+

Default template in topwrap/templates/core.yaml.j2 does not make use of resources added with add_dependency() or add_external_ip(), i.e. they won’t be present in the generated core file.

+
+
+
+class FuseSocBuilder(part)
+

Use this class to generate a FuseSoC .core file

+
+
+__init__(part)
+
+ +
+
+add_dependency(dependency: str)
+

Adds a dependency to the list of dependencies in the core file

+
+ +
+
+add_external_ip(vlnv: str, name: str)
+

Store information about IP Cores from Vivado library +to generate hooks that will add the IPs in a TCL script.

+
+ +
+
+add_source(filename, type)
+

Adds an HDL source to the list of sources in the core file

+
+ +
+
+add_sources_dir(sources_dir)
+

Given a name of a directory, add all files found inside it. +Recognize VHDL, Verilog, and XDC files.

+
+ +
+
+build(core_filename, sources_dir=[], template_name=None)
+

Generate the final create .core file

+
+
Parameters:
+
+
sources_dir=[]

additional directory with source files to add

+
+
template_name=None

name of jinja2 template to be used, +either in working directory, or bundled with the package. +defaults to a bundled template

+
+
+
+
+
+ +
+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/future_enhancements.html b/developers_guide/future_enhancements.html new file mode 100644 index 00000000..694be8cc --- /dev/null +++ b/developers_guide/future_enhancements.html @@ -0,0 +1,880 @@ + + + + + + + + + + + + + + + + Future enhancements - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ + + + + + +
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+
+ + + + +
+
+ + + + + + + + +

Future enhancements

+

Support for hierarchical block design in Pipeline Manager

+

Currently topwrap supports creating hierarchical designs only by manually writing the hierarchy in the design description YAML. +Supporting such feature in the Pipeline Manager via its subgraphs would be a huge improvement in terms of organizing complex designs.

+

Bus management

+

Another goal we’d like to achieve is to enable users to create full-featured designs with processors by providing proper support for bus management. +This should include features such as:

+
    +

  • ability to specify the address of a peripheral device on the bus

    • +

  • support for the most popular buses or the ones that we use (AXI, wishbone, Tile-link)

    • +
+

This will require writing or creating bus arbiters (round-robin, crossbar) and providing a mechanism for connecting master(s) and slave(s) together. +As a result, the user should be able to create complex SoC with Topwrap.

+

Currently only experimental support for Wishbone with a round-robin arbiter is available.

+

Improve the process of recreating a design from a YAML file

+

One of the main features that are supported by Topwrap and Pipeline Manager is exporting and importing user-created design to or from a design description YAML. However, during these conversions, information about the positions of user-added nodes is not preserved. This is cumbersome in the case of complicated designs since the imported nodes cannot be placed in the optimal positions.

+

Therefore, one of our objectives is to provide a convenient way of creating and restoring user-created designs in Pipeline Manager, so that the user doesn’t have to worry about node positions when importing a design to Pipeline Manager.

+

Support for parsing SystemVerilog sources

+

Information about IP cores is stored in IP core description YAMLs. These files can be generated automatically from HDL source files - currently Verilog and VHDL are supported. Our goal is to provide the possibility of generating such YAMLs from SystemVerilog too.

+

Provide a way to parse HDL sources from the Pipeline Manager level

+

Another issue related to HDL parsing is that the user has to manually parse HDL sources to obtain the IP core description YAMLs. Then the files need to be provided as command-line parameters when launching the Topwrap Pipeline Manager client application. Therefore, we aim to provide a way of parsing HDL files and including them in the editor directly from the Pipeline Manager level.

+

Ability to produce top-level wrappers in VHDL

+

Topwrap now uses Amaranth to generate top-level design in Verilog. We would also like to add the ability to produce such designs in VHDL.

+

Library of open-source cores

+

Currently user has to supply all of the cores used in the design manually or semi-manually (e.g. through FuseSoC). +A repository of open-source cores that could be easily reused in topwrap would improve convenience and allow quickly putting together a design from premade hardware blocks.

+

Integrating with other tools

+

Topwrap can build the design but testing and synthesis rely on the user - they have to automate this process themselves (e.g. with makefiles). +Ideally the user should be able to write scripts that integrate tools for synthesis, simulation and co-simulation (e.g. with Renode) with topwrap. +Some would come pre-packaged with topwrap (e.g. simulation with verilator, synthesis with vivado). +It should also be possible to invoke these from the Pipeline Manager GUI by using its ability to add custom buttons and integrated terminal.

+ + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/interface.html b/developers_guide/interface.html new file mode 100644 index 00000000..a616c07d --- /dev/null +++ b/developers_guide/interface.html @@ -0,0 +1,887 @@ + + + + + + + + + + + + + + + + Interface definition - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + +
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+ + + + + + + + +

Interface definition

+

Topwrap uses interface definition files for its parsing functionality. +These are used to match a given set of signals that appear in the HDL source with signals in the interface definition.

+

InterfaceDefinition is defined as a marshmallow_dataclass.dataclass - this enables loading YAML structure into Python objects and performs validation (that the YAML has the correct format) and typechecking (that the loaded values are of correct types).

+
+
+class InterfaceDefinition(name: str, port_prefix: str, signals: InterfaceDefinitionSignals)
+

Interface described in YAML interface definition file

+
+
+__init__(name: str, port_prefix: str, signals: InterfaceDefinitionSignals)
+
+ +
+
+Schema
+

alias of InterfaceDefinition

+
+ +
+ +
+
+get_interface_by_name(name: str) → InterfaceDefinition | None
+

Retrieve interface definition by its name

+
+
Returns:
+

InterfaceDefinition object, or None if there’s no such interface

+
+
+
+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/ipconnect.html b/developers_guide/ipconnect.html new file mode 100644 index 00000000..3e46c95e --- /dev/null +++ b/developers_guide/ipconnect.html @@ -0,0 +1,1686 @@ + + + + + + + + + + + + + + + + IPConnect class - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ +
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+ + + +
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+ + + + + + +
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+
+ + + + +
+
+ + + + + + + + +

IPConnect class

+

IPConnect provides means of connecting ports and interfaces of objects that are subclasses of Wrapper. +Since IPConnect is a subclass of Wrapper itself, this means that it also has IO - ports and interfaces, and that multiple IPConnects can have their ports and interfaces connected to each other (or other objects that subclass Wrapper).

+../_images/ipconnect.png +

Instances of Wrapper objects can be added to an IPConnect using add_component() method:

+
# create a wrapper for an IP
+dma = IPWrapper('DMATop.yaml', ip_name='DMATop', instance_name='DMATop0')
+ipc = IPConnect()
+ipc.add_component("dma", dma)
+
+
+

Connections between cores can then be made with connect_ports() and connect_interfaces() based on names of the components and names of ports/interfaces:

+
ipc.connect_ports("comp1_port_name", "comp1_name", "comp2_port_name", "comp2_name")
+ipc.connect_interfaces("comp1_interface_name", "comp1_name", "comp2_interface_name", "comp2_name")
+
+
+

Setting ports or interfaces of a module added to IPConnect as external with _set_port() and _set_interface() and allows these ports/interfaces to be connected to other Wrapper instances.

+
ipc._set_port("comp1_name", "comp1_port_name", "external_port_name")
+ipc._set_interface("comp1_name", "comp1_interface_name", "external_interface_name")
+
+
+

This is done automatically in make_connections() method when the design is built based on the data from the YAML design description.

+
+
+class IPConnect(*args, src_loc_at=0, **kwargs)
+

Connector for multiple IPs, capable of connecting their interfaces +as well as individual ports.

+
+
+__init__(name: str = 'ip_connector')
+
+ +
+
+_connect_external_ports(internal: WrapperPort, external: WrapperPort)
+

Makes a pass-through connection - port of an internal module in IPConnect +is connected to an external IPConnect port.

+
+
Parameters:
+
+
internal: WrapperPort

port of an internal module of IPConnect

+
+
external: WrapperPort

external IPConnect port

+
+
+
+
+
+ +
+
+_connect_internal_ports(port1: WrapperPort, port2: WrapperPort)
+

Connects two ports with matching directionality. Disallowed configurations are: +- input to input +- output to output +- inout to inout +All other configurations are allowed.

+
+
Parameters:
+
+
port1: WrapperPort

1st port to connect

+
+
port2: WrapperPort

2nd port to connect

+
+
+
+
+
+ +
+
+_connect_to_external_port(internal_port: str, internal_comp: str, external_port: str, external: DesignExternalPorts) → None
+

Connect internal port of a component to an external port

+
+
Parameters:
+
+
internal_port: str

internal port name in internal_component to connect to external_port

+
+
internal_comp: str

internal component name

+
+
external_port: str

external port name

+
+
external: DesignExternalPorts

dictionary in the form of {“in”: list, “out”: list, “inout”: list} containing +port names specified as external in each of the three categories. All keys are +optional and lack of a category implies an empty list

+
+
+
+
+
+ +
+
+_set_interface(comp_name: str, iface_name: str, external_iface_name: str) → None
+

Set interface specified by name as an external interface

+
+
Parameters:
+
+
comp_name: str

name of the component - hierarchy or IP core

+
+
iface_name: str

interface name in the component

+
+
external_iface_name: str

external name of the interface specified in “external” section

+
+
+
+
Raises:
+

ValueError – if such interface doesn’t exist

+
+
+
+ +
+
+_set_port(comp_name: str, port_name: str, external_name: str) → None
+

Set port specified by name as an external port

+
+
Parameters:
+
+
comp_name: str

name of the component - hierarchy or IP core

+
+
port_name: str

port name in the component

+
+
external_name: str

external name of the port specified in “external” section

+
+
+
+
Raises:
+

ValueError – if such port doesn’t exist

+
+
+
+ +
+
+add_component(name: str, component: Wrapper) → None
+

Add a new component to this IPConnect, allowing to make connections with it

+
+
Parameters:
+
+
name: str

name of the component

+
+
component: Wrapper

Wrapper object

+
+
+
+
+
+ +
+
+connect_interfaces(iface1: str, comp1_name: str, iface2: str, comp2_name: str) → None
+

Make connections between all matching ports of the interfaces

+
+
Parameters:
+
+
iface1: str

name of the 1st interface

+
+
comp1_name: str

name of the 1st IP

+
+
iface2: str

name of the 2nd interface

+
+
comp2_name: str

name of the 2nd IP

+
+
+
+
Raises:
+

ValueError – if any of the IPs doesn’t exist

+
+
+
+ +
+
+connect_ports(port1_name: str, comp1_name: str, port2_name: str, comp2_name: str) → None
+

Connect ports of IPs previously added to this Connector

+
+
Parameters:
+
+
port1_name: str

name of the port of the 1st IP

+
+
comp1_name: str

name of the 1st IP

+
+
port2_name: str

name of the port of the 2nd IP

+
+
comp2_name: str

name of the 2nd IP

+
+
+
+
Raises:
+

ValueError – if such IP doesn’t exist

+
+
+
+ +
+
+get_ports() → list
+

Return a list of external ports of this module

+
+ +
+
+make_connections(ports: DS_PortsT, interfaces: DS_InterfacesT, external: DesignExternalSection) → None
+

Use names of port and names of ips to make connections

+
+
Parameters:
+
+
ports: DS_PortsT

“ports” section in the YAML design specification

+
+
interfaces: DS_InterfacesT

“interfaces” section in the YAML design specification

+
+
external: DesignExternalSection

“external” section in the YAML design specification

+
+
+
+
+
+ +
+
+make_interconnect_connections(interconnects: Dict[str, DesignSectionInterconnect], external: DesignExternalSection)
+

Connect slaves and masters to their respective interfaces in the interconnect

+
+
Parameters:
+
+
interconnects: Dict[str, DesignSectionInterconnect]

“interconnects” section in the YAML design specification

+
+
external: DesignExternalSection

“external” section in the YAML design specification

+
+
+
+
+
+ +
+
+set_constant(comp_name: str, comp_port: str, target: int) → None
+

Set a constant value on a port of an IP

+
+
Parameters:
+
+
comp_name: str

name of the IP or hierarchy

+
+
comp_port: str

name of the port of the IP or hierarchy

+
+
target: int

int value to be assigned

+
+
+
+
Raises:
+

ValueError – if such IP doesn’t exist

+
+
+
+ +
+
+validate_inout_connections(inouts: Collection[Tuple[str, str]])
+

Checks that all inout ports of any IP or hierarchy in the design are explicitly +listed in the ‘external’ section.

+
+
Parameters:
+
+
inouts: Collection[Tuple[str, str]]

external.ports.inout section of the design description YAML

+
+
+
+
+
+ +
+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/ipwrapper.html b/developers_guide/ipwrapper.html new file mode 100644 index 00000000..816cfc8c --- /dev/null +++ b/developers_guide/ipwrapper.html @@ -0,0 +1,921 @@ + + + + + + + + + + + + + + + + IPWrapper class - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ + + +
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+ + + + + + +
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+
+ + + + +
+
+ + + + + + + + +

IPWrapper class

+

IPWrapper provides an abstraction over a raw HDL source file. +Instances of this class can be created from a loaded YAML IP-core description.

+

Under the hood it will create Amaranth’s Instance object during elaboration, referencing a particular HDL module and it will appear as a module instantiation in the generated toplevel. +Ports and interfaces (lists of ports) can be retrieved via standard methods of Wrapper. +These are instances of WrapperPorts.

+../_images/wrapper.png +
+
+class IPWrapper(*args, src_loc_at=0, **kwargs)
+

This class instantiates an IP in a wrapper to use its individual ports +or grouped ports as interfaces.

+
+
+__init__(yaml_path: Path, ip_name: str, instance_name: str, params={})
+
+
Parameters:
+
+
yaml_path: Path

path to the IP Core description yaml file

+
+
ip_name: str

name of the module to wrap

+
+
instance_name: str

name of this instance

+
+
params={}

optional, HDL parameters of this instance

+
+
+
+
+
+ +
+
+get_ports() → List[WrapperPort]
+

Return a list of all ports that belong to this IP.

+
+ +
+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/parsing.html b/developers_guide/parsing.html new file mode 100644 index 00000000..6dc915d8 --- /dev/null +++ b/developers_guide/parsing.html @@ -0,0 +1,904 @@ + + + + + + + + + + + + + + + + Deducing interfaces - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Deducing interfaces

+

This section describes how inferring interfaces works when using topwrap parse with --iface-deduce, --iface or --use-yosys options.

+

The problem can be described as follows: given a set of signals, infer what interfaces are present in this set and assign signals to appropriate interfaces. +Interface names and types (AXI4, AXI Stream, Wishbone, etc.) are, in the general case, not given in advance. +Algorithm implemented in topwrap works roughly as follows:

+
    +

  1. Split the given signal set into disjoint subsets of signals based on common prefixes in their names

    2. +

  2. For a given subset, try to pair each signal name (as it appears in the RTL) with the name of an interface signal (as it is defined in the specification of a particular interface). +This pairing is called “a matching”. +Matching with signals from all defined interfaces is tried.

    3. +

  3. For a given subset and matched interface, infer the interface direction (master/slave) based on the direction of some signal in this set.

    4. +

  4. Compute score for each matching, e.g. if signal names contain cyc, stb and ack (and possibly more) it’s likely that this set is a Wishbone interface. +Among all interfaces, interface that has the highest matching score is selected.

    5. +
+

Step 1. - splitting ports into subsets

+

First, all ports of a module are grouped into disjoint subsets. Execution of this step differs based on the options supplied to topwrap parse:

+
    +

  • with --iface the user supplies topwrap with interface names - ports with names starting with a given interface name will be put in the same subset.

    • +

  • with --use-yosys grouping is done by parsing the RTL source with yosys, where ports have attributes in the form of (* interface="interface_name" *). +Ports with the same interface_name will be put in the same subset.

    • +

  • with --iface-deduce grouping is done by computing longest common prefixes among all ports. +This is done with the help of a trie and only allows prefixes that would split the port name on an underscore (e.g. in under_score valid prefixes are an empty string, under and under_score) or a camel-case word boundary (e.g. in wordBoundary valid prefixes are an empty string, word and wordBoundary). +As with user-supplied prefixes, ports with names starting with a given prefix will be put in the same subset.

    • +
+

Step 2. - matching ports with interface signal names

+

Given a subset of ports from a previous step, this step tries to match a regexp from an interface definition YAML for a given interface signal to one of the port names and returns a collection of pairs: RTL port + interface port. +For example, when matching against AXI4, a port named axi_a_arvalid should match to an interface port named ARVALID in the interface definition YAML.

+

This operation is performed for all defined interfaces per a given subset of ports so the overall result of this step is a collection of matchings. +For most interfaces these matching will be poor - e.g. axi_a_arvalid or other AXI4 signals won’t match to most Wishbone interface signals, but an interface that a human would usually assign to a given set of signals will have the most signals matched.

+

Step 3. - inferring interface direction

+

This step picks a representative RTL signal from a single signal matching from the previous step and checks its direction against direction of the corresponding interface signal in interface definition YAML - if it’s the same then it’s a master interface (since the convention in interface description files is to describe signals from the master’s perspective), otherwise it’s a slave.

+

Step 4. - computing interface matching score

+

This step computes a score for each matching returned by step 2. +This score is based on the number of matched/unmatched optional/required signals in each matching.

+

Not matching some signals in a given group (from step 1.) is heavily penalized to encourage selecting interface that “fits” a given group best. +For example, AXI Lite is a subset of AXI4, so a set of signals that should be assigned AXI4 interface could very well fit the description of AXI Lite, but this mechanism discourages selecting such matching in favor of selecting the other.

+

Not matching some signals of a given interface (from interface description YAML) is also penalized. +Inverting the previous example, a set of signals that should be assigned AXI Lite interface could very well fit the description of AXI4, but because it’s missing a few AXI4 signals so selecting this matching is discouraged in favor of selecting the other.

+

Good scoring function

+

A well-behaving scoring function should satisfy some properties to ensure that the best “fitting” interface is selected. +To describe these we introduce the following terminology:

+
    +

  • >/>=/== should be read as “must have a greater/greater or equal/equal score than”.

    • +

  • Partial matching means matching where some rtl signals haven’t been matched to interface signals, full matching means matching where all have been matched.

    • +
+

Current implementation when used with default config values satisfies these properties:

+
    +

  1. full matching with N+1 signals matched (same type) == full matching with N signals matched (same type)

    2. +

  2. full matching with N signals matched (same type) > partial matching with N signals matched (same type)

    3. +

  3. partial matching with N+1 signals matched (same type) > partial matching with N signals matched (same type)

    4. +

  4. full matching with N+1 required, M+1 optional signals >= full matching with N+1 optional, M optional signals >= full matching with N required, M+1 optional signals >= full matching with N required, M optional signals

    5. +
+

Properties 2-4 generally ensure that interfaces with more signals matched are favored more over those with less signals matched. +Property 1. follows from the current implementation and is not needed in all implementations.

+

Full details can be found in the implementation itself.

+ + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
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+ + +
+ +
+ + + +
+
+
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+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/setup.html b/developers_guide/setup.html new file mode 100644 index 00000000..132e85a3 --- /dev/null +++ b/developers_guide/setup.html @@ -0,0 +1,794 @@ + + + + + + + + + + + + + + + + Setup - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + + + + + +

Setup

+

It is required for developers to keep code style and recommended to frequently run tests. +In order to setup the developer’s environment install optional dependency groups topwrap-parse, tests and lint specified in pyproject.toml which include nox and pre-commit:

+
python -m venv venv
+source venv/bin/activate
+pip install -e ".[topwrap-parse,tests,lint]"
+
+
+

The -e option is for installing in editable mode - meaning changes in the code under development will be immediately visible when using the package.

+ + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/style.html b/developers_guide/style.html new file mode 100644 index 00000000..43164024 --- /dev/null +++ b/developers_guide/style.html @@ -0,0 +1,886 @@ + + + + + + + + + + + + + + + + Code style - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ + + + + + + + +

Code style

+

Automatic formatting and linting of the code can be performed with either nox or pre-commit.

+

Lint with nox

+

After successful setup, nox sessions can be executed to perform lint checks:

+
nox -s lint
+
+
+

This runs isort, black, flake8 and codespell and fixes almost all formatting and linting problems automatically, but a small minority has to be fixed by hand (e.g. unused imports).

+
+

Note

+

To reuse current virtual environment and avoid long installation time use -R option:

+
nox -R -s lint
+
+
+
+
+

Note

+

pre-commit can also be run from nox:

+
nox -s pre_commit
+
+
+
+

Lint with pre-commit

+

Alternatively, you can use pre-commit to perform the same job. +Pre-commit hooks need to be installed:

+
pre-commit install
+
+
+

Now, each use of git commit in the shell will trigger actions defined in the .pre-commit-config.yaml file. +Pre-commit can be easily disabled with a similar command:

+
pre-commit uninstall
+
+
+

If you wish to run pre-commit asynchronously, then use:

+
pre-commit run --all-files
+
+
+
+

Note

+

pre-commit by default also runs nox with isort,flake8, black and codespell sessions

+
+

Tools

+

Tools used in project for maintaining code style:

+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/tests.html b/developers_guide/tests.html new file mode 100644 index 00000000..ec368209 --- /dev/null +++ b/developers_guide/tests.html @@ -0,0 +1,877 @@ + + + + + + + + + + + + + + + + Tests - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + + + + + +

Tests

+

Topwrap functionality is validated with tests, leveraging the pytest library.

+

Test execution

+

Tests are located in the tests directory. +All tests can be run with nox by specifying the tests session:

+
nox -s tests
+
+
+

This only runs tests on python interpreter versions that are available locally. +There is also a session tests_in_env that will automatically install all required python versions, provided you have pyenv installed:

+
nox -s tests_in_env
+
+
+
+

Note

+

To reuse existing virtual environment and avoid long installation time use -R option:

+
nox -R -s tests_in_env
+
+
+
+

To force a specific Python version and avoid running tests for all listed versions, use -p VERSION option:

+
nox -p 3.10 -s tests_in_env
+
+
+

Tests can also be launched without nox by executing:

+
python -m pytest
+
+
+
+

Warning

+

When running tests by invoking pytest directly, tests are ran only on the locally selected python interpreter. +As CI runs them on all supported Python versions it’s recommended to run tests with nox on all versions before pushing.

+
+

Ignoring particular test can be done with --ignore=test_path, e.g:

+
python -m pytest --ignore=tests/tests_build/test_interconnect.py
+
+
+

Sometimes it’s useful to see what’s being printed by the test for debugging purposes. +Pytest captures all output from the test and displays it when all tests finish. +To see the output immediately, pass -s option to pytest:

+
python -m pytest -s
+
+
+

Test coverage

+

Test coverage is automatically generated when running tests with nox. +When invoking pytest directly it can be generated with --cov=topwrap option. +This will generate a summary of coverage displayed in CLI.

+
python -m pytest --cov=topwrap
+
+
+

Additionally, the summary can be generated in HTML with --cov=topwrap --cov-report html, where lines that were not covered by tests can be browsed:

+
python -m pytest --cov=topwrap --cov-report html
+
+
+

Generated report is available at htmlcov/index.html

+ + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/wrapper.html b/developers_guide/wrapper.html new file mode 100644 index 00000000..433e13ed --- /dev/null +++ b/developers_guide/wrapper.html @@ -0,0 +1,920 @@ + + + + + + + + + + + + + + + + Wrapper - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Wrapper

+

Wrapper is an abstraction over entities that have ports - examples include IP cores written in Verilog/VHDL, cores written in Amaranth and hierarchical collections for these that expose some external ports. +Subclasses of this class have to supply implementation of property get_ports() that has to return a list of all ports of the entity.

+
+
+class Wrapper(*args, src_loc_at=0, **kwargs)
+

Base class for modules that want to connect to each other.

+

Derived classes must implement get_ports method that returns +a list of WrapperPort’s - external ports of a class that can +be used as endpoints for connections.

+
+
+__init__(name: str)
+
+ +
+
+get_port_by_name(name: str) → WrapperPort
+

Given port’s name, return the port as WrapperPort object.

+
+
Raises:
+

ValueError – If such port doesn’t exist.

+
+
+
+ +
+
+get_ports() → List[WrapperPort]
+

Return a list of external ports.

+
+ +
+
+get_ports_of_interface(iface_name: str) → List[WrapperPort]
+

Return a list of ports of specific interface.

+
+
Raises:
+

ValueError – if such interface doesn’t exist.

+
+
+
+ +
+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
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+ + + + + + + + \ No newline at end of file diff --git a/developers_guide/wrapper_port.html b/developers_guide/wrapper_port.html new file mode 100644 index 00000000..b65aa85e --- /dev/null +++ b/developers_guide/wrapper_port.html @@ -0,0 +1,986 @@ + + + + + + + + + + + + + + + + Wrapper Port - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + + + + + +

Wrapper Port

+

Class WrapperPort is an extension to Amaranth’s Signal. +It wraps a port, adding a new name and optionally slicing the signal. +It adds these attributes:

+
WrapperPort.internal_name     # name of the port in internal source to be wrapped
+WrapperPort.direction         # DIR_FANIN, DIR_FANOUT or DIR_NONE
+WrapperPort.interface_name    # name of the group of ports (interface)
+WrapperPort.bounds            # range of bits that belong to the port
+                              # and range which is sliced from the port
+
+
+

See Port slicing to know more about bounds.

+

This is used in IPWrapper class implementation and there should be no need to use WrapperPort individually.

+
+

Warning

+

WrapperPort is scheduled to be replaced in favor of plain Amaranth’s Signal so it should not be used in any new functionality.

+
+
+
+class WrapperPort(shape=None, src_loc_at=0, **kwargs)
+
+
+__init__(shape=None, src_loc_at=0, *, bounds: List[int], name: str, internal_name: str, interface_name: str | None = None, direction: PortDirection)
+

Wraps a port, adding a new name and optionally slicing the signal

+
+
Parameters:
+
+
bounds: List[int]

4-element list where: +[0:1] - upper and lower bounds of reference signal, +[2:3] - upper and lower bounds of internal port, +which are either the same as reference port, +or a slice of the reference port

+
+
name: str

a new name for the signal

+
+
internal_name: str

name of the port to be wrapped/sliced

+
+
interface_name: str | None = None

name of the interface the port belongs to

+
+
direction: PortDirection

one of PortDirection, e.g. DIR_OUT

+
+
+
+
+
+ +
+
+static like(other, **kwargs)
+

Creates a WrapperPort object with identical parameters as other object

+
+
Parameters:
+
+
other

object to clone data from

+
+
**kwargs

optional constructor parameters to override

+
+
+
+
+
+ +
+ + + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/fusesoc.html b/fusesoc.html new file mode 100644 index 00000000..4f580592 --- /dev/null +++ b/fusesoc.html @@ -0,0 +1,796 @@ + + + + + + + + + + + + + + + + FuseSoC - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ +
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+ + + + + + +
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+ + + + +
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+ + + + + + + + +

FuseSoC

+

Topwrap uses FuseSoC to automate project generation and build process. +When topwrap build is invoked it generates a FuseSoC core file along with the top-level wrapper.

+

A template for the core file is bundled with Topwrap (templates/core.yaml.j2). +You may need to edit the file to change the backend tool, set additional Hooks and change the FPGA part name or other parameters. +By default, topwrap.fuse_helper.FuseSocBuilder searches for the template file in the directory you work in, so you should first copy the template into the project’s location.

+

After generating the core file you can run FuseSoC to generate bitstream and program FPGA:

+
fusesoc --cores-root build run project_1
+
+
+

This requires having the suitable backend tool in your PATH (Vivado, for example).

+ + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ + + +
+
+
+
+ + + + + + + + \ No newline at end of file diff --git a/genindex.html b/genindex.html new file mode 100644 index 00000000..55e8dcdc --- /dev/null +++ b/genindex.html @@ -0,0 +1,741 @@ + + + + + + + + + + + + + + + + None - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ +
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+ + + +
+
+
+ + + + + + +
+
+
+ + + + +
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+ + + + + + + + +None + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
+
+ + +
+ +
+ +
+ + + +
+ +
+
+ +
+ Copyright © Antmicro, 2024. + +
+ + 448398be + @ main + +
+ +
+ + + + + + + + + + + + + + + + + + + +
+ +
+ +
+
+ +
+
+
+
+ + + + + + + + + + \ No newline at end of file diff --git a/getting_started.html b/getting_started.html new file mode 100644 index 00000000..795c9ae3 --- /dev/null +++ b/getting_started.html @@ -0,0 +1,1037 @@ + + + + + + + + + + + + + + + + Getting started - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
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+ +
+ + + + +
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+ + + +
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+ + + + + + +
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+
+ + + + +
+
+ + + + + + + + +

Getting started

+

Installation

+
    +

  1. Install required system packages:

    +

    Debian:

    +
    apt install -y git g++ make python3 python3-pip antlr4 libantlr4-runtime-dev yosys npm
+
    +
    +

    Arch:

    +
    pacman -Syu git gcc make python3 python-pip antlr4 antlr4-runtime yosys npm
+
    +
    +

    Fedora:

    +
    dnf install git g++ make python3 python3-pip python3-devel antlr4 antlr4-cpp-runtime-devel yosys npm
+
    +
    +
    2. +

  2. Install the Topwrap package (It is highly recommended to run this step in a Python virtual environment, e.g. venv):

    +
    pip install .
+
    +
    +
    3. +
+
+

Note

+

To use topwrap parse command you also need to install optional dependencies:

+
pip install ".[topwrap-parse]"
+
+
+

On Arch-based distributions a symlink to antlr4 runtime library needs to created and an environment variable set:

+
ln -s /usr/share/java/antlr-complete.jar antlr4-complete.jar
+ANTLR_COMPLETE_PATH=`pwd` pip install ".[topwrap-parse]"
+
+
+

On Fedora-based distributions symlinks need to be made inside /usr/share/java directory itself:

+
sudo ln -s /usr/share/java/stringtemplate4/ST4.jar /usr/share/java/stringtemplate4.jar
+sudo ln -s /usr/share/java/antlr4/antlr4.jar /usr/share/java/antlr4.jar
+sudo ln -s /usr/share/java/antlr4/antlr4-runtime.jar /usr/share/java/antlr4-runtime.jar
+sudo ln -s /usr/share/java/treelayout/org.abego.treelayout.core.jar /usr/share/java/treelayout.jar
+pip install ".[topwrap-parse]"
+
+
+
+

Example usage

+

This section demonstrates the basic usage of Topwrap to generate IP wrappers and a top module.

+
    +

  1. Create IP core description file for every IP Core you want to use or let topwrap parse handle this for you. This file describes the ports, parameters and interfaces of an IP core.

    2. +
+

As an example, Verilog module such as:

+
module ibuf (
+    input  wire clk,
+    input  wire rst,
+    input  wire a,
+    output reg z
+);
+    // ...
+endmodule
+
+
+

Needs this corresponding description:

+
signals:
+  in:
+    - clk
+    - rst
+    - a
+  out:
+    - z
+
+
+
    +

  1. Create a design description file where you can specify all instances of IP cores and connections between them (project.yaml in this example)

    2. +
+
    +

  • Create instances of IP cores:

    • +
+
ips:
+  vexriscv_instance:
+    file: ipcores/gen_VexRiscv.yaml
+    module: VexRiscv
+  wb_ram_data_instance:
+    file: ipcores/gen_mem.yaml
+    module: mem
+  wb_ram_instr_instance:
+    file: ipcores/gen_mem.yaml
+    module: mem
+
+
+

file and module are mandatory fields providing the IP description file and the name of the HDL module as it appears in the source.

+
    +

  • (Optional) Set parameters for IP core instances:

    • +
+
parameters:
+  wb_ram_data_instance:
+    depth: 0x1000
+    memfile: "top_sram.init"
+  wb_ram_instr_instance:
+    depth: 0xA000
+    memfile: "bios.init"
+
+
+
    +

  • Connect desired ports of the IP cores:

    • +
+
ports:
+  wb_ram_data_instance:
+    clk: [some_other_ip, clk_out]
+    rst: [reset_core, reset0]
+  wb_ram_instr_instance:
+    clk: [some_other_ip, clk_out]
+    rst: [reset_core, reset0]
+  vexriscv_instance:
+    softwareInterrupt: [some_other_ip, sw_interrupt]
+    ...
+
+
+

Connections only need to be written once, i.e. if A connects to B, then only a connection A: B has to be specified (B: A is redundant).

+
    +

  • Connect desired interfaces of the IP cores:

    • +
+
interfaces:
+  vexriscv_instance:
+    iBusWishbone: [wb_ram_instr_instance, mem_bus]
+    dBusWishbone: [wb_ram_data_instance, mem_bus]
+
+
+
    +

  • Specify external ports or interfaces of the top module and connect them with chosen IP cores’ ports or interfaces:

    • +
+
ports:
+  vexriscv_instance:
+    timerInterrupt: ext_timer_interrupt
+
+...
+
+external:
+  ports:
+    out:
+      - ext_timer_interrupt
+  interfaces:
+    ...
+
+
+
    +

  1. Create a Core file template for FuseSoC, or use a default one bundled with Topwrap.

    2. +
+

You may want to modify the file to add dependencies, source files, or change the target board. +The file should be named core.yaml.j2. You can find an example template in examples/hdmi directory of the project. +If you don’t create any template a default template bundled with Topwrap will be used (stored in templates directory).

+
    +

  1. Place any additional source files in a directory (sources in this example).

    2. +

  2. Run Topwrap:

    +
    python -m topwrap build --design project.yaml --sources sources
+
    +
    +
    3. +
+

Example PWM design

+

There’s an example setup in examples/pwm.

+

In order to generate the top module, run:

+
make generate
+
+
+

In order to generate bitstream, add Vivado to your path and run:

+
make
+
+
+

The FPGA design utilizes an AXI-mapped PWM IP Core. +You can access its registers starting from address 0x4000000 (that’s the base address of AXI_GP0 on ZYNQ). +Each IP Core used in the project is declared in ips section in project.yml file. +ports section allows to connect individual ports of IP Cores, and interfaces is used analogously for connecting whole interfaces. +Finally, you can specify which ports will be used as external I/O in external section.

+

To connect the I/O signals to specific FPGA pins, you need proper mappings in a constraints file. See zynq.xdc used in the setup and modify it accordingly.

+_images/pwm.png +

Example HDMI design

+

There’s an example setup stored in examples/hdmi.

+

You can generate bitstream for desired target:

+
+
    +

  • Snickerdoodle Black:

    +
    make snickerdoodle
+
    +
    +
    • +

  • Zynq Video Board:

    +
    make zvb
+
    +
    +
    • +
+
+

If you wish to generate HDL sources without running Vivado, you can use:

+
make generate
+
+
+

You can find more information in README of the example setup.

+ + +
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+ + + Last update: + 2024-08-30 + + +
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+ + + + + + + + \ No newline at end of file diff --git a/hierarchies.html b/hierarchies.html new file mode 100644 index 00000000..12c848de --- /dev/null +++ b/hierarchies.html @@ -0,0 +1,854 @@ + + + + + + + + + + + + + + + + Hierarchies - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Hierarchies

+

Hierarchies allow for creating designs with subgraphs in them. +Subgraphs can contain multiple IP-cores and other subgraphs. +This allows creating nested designs in topwrap.

+

Format

+

All information about hierarchies is specified in design description. +hierarchies key must be a direct descendant of the design key. +Format is as follows:

+
hierarchies:
+    {hierarchy_name_1}:
+      ips: # ips that are used on this hierarchy level
+        {ip_name}:
+          ...
+
+      design:
+        parameters:
+          ...
+        ports: # ports connections internal to this hierarchy
+          # note that also you have to connect port to it's external port equivalent (if exists)
+          {ip1_name}:
+              {port1_name} : [{ip2_name}, {port2_name}]
+              {port2_name} : {port2_external_equivalent} # connection to external port equivalent. Note that it has to be to the parent port
+            ...
+        hierarchies:
+          {nested_hierarchy_name}:
+            # structure here will be the same as for {hierarchy_name_1}
+            ...
+      external:
+        # external ports and/or interfaces of this hierarchy; these can be
+        # referenced in the upper-level `ports`, `interfaces` or `external` section
+        ports:
+            in:
+              - {port2_external_equivalent}
+        ...
+    {hierarchy_name_2}:
+      ...
+
+
+

More complex hierarchy example can be found in examples/hierarchy.

+ + +
+
+ + + Last update: + 2024-08-30 + + +
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+ + + + + + + + \ No newline at end of file diff --git a/index.html b/index.html new file mode 100644 index 00000000..434dc18b --- /dev/null +++ b/index.html @@ -0,0 +1,871 @@ + + + + + + + + + + + + + + + + Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Welcome to Topwrap!

+
+

Documentation

+ +
+
+

Developer's Guide

+ +
+ + +
+
+ + + Last update: + 2024-08-30 + + +
+ + + + + + +
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+ + + + + + + + \ No newline at end of file diff --git a/interconnect_gen.html b/interconnect_gen.html new file mode 100644 index 00000000..30695bb6 --- /dev/null +++ b/interconnect_gen.html @@ -0,0 +1,904 @@ + + + + + + + + + + + + + + + + Interconnect generation - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Interconnect generation

+

Generating interconnects is an experimental feature of topwrap. +With a specification of which interfaces are masters or slaves and their address ranges, topwrap is able to automatically generate an interconnect conforming to this description. Currently supported interconnect types are:

+
    +

  • Wishbone round-robin

    • +
+

Format

+

The format for describing interconnects is specified below. interconnects key must be a direct descendant of the design key in the design description.

+
interconnects:
+  {interconnect1_name}:
+    # specify clock and reset to drive the interconnect with
+    clock: [{ip_name, clk_port_name}]
+    reset: [{ip_name, rst_port_name}]
+    # alternatively you can specify a connection to an external interface:
+    # clock: ext_clk_port_name
+    # reset: ext_rst_port_name
+
+    # specify interconnect type
+    type: {interconnect_type}
+
+    # specify interconnect parameters - interconnect-type-dependent (see "Interconnect params" section):
+    params:
+      {param_name1}: param_value1
+      ...
+
+    # specify masters and their interfaces connected to the bus
+    masters:
+    {master1_name}:
+      - {master1_iface1_name}
+      ...
+    ...
+
+    # specify slaves, their interfaces connected to the bus and their bus parameters
+    slaves:
+    {slave1_name}:
+      {slave1_interface1_name}:
+      # requests in address range [address, address+size) will be routed to this interface
+      address: {start_address}
+      size: {range_size}
+      ...
+    ...
+
+
+

Interconnect params

+

Different interconnect types may provide different configuration options. +This section lists parameter names for available interconnects for use in the params section of interconnect specification.

+

Wishbone round-robin

+

Corresponds to type: wishbone_roundrobin

+
    +

  • addr_width - bit width of the address line (addresses access data_width-sized chunks)

    • +

  • data_width - bit width of the data line

    • +

  • granularity - access granularity - smallest unit of data transfer that the interconnect is capable of transferring. Must be one of: 8, 16, 32, 64

    • +

  • features - optional, list of optional wishbone signals, can contain: err, rty, stall, lock, cti, bte

    • +
+

Limitations

+

Known limitations currently are:

+
    +

  • only word-sized addressing is supported (in other words - consecutive addresses access word-sized chunks of data)

    • +

  • crossing clock domains is not supported

    • +

  • down-converting (initiating multiple transactions on a narrow bus per one transaction on a wider bus) is not supported

    • +

  • up-converting is not supported

    • +
+ + +
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+ + + Last update: + 2024-08-30 + + +
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+ + + + + + + + \ No newline at end of file diff --git a/introduction.html b/introduction.html new file mode 100644 index 00000000..cb30a592 --- /dev/null +++ b/introduction.html @@ -0,0 +1,797 @@ + + + + + + + + + + + + + + + + Introduction - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Introduction

+

ASIC and FPGA designs consist of distinct blocks of logic bound together by a top-level design. +To take advantage of this modularity and enable reuse of blocks across designs and so facilitate the shift towards automation in logic design, it is necessary to derive a generic way to aggregate the blocks in various configurations and make the top-level design easy to parse and process automatically.

+

Topwrap is an open source command line toolkit for connecting individual HDL modules into full designs of varying complexity. +The toolkit is designed to take advantage of the ever-growing availability of open source digital logic designs and offers a user-friendly graphical interface which lets you mix-and-match GUI-driven design with CLI-based adjustments and present designs in a diagram form thanks to the integration with Antmicro’s Pipeline Manager.

+

Topwrap’s most notable features are:

+
    +

  • Parsing HDL design files with automatic recognition of common interfaces

    • +

  • Simple YAML-based description for command-line use

    • +

  • Capability to create a custom libraries for reuse across projects

    • +

  • User-friendly GUI powered by Kenning Pipeline Manager.

    • +
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+ + + + + + + + \ No newline at end of file diff --git a/objects.inv b/objects.inv new file mode 100644 index 00000000..aff13eba Binary files /dev/null and b/objects.inv differ diff --git a/pipeline_manager.html b/pipeline_manager.html new file mode 100644 index 00000000..1391247d --- /dev/null +++ b/pipeline_manager.html @@ -0,0 +1,934 @@ + + + + + + + + + + + + + + + + Kenning Pipeline Manager - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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Kenning Pipeline Manager

+

Topwrap can make use of Kenning Pipeline Manager to visualize the process of creating block design.

+

Run Topwrap with Pipeline Manager

+
    +

  1. Build and run Pipeline Manager server

    +

    In order to start creating block design in Pipeline Manager, you need to first build and run a server application - here is a brief instruction on how to achieve this (the process of building and installation of Pipeline Manager is described in detail in its documentation):

    +
    python -m topwrap kpm_build_server
+python -m topwrap kpm_run_server
+
    +
    +

    After executing the above-mentioned commands, the Pipeline Manager server is waiting for an external application (i.e. Topwrap) to connect on 127.0.0.1:9000 and you can connect to the web GUI frontend in your browser on http://127.0.0.1:5000.

    +
    2. +

  2. Establish connection with Topwrap

    +

    Once the Pipeline Manager server is running, you can now launch Topwrap’s client application in order to connect to the server. You need to specify:

    +
      +

    • IP address (127.0.0.1 is default)

      • +

    • listening port (9000 is default)

      • +

    • yamls describing IP cores, that will be used in the block design

      • +

    • design to load initially (None by default)

      • +
    +

    An example command, that runs Topwrap’s client, may look like this:

    +
    python -m topwrap kpm_client -h 127.0.0.1 -p 9000 \
+    topwrap/ips/axi/axi_axil_adapter.yaml \
+    examples/pwm/ipcores/{litex_pwm.yml,ps7.yaml} -d examples/pwm/project.yml
+
    +
    +
    3. +

  3. Create block design in Pipeline Manager

    +

    Upon successful connection to a Pipeline Manager server, Topwrap will generate and send to the server a specification describing the structure of previously selected IP cores. After that, you are free to create a custom block design by means of:

    +
      +

    • adding IP core instances to the block design. Each Pipeline Manager’s node has delete and rename options, which make it possible to remove the selected node and change its name respectively. This means that you can create multiple instances of the same IP core.

      • +

    • adjusting IP cores’ parameters values. Each node may have input boxes in which you can enter parameters’ values (default parameter values are added while adding an IP core to the block design):

      • +
    +_images/node_parameters.png +
      +

    • connecting IP cores’ ports and interfaces. Only connections between ports or interfaces of matching types are allowed. This is automatically checked by Pipeline Manager, as the types of nodes’ ports and interfaces are contained in the loaded specification, so Pipeline Manager will prevent you from connecting non-matching interfaces (e.g. AXI4 with AXI4Lite or a port with an interface). A green line will be displayed if a connection is possible to create, or a red line elsewhere:

      • +
    +_images/invalid_connection.png +
      +

    • specifying external ports or interfaces in the top module. This can be done by adding External Input, External Output or External Inout metanodes and creating connections between them and chosen ports or interfaces. Note that you should adjust the name of the external port or interface in a textbox inside selected metanode. In the example below, output port pwm of litex_pwm_top IP core will be made external in the generated top module and the external port name will be set to ext_pwm:

      • +
    +_images/external_port.png +

    Note, that you don’t always have to create a new block design by hand - you can use a design import feature to load an existing block design from a description in Topwrap’s yaml format.

    +

    An example block design in Pipeline Manager for the PWM project may look like this:

    +_images/pwm_design.png +
    4. +
+

Pipeline Manager features

+

While creating a custom block design, you can make use of the following Pipeline Manager’s features:

+
    +

  • export (save) design to a file

    • +

  • import (load) design from a file

    • +

  • validate design

    • +

  • build design

    • +
+

Export design to yaml description file

+

Created block design can be saved to a design description file in yaml format, using Pipeline Manager’s Save file option. +Target location on the filesystem can then be browsed in a filesystem dialog window.

+

Import design from yaml description file

+

Topwrap also supports conversion in the opposite way - block design in Pipeline Manager can be generated from a yaml design description file using Load file feature.

+

Design validation

+

Pipeline Manager is capable of performing some basic checks at runtime such as interface type checking while creating a connection. However you can also run more complex tests by using Pipeline Manager’s Validate option. Topwrap will then respond with a validity confirmation or error messages. The rules you need to follow in order to keep your block design valid are:

+
    +

  • multiple IP cores with the same name are not allowed (except from external metanodes).

    • +

  • parameters values can be integers of different bases (e.g. 0x28, 40 or 0b101000) or arithmetic expressions, that are later evaluated using numexpr.evaluate() function (e.g. (AXI_DATA_WIDTH+1)/4 is a valid parameter value assuming that a parameter named AXI_DATA_WIDTH exists in the same IP core). You can also write a parameter value in a Verilog format (e.g. 8'b00011111 or 8'h1F) - in such case it will be interpreted as a fixed-width bit vector.

    • +

  • a single port or interface cannot be external and connected to another IP core at the same time.

    • +

  • connections between two external metanodes are not allowed.

    • +

  • all the created external output or inout ports must have unique names. Only multiple input ports of IP cores can be driven be the same external signal.

    • +
+

Topwrap can also generate warnings if:

+
    +

  • some ports or interfaces remain unconnected.

    • +

  • multiple ports are connected to an External Input metanode with an empty External Name property.

    • +

  • inout ports of two modules are connected together (all inout ports are required to be directly connected to External Inout metanodes)

    • +
+

If a block design validation returns a warning, it means that the block design can be successfully built, but it is recommended to follow the suggestion and resolve a particular issue.

+

Building design

+

Once the design has been created and tested for validity, you can build design using Run button. If the design does not contain any errors, this will result in creating a top module in a directory where topwrap kpm_client was ran, similarly when using Topwrap’s topwrap build command.

+ + +
+
+ + + Last update: + 2024-08-30 + + +
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+ + + + + + + + \ No newline at end of file diff --git a/searchindex.js b/searchindex.js new file mode 100644 index 00000000..d0bea7e6 --- /dev/null +++ b/searchindex.js @@ -0,0 +1 @@ +Search.setIndex({"alltitles": {"Ability to produce top-level wrappers in VHDL": [[6, "ability-to-produce-top-level-wrappers-in-vhdl"]], "Building design": [[0, "building-design"], [22, "building-design"]], "Bus management": [[6, "bus-management"]], "Code style": [[12, "code-style"]], "Command-line Interface": [[0, "command-line-interface"]], "Config": [[2, "config"]], "Connect Topwrap to Pipeline Manager": [[0, "connect-topwrap-to-pipeline-manager"]], "Deducing interfaces": [[10, "deducing-interfaces"]], "Description files": [[1, "description-files"]], "Design Description": [[1, "design-description"]], "Design validation": [[22, "design-validation"]], "Developer's Guide": [[19, null]], "Documentation": [[19, null]], "ElaboratableWrapper class": [[3, "elaboratablewrapper-class"]], "Example HDMI design": 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false]], "like() (wrapperport static method)": [[15, "topwrap.amaranth_helpers.WrapperPort.like", false]], "make_connections() (ipconnect method)": [[8, "topwrap.ipconnect.IPConnect.make_connections", false]], "make_interconnect_connections() (ipconnect method)": [[8, "topwrap.ipconnect.IPConnect.make_interconnect_connections", false]], "schema (config attribute)": [[2, "topwrap.config.Config.Schema", false]], "schema (interfacedefinition attribute)": [[7, "topwrap.interface.InterfaceDefinition.Schema", false]], "set_constant() (ipconnect method)": [[8, "topwrap.ipconnect.IPConnect.set_constant", false]], "validate_inout_connections() (ipconnect method)": [[8, "topwrap.ipconnect.IPConnect.validate_inout_connections", false]], "wrapper (class in topwrap.wrapper)": [[14, "topwrap.wrapper.Wrapper", false]], "wrapperport (class in topwrap.amaranth_helpers)": [[15, "topwrap.amaranth_helpers.WrapperPort", false]]}, "objects": {"topwrap.amaranth_helpers": [[15, 0, 1, 0, "WrapperPort", "Wraps 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"Hierarchies", "Welcome to Topwrap!", "Interconnect generation", "Introduction", "Kenning Pipeline Manager", "User repositories"], "titleterms": {"": 19, "1": 10, "2": 10, "3": 10, "4": 10, "abil": 6, "block": 6, "bu": 6, "build": [0, 22], "class": [3, 8, 9], "code": 12, "command": 0, "commit": 12, "comput": 10, "config": 2, "connect": 0, "core": [0, 6], "coverag": 13, "deduc": 10, "definit": 7, "descript": [0, 1, 22], "design": [0, 1, 6, 17, 22], "develop": 19, "direct": 10, "document": 19, "elaboratablewrapp": 3, "enhanc": 6, "exampl": [4, 17], "execut": 13, "export": 22, "featur": 22, "file": [1, 6, 22], "format": [18, 20], "from": [6, 22], "function": 10, "fusesoc": 16, "fusesocbuild": 5, "futur": 6, "gener": [0, 20], "get": 17, "good": 10, "guid": 19, "hdl": 6, "hdmi": 17, "hierarch": 6, "hierarchi": 18, "import": 22, "improv": 6, "infer": 10, "instal": 17, "integr": 6, "interconnect": 20, "interfac": [0, 1, 7, 10], "introduct": 21, "ip": [0, 1], "ipconnect": 8, "ipwrapp": 9, "ken": 22, "level": 6, "librari": 6, "limit": 20, "line": 0, "lint": 12, "manag": [0, 6, 22], "match": 10, "name": 10, "nox": 12, "open": 6, "other": 6, "param": 20, "parameter": 1, "pars": 6, "pipelin": [0, 6, 22], "port": [1, 10, 15], "pre": 12, "process": 6, "produc": 6, "provid": 6, "pwm": 17, "recreat": 6, "repositori": 23, "robin": 20, "round": 20, "run": 22, "score": 10, "setup": 11, "signal": 10, "slice": 1, "sourc": 6, "split": 10, "start": 17, "step": 10, "style": 12, "subset": 10, "support": 6, "systemverilog": 6, "test": 13, "tool": [6, 12], "top": 6, "topwrap": [0, 19, 22], "usag": 17, "user": 23, "valid": 22, "vhdl": 6, "wai": 6, "welcom": 19, "width": 1, "wishbon": 20, "wrapper": [6, 14, 15], "yaml": [0, 6, 22]}}) \ No newline at end of file diff --git a/topwrap.pdf b/topwrap.pdf new file mode 100644 index 00000000..2a2528a3 Binary files /dev/null and b/topwrap.pdf differ diff --git a/user_repositories.html b/user_repositories.html new file mode 100644 index 00000000..0803cb83 --- /dev/null +++ b/user_repositories.html @@ -0,0 +1,823 @@ + + + + + + + + + + + + + + + + User repositories - Topwrap + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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User repositories

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Repositories allow for easy loading packages with IP-cores.

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You can add repositories to be loaded each time topwrap is ran by specifying them in configuration file.

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It has to be located in one of the following locations:

+
topwrap.yaml
+~/.config/topwrap/topwrap.yaml
+~/.config/topwrap/config.yaml
+
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Example contents of user config:

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force_interface_compliance: true
+repositories:
+  - name: name of repo
+    path: ~/path_to_repo/repo
+
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Topwrap provides internal API for constructing repositories in python code which can be found here

+

Structure of repository has to be as follows:

+
path_to_repository/
+|───cores
+|   |───someCore1
+|   |   |───srcs
+|   |   |   |   file1.v
+|   |   |   design.yaml
+|   |
+|   |───someCore1
+|       |───srcs
+|       |   |   file1.v
+|       |   design.yaml
+|
+|───interfaces(Optional)
+|   interface1.yaml
+|   interface2.yaml
+
+
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Repository has two main catalogs: cores and interfaces. Inside cores each core has it’s own catalog with it’s design file and srcs where are stored verilog/VHDL files.

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There is optional interfaces catalog where can be stored interfaces for cores.

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Example User Repo can be found in examples/user_repository.

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+ + + Last update: + 2024-08-30 + + +
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