From f9d1516164d5ca5a8af73ae893ea9690d8ca82b2 Mon Sep 17 00:00:00 2001 From: franciscatan-armedu Date: Thu, 9 Dec 2021 12:24:05 +0000 Subject: [PATCH] Unzipped code folders Unzipped code folders to aid tracking changes. --- ST-DiscoveryF4/Contents/Module_10/Code.zip | Bin 13449 -> 0 bytes .../Contents/Module_10/Code/RTX_Conf_CM.c | 205 ++++++ .../Contents/Module_10/Code/Template.uvoptx | 370 +++++++++++ .../Contents/Module_10/Code/Template.uvprojx | 558 ++++++++++++++++ .../Contents/Module_10/Code/drivers/adc.c | 44 ++ .../Contents/Module_10/Code/drivers/adc.h | 19 + .../Contents/Module_10/Code/drivers/gpio.c | 59 ++ .../Contents/Module_10/Code/drivers/gpio.h | 98 +++ .../Module_10/Code/drivers/platform.h | 37 ++ ST-DiscoveryF4/Contents/Module_10/Code/main.c | 183 ++++++ ST-DiscoveryF4/Contents/Module_11/Code.zip | Bin 13433 -> 0 bytes .../Contents/Module_11/Code/RTX_Conf_CM.c | 205 ++++++ .../Contents/Module_11/Code/Template.uvoptx | 404 ++++++++++++ .../Contents/Module_11/Code/Template.uvprojx | 553 ++++++++++++++++ .../Contents/Module_11/Code/drivers/adc.c | 44 ++ .../Contents/Module_11/Code/drivers/adc.h | 19 + .../Contents/Module_11/Code/drivers/gpio.c | 59 ++ .../Contents/Module_11/Code/drivers/gpio.h | 98 +++ .../Module_11/Code/drivers/platform.h | 37 ++ ST-DiscoveryF4/Contents/Module_11/Code/main.c | 114 ++++ .../Contents/Module_11/Code_Solution.zip | Bin 13973 -> 0 bytes .../Module_11/Code_Solution/RTX_Conf_CM.c | 205 ++++++ .../Module_11/Code_Solution/Template.uvoptx | 404 ++++++++++++ .../Module_11/Code_Solution/Template.uvprojx | 547 ++++++++++++++++ .../Module_11/Code_Solution/drivers/adc.c | 44 ++ .../Module_11/Code_Solution/drivers/adc.h | 19 + .../Module_11/Code_Solution/drivers/gpio.c | 59 ++ .../Module_11/Code_Solution/drivers/gpio.h | 98 +++ .../Code_Solution/drivers/platform.h | 37 ++ .../Contents/Module_11/Code_Solution/main.c | 326 ++++++++++ ST-DiscoveryF4/Contents/Module_12/Code.zip | Bin 24348 -> 0 bytes .../Contents/Module_12/Code/RTX_Conf_CM.c | 205 ++++++ .../Contents/Module_12/Code/Template.uvoptx | 355 ++++++++++ .../Contents/Module_12/Code/Template.uvprojx | 605 +++++++++++++++++ .../Contents/Module_12/Code/drivers/adc.c | 44 ++ .../Contents/Module_12/Code/drivers/adc.h | 19 + .../Contents/Module_12/Code/drivers/gpio.c | 59 ++ .../Contents/Module_12/Code/drivers/gpio.h | 98 +++ .../Module_12/Code/drivers/platform.h | 37 ++ .../Contents/Module_12/Code/drivers/setup.c | 43 ++ .../Contents/Module_12/Code/drivers/setup.h | 17 + .../Code/drivers/startup_stm32f4xx.s | 427 ++++++++++++ .../Module_12/Code/drivers/system_stm32f4xx.c | 553 ++++++++++++++++ ST-DiscoveryF4/Contents/Module_12/Code/main.c | 189 ++++++ .../Contents/Module_12/Code_Solution.zip | Bin 14751 -> 0 bytes .../Module_12/Code_Solution/RTX_Conf_CM.c | 205 ++++++ .../Module_12/Code_Solution/Template.uvoptx | 368 +++++++++++ .../Module_12/Code_Solution/Template.uvprojx | 610 ++++++++++++++++++ .../Module_12/Code_Solution/drivers/adc.c | 44 ++ .../Module_12/Code_Solution/drivers/adc.h | 19 + .../Module_12/Code_Solution/drivers/gpio.c | 59 ++ .../Module_12/Code_Solution/drivers/gpio.h | 98 +++ .../Code_Solution/drivers/platform.h | 37 ++ .../Module_12/Code_Solution/drivers/setup.c | 43 ++ .../Module_12/Code_Solution/drivers/setup.h | 17 + .../Contents/Module_12/Code_Solution/main.c | 185 ++++++ ST-DiscoveryF4/Contents/Module_3/Code_1.zip | Bin 12976 -> 0 bytes .../Contents/Module_3/Code_1/RTX_Conf_CM.c | 205 ++++++ .../Contents/Module_3/Code_1/Template.uvoptx | 395 ++++++++++++ .../Contents/Module_3/Code_1/Template.uvprojx | 532 +++++++++++++++ .../Contents/Module_3/Code_1/drivers/adc.c | 44 ++ .../Contents/Module_3/Code_1/drivers/adc.h | 19 + .../Contents/Module_3/Code_1/drivers/gpio.c | 59 ++ .../Contents/Module_3/Code_1/drivers/gpio.h | 98 +++ .../Module_3/Code_1/drivers/platform.h | 37 ++ .../Contents/Module_3/Code_1/main.c | 48 ++ ST-DiscoveryF4/Contents/Module_3/Code_2.zip | Bin 12860 -> 0 bytes .../Contents/Module_3/Code_2/RTX_Conf_CM.c | 205 ++++++ .../Contents/Module_3/Code_2/Template.uvoptx | 374 +++++++++++ .../Contents/Module_3/Code_2/Template.uvprojx | 543 ++++++++++++++++ .../Contents/Module_3/Code_2/drivers/adc.c | 44 ++ .../Contents/Module_3/Code_2/drivers/adc.h | 19 + .../Contents/Module_3/Code_2/drivers/gpio.c | 59 ++ .../Contents/Module_3/Code_2/drivers/gpio.h | 98 +++ .../Module_3/Code_2/drivers/platform.h | 37 ++ .../Contents/Module_3/Code_2/main.c | 43 ++ .../Contents/Module_3/Code_2_Solution.zip | Bin 13049 -> 0 bytes .../Module_3/Code_2_Solution/RTX_Conf_CM.c | 205 ++++++ .../Module_3/Code_2_Solution/Template.uvoptx | 369 +++++++++++ .../Module_3/Code_2_Solution/Template.uvprojx | 543 ++++++++++++++++ .../Module_3/Code_2_Solution/drivers/adc.c | 44 ++ .../Module_3/Code_2_Solution/drivers/adc.h | 19 + .../Module_3/Code_2_Solution/drivers/gpio.c | 59 ++ .../Module_3/Code_2_Solution/drivers/gpio.h | 98 +++ .../Code_2_Solution/drivers/platform.h | 37 ++ .../Contents/Module_3/Code_2_Solution/main.c | 49 ++ ST-DiscoveryF4/Contents/Module_5/Code.zip | Bin 12953 -> 0 bytes .../Contents/Module_5/Code/RTX_Conf_CM.c | 205 ++++++ .../Contents/Module_5/Code/Template.uvoptx | 375 +++++++++++ .../Contents/Module_5/Code/Template.uvprojx | 547 ++++++++++++++++ .../Contents/Module_5/Code/drivers/adc.c | 44 ++ .../Contents/Module_5/Code/drivers/adc.h | 19 + .../Contents/Module_5/Code/drivers/gpio.c | 59 ++ .../Contents/Module_5/Code/drivers/gpio.h | 98 +++ .../Contents/Module_5/Code/drivers/platform.h | 37 ++ ST-DiscoveryF4/Contents/Module_5/Code/main.c | 86 +++ .../Contents/Module_5/Code_Solution.zip | Bin 13306 -> 0 bytes .../Module_5/Code_Solution/RTX_Conf_CM.c | 205 ++++++ .../Module_5/Code_Solution/Template.uvoptx | 375 +++++++++++ .../Module_5/Code_Solution/Template.uvprojx | 547 ++++++++++++++++ .../Module_5/Code_Solution/drivers/adc.c | 44 ++ .../Module_5/Code_Solution/drivers/adc.h | 19 + .../Module_5/Code_Solution/drivers/gpio.c | 59 ++ .../Module_5/Code_Solution/drivers/gpio.h | 98 +++ .../Module_5/Code_Solution/drivers/platform.h | 37 ++ .../Contents/Module_5/Code_Solution/main.c | 282 ++++++++ 106 files changed, 16599 insertions(+) delete mode 100644 ST-DiscoveryF4/Contents/Module_10/Code.zip create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/RTX_Conf_CM.c create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/Template.uvoptx create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/Template.uvprojx create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/drivers/adc.c create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/drivers/adc.h create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/drivers/gpio.c create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/drivers/gpio.h create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/drivers/platform.h create mode 100644 ST-DiscoveryF4/Contents/Module_10/Code/main.c delete mode 100644 ST-DiscoveryF4/Contents/Module_11/Code.zip create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/RTX_Conf_CM.c create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/Template.uvoptx create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/Template.uvprojx create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/drivers/adc.c create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/drivers/adc.h create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/drivers/gpio.c create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/drivers/gpio.h create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/drivers/platform.h create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code/main.c delete mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution.zip create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/RTX_Conf_CM.c create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/Template.uvoptx create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/Template.uvprojx create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/adc.c create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/adc.h create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/gpio.c create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/gpio.h create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/platform.h create mode 100644 ST-DiscoveryF4/Contents/Module_11/Code_Solution/main.c delete mode 100644 ST-DiscoveryF4/Contents/Module_12/Code.zip create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/RTX_Conf_CM.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/Template.uvoptx create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/Template.uvprojx create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/adc.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/adc.h create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/gpio.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/gpio.h create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/platform.h create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/setup.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/setup.h create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/startup_stm32f4xx.s create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/drivers/system_stm32f4xx.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code/main.c delete mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution.zip create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/RTX_Conf_CM.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/Template.uvoptx create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/Template.uvprojx create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/adc.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/adc.h create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/gpio.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/gpio.h create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/platform.h create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/setup.c create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/setup.h create mode 100644 ST-DiscoveryF4/Contents/Module_12/Code_Solution/main.c delete mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1.zip create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/RTX_Conf_CM.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/Template.uvoptx create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/Template.uvprojx create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/adc.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/adc.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/gpio.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/gpio.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/platform.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_1/main.c delete mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2.zip create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/RTX_Conf_CM.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/Template.uvoptx create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/Template.uvprojx create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/adc.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/adc.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/gpio.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/gpio.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/platform.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2/main.c delete mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution.zip create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/RTX_Conf_CM.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/Template.uvoptx create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/Template.uvprojx create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/adc.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/adc.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/gpio.c create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/gpio.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/platform.h create mode 100644 ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/main.c delete mode 100644 ST-DiscoveryF4/Contents/Module_5/Code.zip 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+/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 64 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 16000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 200 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 0 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_10/Code/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_10/Code/Template.uvoptx new file mode 100644 index 0000000..37b19c6 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_10/Code/Template.uvoptx @@ -0,0 +1,370 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O8398 -S3 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC168000000 -TP21 -TDS8053 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + + + + + + 1 + 0 + SP + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + RTX + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_10/Code/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_10/Code/Template.uvprojx new file mode 100644 index 0000000..8ab2f66 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_10/Code/Template.uvprojx @@ -0,0 +1,558 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + STM32F40XX + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\stm32f4xx_hal_conf.h + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_10/Code/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_10/Code/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_10/Code/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_10/Code/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_10/Code/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/platform.h new file mode 100644 index 0000000..dbb30e5 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_10/Code/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 168000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_10/Code/main.c b/ST-DiscoveryF4/Contents/Module_10/Code/main.c new file mode 100644 index 0000000..6ebbc4b --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_10/Code/main.c @@ -0,0 +1,183 @@ + + +#include +#include + +#define MASK(x) (1UL << (x)) + +// Task IDs for the tasks +OS_TID t_PS; +OS_TID t_TRL; +OS_TID t_TGL; +OS_TID t_TBL; + +// Select only one of the scheduling options +#define SCHED_NPRE_NPRI 1 +#define SCHED_NPRE_PRI 0 +#define SCHED_PRE_PRI 0 + + +#define TOP_PRIORITY (9) +#define PS_PRIORITY (1) // try 1 (for low priority) and 5 (for high priority) +#define RED_PRIORITY (4) +#define BLUE_PRIORITY (3) +#define GREEN_PRIORITY (2) + + +#define TASK_PERIOD (30000) +#define TASK_DURATION (30) + +#if (SCHED_PRE_PRI | SCHED_NPRE_PRI) +#define SET_INTERVAL(x) os_itv_set(x) +#define TASK_SUSPEND os_itv_wait() +//#define TASK_SUSPEND os_tsk_pass () +#endif + +#if (SCHED_NPRE_NPRI) +#define SET_INTERVAL(x) +#define TASK_SUSPEND return; +#endif + + +void Delay (uint32_t nCount) +{ + uint32_t count = nCount*100000; + while(count--) + { + __NOP(); + } +} + + + +void Poll_Switch (void) { + while (gpio_get(SWITCH)) { // flash all LEDs + // Light up LEDs + gpio_set(LED[RED],LED_ON); + gpio_set(LED[BLUE],LED_ON); + gpio_set(LED[GREEN],LED_ON); + Delay(10); + // Turn off LEDs + gpio_set(LED[RED],LED_OFF); + gpio_set(LED[BLUE],LED_OFF); + gpio_set(LED[GREEN],LED_OFF); + Delay(10); + } +} + + +__task void Task_Poll_Switch (void) { + SET_INTERVAL(1); + for (;;) { +#if SCHED_NPRE_PRI + os_tsk_prio_self(TOP_PRIORITY); +#endif + Poll_Switch(); +#if SCHED_NPRE_PRI + os_tsk_prio_self(PS_PRIORITY); +#endif + + TASK_SUSPEND; + } +} + + +void ControlRedLED(void) { + gpio_set(LED[RED],LED_ON); + Delay(TASK_DURATION); + gpio_set(LED[RED],LED_OFF); +} + +__task void Task_ControlRedLED (void) { + SET_INTERVAL(TASK_PERIOD); + for (;;) { +#if SCHED_NPRE_PRI + os_tsk_prio_self(TOP_PRIORITY); +#endif + ControlRedLED(); +#if SCHED_NPRE_PRI + os_tsk_prio_self(RED_PRIORITY); +#endif + TASK_SUSPEND; + } +} + + + +void ControlBlueLED(void) { + gpio_set(LED[BLUE],LED_ON); + Delay(TASK_DURATION); + gpio_set(LED[BLUE],LED_OFF); +} + +__task void Task_ControlBlueLED (void) { + SET_INTERVAL(TASK_PERIOD); + for (;;) { +#if SCHED_NPRE_PRI + os_tsk_prio_self(TOP_PRIORITY); +#endif + ControlBlueLED(); +#if SCHED_NPRE_PRI + os_tsk_prio_self(BLUE_PRIORITY); +#endif + TASK_SUSPEND; + } +} + + +void ControlGreenLED (void) { + gpio_set(LED[GREEN],LED_ON); + Delay(TASK_DURATION); + gpio_set(LED[GREEN],LED_OFF); +} + +__task void Task_ControlGreenLED (void) { + SET_INTERVAL(TASK_PERIOD); + for (;;) { +#if SCHED_NPRE_PRI + os_tsk_prio_self(TOP_PRIORITY); +#endif + ControlGreenLED(); +#if SCHED_NPRE_PRI + os_tsk_prio_self(GREEN_PRIORITY); +#endif + TASK_SUSPEND; + } +} + + + +/*---------------------------------------------------------------------------- + The first task run by the OS and should do the initialization for other tasks + *----------------------------------------------------------------------------*/ +__task void init (void) { + t_PS = os_tsk_create( Task_Poll_Switch, PS_PRIORITY); + t_TRL = os_tsk_create( Task_ControlRedLED, RED_PRIORITY); + t_TBL = os_tsk_create( Task_ControlBlueLED, BLUE_PRIORITY); + t_TGL = os_tsk_create( Task_ControlGreenLED, GREEN_PRIORITY); + os_tsk_delete_self (); // Delete the init(self) task +} + +int main(void) +{ + gpio_set_mode(SWITCH,PullDown); + gpio_set_mode(LED[RED],Output); /* Initialize the LEDs */ + gpio_set_mode(LED[BLUE],Output); + gpio_set_mode(LED[GREEN],Output); +// Preemptive, prioritized with RTX +#if (SCHED_PRE_PRI | SCHED_NPRE_PRI) + os_sys_init(init); /* Initialize RTX and start init */ +#endif + +# if SCHED_NPRE_NPRI + while (1) { + Poll_Switch(); + ControlRedLED(); + ControlBlueLED(); + ControlGreenLED(); + } +#endif + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_11/Code.zip b/ST-DiscoveryF4/Contents/Module_11/Code.zip deleted file mode 100644 index 7569901b04effeededec27bc1053903f113af56a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13433 zcmZ{r18^o=+pc5VwkLKbwv7qj*qqqOgcIAgZQHhO+d8xV@0{BE|7xG^>RPLDRaf;| ztJnS9{j`EKC>R1& zvZDb=a68QW0=X3@=5qmw7l{nxv@uvB9*_O~Vv?)U26RA-;8>^Tr%%h6V?wYYGj5E#cDo)Cu=F1qZR5Drrh>B8l)#Pl7zM z9Egi;o3d%zl^oJKSSie=CPp726;`7t2f~t}!;tgaevRyJwsMIZk2yJq6}bT+z2J;m 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*---------------------------------------------------------------------------- + * Name: RTX_CONFIG.C + * Purpose: Configuration of RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 64 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 16000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 100 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_11/Code/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_11/Code/Template.uvoptx new file mode 100644 index 0000000..c1c88b3 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code/Template.uvoptx @@ -0,0 +1,404 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O8398 -S3 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC16000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + + + + + + 0 + 1 + i + + + 1 + 1 + producer_datum + + + 2 + 1 + consumer_datum + + + + + 1 + 0 + SP + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + `producer_datum + FF000000000000000000000000000000000033400000000000000000000000000000000070726F64756365725F646174756D0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700000001000000555555555555D53F1800000000000000000000000000000000000000200A0008 + + + 1 + `consumer_datum + 008000000000000000000000000000000000334000000000000000000000000000000000636F6E73756D65725F646174756D0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700000002000000555555555555D53F1800000000000000000000000000000000000000200A0008 + + + 2 + `i + 0000800000000000000014C000000000000026400000000000000000000000000000000069000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700000003000000555555555555D53F1800000000000000000000000000000000000000200A0008 + + + + + + + RTX + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_11/Code/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_11/Code/Template.uvprojx new file mode 100644 index 0000000..1f2299e --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code/Template.uvprojx @@ -0,0 +1,553 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + HSE_VALUE=8000000 + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\stm32f4xx_hal_conf.h + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_11/Code/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_11/Code/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_11/Code/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_11/Code/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_11/Code/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/platform.h new file mode 100644 index 0000000..52f2000 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 16000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_11/Code/main.c b/ST-DiscoveryF4/Contents/Module_11/Code/main.c new file mode 100644 index 0000000..cc3aa56 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code/main.c @@ -0,0 +1,114 @@ + + +#include +#include +#include + + +#define RMIN CLK_FREQ/20 +#define RMAX CLK_FREQ/10 +#define RDIV 5 +#define RAMT (RMAX-RMIN)/RDIV + +#define RANDOM_SEED 0 + +OS_TID taskID1; +OS_TID taskID2; + +#define BUFFER_SIZE 10 + +int buffer [BUFFER_SIZE]; +int producer_datum; +int consumer_datum; +int i = 0; + + + +void Delay (uint32_t nCount) +{ + while(nCount--) + { + __NOP(); + } +} + +/*---------------------------------------------------------------------------- + Produce a random number ranging from 0 to 19. + *----------------------------------------------------------------------------*/ +int produce(void){ + Delay(rand() % RDIV*RAMT + RMIN); + return (rand()%20); +} + +/*---------------------------------------------------------------------------- + Consume the datum, actually doing nothing. + *----------------------------------------------------------------------------*/ +void consume(int datum){ + Delay(rand() % RDIV*RAMT + RMIN); +} + +/*---------------------------------------------------------------------------- + Append the new datum to the buffer + *----------------------------------------------------------------------------*/ +void append(int datum){ + buffer[i]=datum; + Delay(rand() % RDIV*RAMT + RMIN); + i++; +} + +/*---------------------------------------------------------------------------- + Extract datum from the buffer + *----------------------------------------------------------------------------*/ +int extract(void){ + i--; + Delay(rand() % RDIV*RAMT + RMIN); + return buffer[i]; +} + + +__task void Producer(void){ + while(1){ + //Blue for Producer + gpio_set(LED[BLUE],1); + producer_datum=produce(); + append(producer_datum); + gpio_set(LED[BLUE],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +__task void Consumer(void){ + while(1){ + //Green for Consumer + gpio_set(LED[GREEN],1); + consumer_datum=extract(); + consume(consumer_datum); + gpio_set(LED[GREEN],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + + +/*---------------------------------------------------------------------------- + The first task run by the OS and should do the initialization for other tasks + *----------------------------------------------------------------------------*/ +__task void init (void) { + + + taskID1=os_tsk_create(Producer,0); + //taskID2=os_tsk_create(Consumer,0); + + os_tsk_delete_self (); // Delete the init(self) task +} + +int main(void) +{ + srand(RANDOM_SEED); + gpio_set_mode(LED[RED],Output); + gpio_set_mode(LED[GREEN],Output); + gpio_set_mode(LED[BLUE],Output); + Delay(RMIN); + os_sys_init(init); +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution.zip b/ST-DiscoveryF4/Contents/Module_11/Code_Solution.zip deleted file mode 100644 index 93e0f680d63370c0f2ebcb1b9c2ebbb138f2180e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13973 zcmZ{r1CS<5_vYW`bWhv1ZQC}cZQI?`wr$&*Hm7adwr%g+{r7m9))d1#y@hxrAjwzwLxEhB~=N|(%z#}>b>D{X!emKHbUw$w(K(*S41T-JRMjRJoiH7?JDOjm^D~d ziQb{pg7--UekucAa_Lg2G_9!FAH1fAK;)_QPNQ2F<(ke*KkrB8$fjEC-XW|{qe)Ye zmxwezOm!0AnD6&#Faz)py(;tGy{^68KFCoQ&qi#IUD^w~RUiTQXhWlGQF>93 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zbzlg*J{413qhijbw8*6FyOScWerAxEV>$^r;#5NDXLyqi^_DnIu*3va%)&AMkEfim zTQ$}+VGFyL^)Z9vplVvDG28<0fT4%Np;0jV)HJ&?)d-{$mK;W{^qjYgPkCgI1z&Ii zBwbVdQ0|r-$XgfpOcl>Q##^E#ATeB0Lo*7x9-mdm{5Nrt8>f~Sp?RaQcxhw-01DW+ z2Zb!@2c_dr9`ynS!_Hsjls8ILBg6xzV?Uz!MtW-(;2^H9U-My55=@dv>P0$|OaPKo zY*2v+yir^Lotv|N0HBcu3F>L|8>QcWEp4u|9o{^($pr5GWvq{gS6ih7DKNtI5 zL&-fiO!lgm!$x8tNBLn{b8;$;a&;dXI z{J+AVHjH${wMrzMI(P<|A8z27=?ep|GR|bpY*>i zIsJ#m{}U<+|9g?Z@So_vttkABLXiA7YW7d`-xBG+QEAe@(f_2?|78CyY5SYSCjWof z|9bDgxv0O{A?m-`zdhAI-~Dfj{WqUM`+xLXUJC3lF$X~YInn + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 64 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 16000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 100 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/Template.uvoptx new file mode 100644 index 0000000..53ab3ff --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/Template.uvoptx @@ -0,0 +1,404 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O8398 -S3 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC16000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + + + + + + 0 + 1 + producer_datum + + + 1 + 1 + consumer_datum + + + 2 + 1 + i + + + + + 1 + 0 + SP + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + `producer_datum + FF000000000000000000000000000000000033400000000000000000000000000000000070726F64756365725F646174756D0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700000001000000565555555555D53F1700000000000000000000000000000000000000100A0008 + + + 1 + `consumer_datum + 008000000000000000000000000000000000334000000000000000000000000000000000636F6E73756D65725F646174756D0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700000002000000565555555555D53F1700000000000000000000000000000000000000100A0008 + + + 2 + `i + 0000800000000000000014C000000000000026400000000000000000000000000000000069000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700000003000000555555555555D53F1700000000000000000000000000000000000000100A0008 + + + + + + + RTX + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/Template.uvprojx new file mode 100644 index 0000000..045b13b --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/Template.uvprojx @@ -0,0 +1,547 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + STM32F40XX + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/platform.h new file mode 100644 index 0000000..52f2000 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 16000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_11/Code_Solution/main.c b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/main.c new file mode 100644 index 0000000..00661ae --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_11/Code_Solution/main.c @@ -0,0 +1,326 @@ + + +#include +#include +#include + +#define RMIN CLK_FREQ/20 +#define RMAX CLK_FREQ/10 +#define RDIV 5 +#define RAMT (RMAX-RMIN)/RDIV + +#define RANDOM_SEED 0 + +OS_TID taskID1; +OS_TID taskID2; + +#define BUFFER_SIZE 10 + +#define MIN(X,Y) ((X) < (Y) ? (X) : (Y)) + +int buffer [BUFFER_SIZE]; +int producer_datum; +int consumer_datum; +int i = 0; + +OS_TID taskID1; +OS_TID taskID2; +OS_MUT mutexID; +OS_SEM semID; +OS_SEM semID1; +OS_SEM semID2; + +OS_SEM semIDA; +OS_SEM semIDB; +int tickets; + + +void Delay (uint32_t nCount) +{ + while(nCount--) + { + __NOP(); + } +} + +/*---------------------------------------------------------------------------- + Produce a random number ranging from 0 to 19. + *----------------------------------------------------------------------------*/ +int produce(void){ + Delay(rand() % RDIV*RAMT + RMIN); + return (rand()%20); +} + +/*---------------------------------------------------------------------------- + Consume the datum, actually doing nothing. + *----------------------------------------------------------------------------*/ +void consume(int datum){ + Delay(rand() % RDIV*RAMT + RMIN); +} + +/*---------------------------------------------------------------------------- + Append the new datum to the buffer + *----------------------------------------------------------------------------*/ +void append(int datum){ + buffer[i]=datum; + Delay(rand() % RDIV*RAMT + RMIN); + i++; +} + +/*---------------------------------------------------------------------------- + Extract datum from the buffer + *----------------------------------------------------------------------------*/ +int extract(void){ + i--; + Delay(rand() % RDIV*RAMT + RMIN); + return buffer[i]; +} + + + +//Original Version +__task void Producer(void){ + while(1){ + //Blue for Producer + gpio_set(LED[BLUE],1); + producer_datum=produce(); + append(producer_datum); + gpio_set(LED[BLUE],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +__task void Consumer(void){ + while(1){ + //Green for Consumer + gpio_set(LED[GREEN],1); + consumer_datum=extract(); + consume(consumer_datum); + gpio_set(LED[GREEN],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +//Mutex Version +__task void Producer_1(void){ + while(1){ + //Blue for Producer + gpio_set(LED[BLUE],1); + producer_datum=produce(); + os_mut_wait (mutexID, 0xFFFF); + append(producer_datum); + os_mut_release (mutexID); + gpio_set(LED[BLUE],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +__task void Consumer_1(void){ + while(1){ + //Green for Consumer + gpio_set(LED[GREEN],1); + os_mut_wait (mutexID, 0xFFFF); + consumer_datum=extract(); + os_mut_release (mutexID); + consume(consumer_datum); + gpio_set(LED[GREEN],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +//Signaling Version +__task void Producer_2(void){ + while(1){ + //Blue for Producer + gpio_set(LED[BLUE],1); + producer_datum=produce(); + append(producer_datum); + os_sem_send (semID); + gpio_set(LED[BLUE],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +__task void Consumer_2(void){ + while(1){ + //Green for Consumer + gpio_set(LED[GREEN],1); + os_sem_wait (semID, 0xFFFF ); + consumer_datum=extract(); + consume(consumer_datum); + gpio_set(LED[GREEN],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +//Two Semaphores Version +__task void Producer_3(void){ + while(1){ + //Blue for Producer + gpio_set(LED[BLUE],1); + producer_datum=produce(); + os_sem_wait (semID1, 0xFFFF); + append(producer_datum); + os_sem_send (semID1); + os_sem_send (semID2); + gpio_set(LED[BLUE],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +__task void Consumer_3(void){ + while(1){ + //Green for Consumer + gpio_set(LED[GREEN],1); + os_sem_wait (semID2, 0xFFFF ); + os_sem_wait (semID1, 0xFFFF ); + consumer_datum=extract(); + os_sem_send (semID1); + consume(consumer_datum); + gpio_set(LED[GREEN],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +//Swapped sem_send in Producer Version +__task void Producer_4(void){ + while(1){ + //Blue for Producer + gpio_set(LED[BLUE],1); + producer_datum=produce(); + os_sem_wait (semID1, 0xFFFF); + append(producer_datum); + os_sem_send (semID2); + os_sem_send (semID1); + gpio_set(LED[BLUE],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +__task void Consumer_4(void){ + while(1){ + //Green for Consumer + gpio_set(LED[GREEN],1); + os_sem_wait (semID2, 0xFFFF ); + os_sem_wait (semID1, 0xFFFF ); + consumer_datum=extract(); + os_sem_send (semID1); + consume(consumer_datum); + gpio_set(LED[GREEN],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +//Swapped sem_wait in Consumer Version +__task void Producer_5(void){ + while(1){ + //Blue for Producer + gpio_set(LED[BLUE],1); + producer_datum=produce(); + os_sem_wait (semID1, 0xFFFF); + append(producer_datum); + os_sem_send (semID1); + os_sem_send (semID2); + gpio_set(LED[BLUE],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +__task void Consumer_5(void){ + while(1){ + //Green for Consumer + gpio_set(LED[GREEN],1); + os_sem_wait (semID1, 0xFFFF ); + //The delay here is deliberately inserted to invite the deadlock + Delay(rand() % RDIV*RAMT + RMIN); + Delay(rand() % RDIV*RAMT + RMIN); + os_sem_wait (semID2, 0xFFFF ); + consumer_datum=extract(); + os_sem_send (semID1); + consume(consumer_datum); + gpio_set(LED[GREEN],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +//Mutex Signaling Version +__task void Producer_6(void){ + while(1){ + //Blue for Producer + gpio_set(LED[BLUE],1); + producer_datum=produce(); + os_mut_wait (mutexID, 0xFFFF); + append(producer_datum); + os_mut_release (mutexID); + os_sem_send (semID); + gpio_set(LED[BLUE],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +__task void Consumer_6(void){ + while(1){ + //Green for Consumer + gpio_set(LED[GREEN],1); + os_sem_wait (semID, 0xFFFF ); + os_mut_wait (mutexID, 0xFFFF); + consumer_datum=extract(); + os_mut_release (mutexID); + consume(consumer_datum); + gpio_set(LED[GREEN],0); + Delay(rand() % RDIV*RAMT + RMIN); + } +} + +//Solution for the general semaphore +//Semaphore A is actually a mutex +//Semaphore B is keeping track of if there is still any ticket. +void general_init_sem(int inital_value){ + os_sem_init (semIDA, 1); + os_sem_init (semIDB, MIN(1,inital_value)); + tickets = inital_value; +} +void general_wait_sem(void){ + os_sem_wait(semIDB,0xFFFF); + os_sem_wait(semIDA,0XFFFF); + tickets--; + if(tickets>0){ + os_sem_send(semIDB); + } + os_sem_send(semIDA); +} +void general_send_sem(void){ + os_sem_wait(semIDA,0xFFFF); + tickets++; + if(tickets==1){ + os_sem_send(semIDB); + } + os_sem_send(semIDA); +} + + +/*---------------------------------------------------------------------------- + The first task run by the OS and should do the initialization for other tasks + *----------------------------------------------------------------------------*/ +__task void init (void) { + os_mut_init (mutexID); + os_sem_init (semID, 0); + os_sem_init (semID1, 1); + os_sem_init (semID2, 0); + general_init_sem(0); + taskID1=os_tsk_create(Producer_6,0); + taskID2=os_tsk_create(Consumer_6,0); + os_tsk_delete_self (); // Delete the init(self) task +} + +int main(void) +{ + srand(RANDOM_SEED); + gpio_set_mode(LED[RED],Output); + gpio_set_mode(LED[GREEN],Output); + gpio_set_mode(LED[BLUE],Output); + Delay(RMIN); + os_sys_init(init); +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code.zip b/ST-DiscoveryF4/Contents/Module_12/Code.zip deleted file mode 100644 index f69609505d1b31edcfe53d0e83d264c0d26dde1e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 24348 zcmZs>V~{Ap(k(i+ZQHhuJ+^Jzwr$(CZQGvNW7~J1`|gYHJpAaajH>ABuF70hD>G7F z8W;ox00002z)9~*Y<*v3nF|sCfQlLb0RCUEvWbnowSltqRB#J50-bhw~-k(MNJ(Cb=WE;bhARzuPioh;S-lHTi| zy=7)B!>^7Ap%XY0kN9DHY)@$`3W}FRQG`!?Y`q+X$M%Bb^%!*9^x-ojVp*)oyl?hV z7U>@$yxu~e0?81F4EX$KkuiTN|GNKgliJD6yf-0{F4PbV-k43a?8d?*d5sY&P3OiLo5k7F< zsw$O3gx3%s69bM+`H;|>04KcnT*-1?%DG`2=>v$m*_9!W7bTJY_EQ#e9!qRF3ziO6 zMk0<3tQ2!%Y?kD+VCUdfrmjX7)+1=56YQ?R$FY8Z15I!U?K@s@#9|DrDdy}AgW zC`0BDCd1u%bQ73!Qh?S*uEP-_vB;_r;8ElhIxYwI>;J4AO(vs|Ria`?jO5vo%*>e^ z6(QgOe5}VOrj3?hxF^-k-V`XqdG*N7$xDlw)Kas*Afk-wH;l{YA_w8^-&Dp^c?gJ` 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zxXOWFWE+fSBq!-&pR?wvdTH=h{t`lVYE+6HVu5<{n<;{n;Zs7R!90xdJz0J6whdSY&px3!Ctv2ijn%3 zEdQkcmMigZ`u(pP?6210f336sPMP=<{ab9nZ`73FKT*p+(ZAX9ztJ+n-{`;H`9Ime znc2Tt58{8Y|FQ1hRLS2g8ToJaw>bId+JCe1e)A6$zxn@h^!|kZW;6YUU#R~H|Hsb% zCI$V5uW9~(|F0tS=Pv#>xb(YF8rL6%{?8cGpLPCrF8^HzT;YFD>3=eR>q>t!9KXh> c{-Z}#l!5-&Y5!OAiU>ybOKjcN`Pb8b0ZGTWcmMzZ diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/RTX_Conf_CM.c b/ST-DiscoveryF4/Contents/Module_12/Code/RTX_Conf_CM.c new file mode 100644 index 0000000..479a853 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/RTX_Conf_CM.c @@ -0,0 +1,205 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CONFIG.C + * Purpose: Configuration of RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 128 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 168000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 10 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_12/Code/Template.uvoptx new file mode 100644 index 0000000..2b5548e --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/Template.uvoptx @@ -0,0 +1,355 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O206 -S1 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC168000000 -TP21 -TDS8053 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$CMSIS\Flash\STM32F4xx_1024.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + RTX + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + 0 + .\drivers\setup.c + setup.c + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_12/Code/Template.uvprojx new file mode 100644 index 0000000..00f231c --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/Template.uvprojx @@ -0,0 +1,605 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + setup.c + 1 + .\drivers\setup.c + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\stm32f4xx_hal_conf.h + + + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/platform.h new file mode 100644 index 0000000..dbb30e5 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 168000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/setup.c b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/setup.c new file mode 100644 index 0000000..b0b04b8 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/setup.c @@ -0,0 +1,43 @@ +#include "stm32f4xx_hal.h" + +/* System Clock Configuration */ +/* Set up the Discovery board to operate at 168MHz (requried for Trace) */ +void SystemClock_Config(void) { + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /* Initialize the HAL Library */ + HAL_Init(); + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the + device is clocked below the maximum system frequency (see datasheet). */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/setup.h b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/setup.h new file mode 100644 index 0000000..eb7b41d --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/setup.h @@ -0,0 +1,17 @@ +/*! + * \file setup.h + * \brief Implements setup functions. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Sets up Clock configuration. + */ +#ifndef SETUP_H +#define SETUP_H + + +/*! \brief Configures the System clock. + */ +void SystemClock_Config(void); + + +#endif // SETUP_H diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/startup_stm32f4xx.s b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/startup_stm32f4xx.s new file mode 100644 index 0000000..6c50b1f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/startup_stm32f4xx.s @@ -0,0 +1,427 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f4xx.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 30-September-2011 +;* Description : STM32F4xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock and the external SRAM mounted on +;* STM324xG-EVAL board to be used as data memory (optional, +;* to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/drivers/system_stm32f4xx.c b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/system_stm32f4xx.c new file mode 100644 index 0000000..a2a0b89 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/drivers/system_stm32f4xx.c @@ -0,0 +1,553 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 30-September-2011 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F4xx devices, + * and is generated by the clock configuration tool + * stm32f4xx_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define + * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F4xx device revision | Rev A + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 168000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 168000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 8000000 + *----------------------------------------------------------------------------- + * PLL_M | 8 + *----------------------------------------------------------------------------- + * PLL_N | 336 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 7 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Main regulator output voltage | Scale1 mode + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 5 + *----------------------------------------------------------------------------- + * Prefetch Buffer | OFF + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + +#include "stm32f4xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM324xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/************************* PLL Parameters *************************************/ +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 8 +#define PLL_N 336 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 7 + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 168000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_VOS; + + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f4xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external SRAM mounted on STM324xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | + | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | + | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+ + | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 | + | | PE15 <-> FSMC_D12 | + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xaaaa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xffff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00cc0cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa828a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc3cf; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010603; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 3; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 6; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/ST-DiscoveryF4/Contents/Module_12/Code/main.c b/ST-DiscoveryF4/Contents/Module_12/Code/main.c new file mode 100644 index 0000000..d630ca3 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code/main.c @@ -0,0 +1,189 @@ + +#include +#include +#include +#include +#include + +#define COEFFICIENT_RAM_GEN 0 +#define ML 0 + +#define RMIN CLK_FREQ/120000 +#define RMAX CLK_FREQ/110000 +#define RDIV 20 +#define RAMT (RMAX-RMIN)/RDIV + +#define MAX_COUNT 100 +#define MAX_LED_NUM 4 + +#if ML +#define TRAIN_COUNT 2000 +#endif + + +OS_TID tskID_Tsk_Dispatcher; +OS_TID tskID_Tsk_LED[LED_NUM]; + +int count=0; +int end_time; + +//Statically assign the priority +int LED_priority[4]={4,3,2,1}; +//The coefficients reflect the program's preference +int LED_preference[4]={4,3,2,1}; + + +void Delay (uint32_t nCount) +{ + while(nCount--) + { + __NOP(); + } +} + +__task void Tsk_LED(void *colour){ + + while(1){ + //Turn on the LED + gpio_set(LED[(*(int *)colour)],LED_ON); + //Do some computation + Delay((int)((rand() % RDIV*RAMT + RMIN))*(LED_preference[(*(int *)colour)])); + //Turn off the LED + gpio_set(LED[(*(int *)colour)],LED_OFF); + //Do some computation + Delay((int)((rand() % RDIV*RAMT + RMIN))*(LED_preference[(*(int *)colour)])); + //Readujust self priority + os_tsk_prio_self(1); + //Give up current control section + os_tsk_pass(); + } + +} + +/*---------------------------------------------------------------------------- + The dispatcher task dispatches LED tasks + *----------------------------------------------------------------------------*/ +__task void Tsk_Dispatcher(){ + + int i; + int j; + +#if ML + int current_cycle_time; + int last_cycle_time; + int temp1[4]; + int temp2[4]; + double record_priority[4]; +#endif + + while(count=temp1[j]){ + temp2[i]++; + } + } + LED_priority[i]=temp2[i]; + temp2[i]=0; + } + } + if(count==TRAIN_COUNT){ + for(i=0;i<4;i++){ + temp2[i]=5; + for(j=0;j<4;j++){ + if(record_priority[i]>=record_priority[j]){ + temp2[i]--; + } + } + LED_priority[i]=temp2[i]; + } + } + last_cycle_time=current_cycle_time; +#endif + + //Dispatch tasks + for(i=0;i0;j--){ + os_tsk_prio (tskID_Tsk_LED[i], 10); + } + } + } + //Calculate the time to finish + end_time=os_time_get(); + //Delete tasks + for(i=0;i=temp1[j]){ + temp2[i]++; + } + } + LED_preference[i]=temp2[i]; + temp2[i]=0; + } +#endif + + + + os_tsk_prio_self(10); + tskID_Tsk_Dispatcher=os_tsk_create(Tsk_Dispatcher,9); + //Create LED tasks + for(i=0;iYN+cvt?Wmk3Cwr$&feeSvU?S1asFLUIGSefG+kt-tR zihs@-Auk0Cf&u^l00B@F`XW{n&AcTD2>{Sc0{{U3=UZhH8+&U5XA?RXS37%W_eD)D zr!`3=-{~6p1RjoZPzh~stq>)3jIjD}%BTU~{4vr20_Q?43F4sVWxHt^EXeh`q$Hhe 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b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/RTX_Conf_CM.c new file mode 100644 index 0000000..479a853 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/RTX_Conf_CM.c @@ -0,0 +1,205 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CONFIG.C + * Purpose: Configuration of RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 128 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 168000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 10 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/Template.uvoptx new file mode 100644 index 0000000..bc14542 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/Template.uvoptx @@ -0,0 +1,368 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O206 -S1 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC168000000 -TP21 -TDS8053 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$CMSIS\Flash\STM32F4xx_1024.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + RTX + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + 0 + .\drivers\setup.c + setup.c + 0 + 0 + + + 2 + 8 + 5 + 0 + 0 + 0 + 0 + .\drivers\setup.h + setup.h + 0 + 0 + + + + + src + 0 + 0 + 0 + 0 + + 3 + 9 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/Template.uvprojx new file mode 100644 index 0000000..6b520d1 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/Template.uvprojx @@ -0,0 +1,610 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + STM32F40XX + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + setup.c + 1 + .\drivers\setup.c + + + setup.h + 5 + .\drivers\setup.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\stm32f4xx_hal_conf.h + + + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/platform.h new file mode 100644 index 0000000..dbb30e5 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 168000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/setup.c b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/setup.c new file mode 100644 index 0000000..b0b04b8 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/setup.c @@ -0,0 +1,43 @@ +#include "stm32f4xx_hal.h" + +/* System Clock Configuration */ +/* Set up the Discovery board to operate at 168MHz (requried for Trace) */ +void SystemClock_Config(void) { + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /* Initialize the HAL Library */ + HAL_Init(); + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the + device is clocked below the maximum system frequency (see datasheet). */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/setup.h b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/setup.h new file mode 100644 index 0000000..eb7b41d --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/drivers/setup.h @@ -0,0 +1,17 @@ +/*! + * \file setup.h + * \brief Implements setup functions. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Sets up Clock configuration. + */ +#ifndef SETUP_H +#define SETUP_H + + +/*! \brief Configures the System clock. + */ +void SystemClock_Config(void); + + +#endif // SETUP_H diff --git a/ST-DiscoveryF4/Contents/Module_12/Code_Solution/main.c b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/main.c new file mode 100644 index 0000000..034f0aa --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_12/Code_Solution/main.c @@ -0,0 +1,185 @@ + +#include +#include +#include +#include +#include + +#define COEFFICIENT_RAM_GEN 0 +#define ML 1 + +#define RMIN CLK_FREQ/120000 +#define RMAX CLK_FREQ/110000 +#define RDIV 20 +#define RAMT (RMAX-RMIN)/RDIV + +#define MAX_COUNT 10000 +#define MAX_LED_NUM 4 + +#if ML +#define TRAIN_COUNT 2000 +#endif + +OS_TID tskID_Tsk_Dispatcher; +OS_TID tskID_Tsk_LED[LED_NUM]; + +int count=0; +int end_time; + +//Statically assign the priority +int LED_priority[4]={1,4,2,3}; +//The coefficients reflect the program's preference +int LED_preference[4]={4,3,2,1}; + + +void Delay (uint32_t nCount) +{ + while(nCount--) + { + __NOP(); + } +} + +__task void Tsk_LED(void *colour){ + + while(1){ + //Turn on the LED + gpio_set(LED[(*(int *)colour)],LED_ON); + //Do some computation + Delay((int)((rand() % RDIV*RAMT + RMIN))*(LED_preference[(*(int *)colour)])); + //Turn off the LED + gpio_set(LED[(*(int *)colour)],LED_OFF); + //Do some computation + Delay((int)((rand() % RDIV*RAMT + RMIN))*(LED_preference[(*(int *)colour)])); + //Readujust self priority + os_tsk_prio_self(1); + //Give up current control section + os_tsk_pass(); + } + +} + +/*---------------------------------------------------------------------------- + The dispatcher task dispatches LED tasks + *----------------------------------------------------------------------------*/ +__task void Tsk_Dispatcher(){ + + int i; + int j; + +#if ML + int current_cycle_time; + int last_cycle_time; + int temp1[4]; + int temp2[4]; + double record_priority[4]; +#endif + + while(count=temp1[j]){ + temp2[i]++; + } + } + LED_priority[i]=temp2[i]; + temp2[i]=0; + } + } + if(count==TRAIN_COUNT){ + for(i=0;i<4;i++){ + temp2[i]=5; + for(j=0;j<4;j++){ + if(record_priority[i]>=record_priority[j]){ + temp2[i]--; + } + } + LED_priority[i]=temp2[i]; + } + } + last_cycle_time=current_cycle_time; +#endif + + //Dispatch tasks + for(i=0;i0;j--){ + os_tsk_prio (tskID_Tsk_LED[i], 10); + } + } + } + //Calculate the time to finish + end_time=os_time_get(); + //Delete tasks + for(i=0;i=temp1[j]){ + temp2[i]++; + } + } + LED_preference[i]=temp2[i]; + temp2[i]=0; + } +#endif + + os_tsk_prio_self(10); + tskID_Tsk_Dispatcher=os_tsk_create(Tsk_Dispatcher,9); + //Create LED tasks + for(i=0;i|04yLYLz*-eo1Yu$(%4hBc={w zZIO7;-EgUFiUYAqyiAMjRcws1|v<;cV zhNF!HV8{{x7pgKJmat9NSC2+2Q$P#uq6&qXuc#?nWT{aol+Xl?*i94Yjzh<5a_YlP z$c_lX9gDly%8Y>-LW^Werg6ICKyW`;6Bi>=o!_`ChXym``>I%TuZv>W-fy^l+-FhPbfq?92Xi1W>Y?0` zgX)1bnED3`Hh1XyQoSxuYYcUN!Yh&y6sSt4TAl?VwT?5DoE=y+`$I{0^)tVZtQl6aGThzWK^6rIrD~g!AKmQ?53dd% z$~=mWTF>)c<3H~o=g)d+R35=4G{`5g7_s(`!V3JNYOXw|5sH0z;i4;kv0Q!uTuF7V zt$v4Zw0cNQABB2MV0Y*wDz0Vc_Vv!%*ys|a%Ym}CvThQ+3vVMWR^v?6Lwtosz)Q#U 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b/ST-DiscoveryF4/Contents/Module_3/Code_1/RTX_Conf_CM.c new file mode 100644 index 0000000..1975563 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/RTX_Conf_CM.c @@ -0,0 +1,205 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CONFIG.C + * Purpose: Configuration of RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 64 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 168000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 10 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_1/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_3/Code_1/Template.uvoptx new file mode 100644 index 0000000..530a6af --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/Template.uvoptx @@ -0,0 +1,395 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O8398 -S3 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC168000000 -TP21 -TDS8053 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + + + + + 0 + 0 + 13 + 1 +
134218292
+ 0 + 0 + 0 + 0 + 0 + 1 + .\main.c + + \\Template\main.c\13 + + + + + 1 + 8 + 0x200018F5 + 0 + + + + + 2 + 8 + r1 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + RTX + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_1/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_3/Code_1/Template.uvprojx new file mode 100644 index 0000000..e8038f0 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/Template.uvprojx @@ -0,0 +1,532 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/platform.h new file mode 100644 index 0000000..dbb30e5 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 168000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_1/main.c b/ST-DiscoveryF4/Contents/Module_3/Code_1/main.c new file mode 100644 index 0000000..dd6eaa9 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_1/main.c @@ -0,0 +1,48 @@ + + + +__asm void my_strcpy(const char *src, char *dst) +{ +loop + LDRB r2, [r0] ; Load byte into r2 from memory pointed to by r0 (src pointer) + ADDS r0, #1 ; Increment src pointer + STRB r2, [r1] ; Store byte in r2 into memory pointed to by (dst pointer) + ADDS r1, #1 ; Increment dst pointer + CMP r2, #0 ; Was the byte 0? + BNE loop ; If not, repeat the loop + BX lr ; Else return from subroutine +} + +__asm void my_capitalize(char *str) +{ +cap_loop + LDRB r1, [r0] ; Load byte into r1 from memory pointed to by r0 (str pointer) + CMP r1, #'a'-1 ; compare it with the character before 'a' + BLS cap_skip ; If byte is lower or same, then skip this byte + + CMP r1, #'z' ; Compare it with the 'z' character + BHI cap_skip ; If it is higher, then skip this byte + + SUBS r1,#32 ; Else subtract out difference to capitalize it + STRB r1, [r0] ; Store the capitalized byte back in memory +cap_skip + ADDS r0, r0, #1 ; Increment str pointer + CMP r1, #0 ; Was the byte 0? + BNE cap_loop ; If not, repeat the loop + BX lr ; Else return from subroutine +} +int main(void) +{ + const char a[] = "Hello world!"; + char b[20]; + + my_strcpy (a, b); + my_capitalize(b); + + while (1) + ; +} + +// *******************************ARM University Program Copyright © ARM Ltd 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z9?Co=sCoiouUrBu?(3Nt*$b0}ecRR|4#R5me%+zwKF5nc6VZ<5mz&~Ap1|wt&m@z& zN5Vas+(sPGqq?pTVSnTgV*mt9T{wZfU3~>m{7nThTJ*TUT8Qvw4qo4|{0C=j!mF#DHzP>oH)I)c+G zn*kfyT}Jde+vgWi0|bovFWUK^nf$MR`CkX(|5X1C-T!U;&y4~9G}=>H?}H-z?|SMpDU)88_DUj**Izs&#ePXB58PyEf_rt4p<)W1#t7mf3u z3jdT1{2ztC%D6A2``-%xl^gtTjsM;;`dg!#;GZ=9wSOcl3HF7J0|3xpkHjyx$J77y G>i+>&C&cam diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/RTX_Conf_CM.c b/ST-DiscoveryF4/Contents/Module_3/Code_2/RTX_Conf_CM.c new file mode 100644 index 0000000..1975563 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/RTX_Conf_CM.c @@ -0,0 +1,205 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CONFIG.C + * Purpose: Configuration of RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 64 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 168000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 10 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_3/Code_2/Template.uvoptx new file mode 100644 index 0000000..d49d714 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/Template.uvoptx @@ -0,0 +1,374 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/Keil/MCBSTM32F400/Documentation/mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/Keil/MCBSTM32F400/Documentation/mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O8398 -S3 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC168000000 -TP21 -TDS8053 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + + + + + + 1 + 0 + SP + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + OS Support\Event Viewer + 35905 + + + OS Support\System and Thread Viewer + 35904 + + + + + + + RTX + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_3/Code_2/Template.uvprojx new file mode 100644 index 0000000..55b497a --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/Template.uvprojx @@ -0,0 +1,543 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/platform.h new file mode 100644 index 0000000..dbb30e5 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 168000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2/main.c b/ST-DiscoveryF4/Contents/Module_3/Code_2/main.c new file mode 100644 index 0000000..94caab4 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2/main.c @@ -0,0 +1,43 @@ + + +#include +#include + + +/*Modified the function to a task*/ +void Turn_GreenLed_On(void){ + + for(;;){ + gpio_set(LED[GREEN],LED_ON); + } + +} + +/*Modified the function to a task*/ +void Turn_GreenLed_Off(void){ + + for(;;){ + gpio_set(LED[GREEN],LED_OFF); + } + +} + +/*---------------------------------------------------------------------------- + The first task run by the OS and should do the initialization for other tasks + *----------------------------------------------------------------------------*/ +__task void init (void) { + + /*Create Tasks here*/ + os_tsk_delete_self (); // Delete the init(self) task +} + +int main(void) +{ + gpio_set_mode(LED[GREEN],Output); + gpio_set_mode(LED[RED],Output); + gpio_set(LED[RED],LED_ON); + os_sys_init(init); + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution.zip b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution.zip deleted file mode 100644 index 26b141ef6e2670cbd0408439f48394c2497fb7a0..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13049 zcma*O19)spxAz;{EA~oOY$q$WjTPIr?PSGv(y?vZwr$(EYrp5*XTRUM`@G+s{q(HS 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zGCJVnc|)e?yxnq4s9kQL=#>)rYUy2)sJcU@&wkt}8@~6USC>}CLPt7E3tF%Ib%1ft zg38}UHuNi&q=$d@^s>3&aAC3~dkF1}Tum@!>k41NS?gpV?)b~W6%ZW#nhYygeG;MN zr993#y`8i0rqBPuz?gu=Z$?y$vwy!Ixsftm#p%5Djv*%r41x;uzsvsr{O|vBApKYI zA2tE}zm$L82Jn|V@V_PzSpQi6+g5^qZ3_6iLQp{er1Jh7mHTI(!GA)T{yXZQ#La)B z9{*^{{x{TrNuB?l^-n_Dzgdgm{}9;`qWYWX{73ft zKfmXHNvi&x@lTqazZsGU|6j)cq2T#<)IY5s{uk=6Gt3`}*Z-`}|5#1@pRoTqDfKrD fgz!JY{xwA + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 64 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 168000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 1000 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/Template.uvoptx new file mode 100644 index 0000000..d07f9e7 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/Template.uvoptx @@ -0,0 +1,369 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/Keil/MCBSTM32F400/Documentation/mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/Keil/MCBSTM32F400/Documentation/mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK/Boards/ST/STM32F4-Discovery/Documentation/stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U303030303030303030303031 -O8398 -S3 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC168000000 -TP21 -TDS8053 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + + + + + + 1 + 0 + SP + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + RTX + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/Template.uvprojx new file mode 100644 index 0000000..6a83891 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/Template.uvprojx @@ -0,0 +1,543 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + STM32F40XX + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/platform.h new file mode 100644 index 0000000..dbb30e5 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 168000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/main.c b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/main.c new file mode 100644 index 0000000..d99cace --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_3/Code_2_Solution/main.c @@ -0,0 +1,49 @@ + + +#include +#include + +OS_TID taskID1; +OS_TID taskID2; + +/*Modified the function to a task*/ +__task void Turn_GreenLed_On(void){ + + for(;;){ + gpio_set(LED[GREEN],LED_ON); + //os_tsk_pass (); + } + +} + +/*Modified the function to a task*/ +__task void Turn_GreenLed_Off(void){ + + for(;;){ + gpio_set(LED[GREEN],LED_OFF); + //os_tsk_pass (); + } + +} + +/*---------------------------------------------------------------------------- + The first task run by the OS and should do the initialization for other tasks + *----------------------------------------------------------------------------*/ +__task void init (void) { + + taskID1 = os_tsk_create( Turn_GreenLed_On, 0); + taskID2 = os_tsk_create( Turn_GreenLed_Off, 0); + + os_tsk_delete_self (); // Delete the init(self) task +} + +int main(void) +{ + gpio_set_mode(LED[GREEN],Output); + gpio_set_mode(LED[RED],Output); + gpio_set(LED[RED],LED_ON); + os_sys_init(init); + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_5/Code.zip b/ST-DiscoveryF4/Contents/Module_5/Code.zip deleted file mode 100644 index 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z9l-&^7K6ML2q+rh|G(Mbk8J`#0EB-ve_sE!_28fAzm-1z1^frC__KTAe-%Rh6aKda z@c+Pn{r-6f_fPo$E{Fe<{?h6N?BDU>pV$63=kqr|_or(0Kdwk#3gR!n S1c3ST#`@!^tQi0L_kRF}F*xV| diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/RTX_Conf_CM.c b/ST-DiscoveryF4/Contents/Module_5/Code/RTX_Conf_CM.c new file mode 100644 index 0000000..1975563 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/RTX_Conf_CM.c @@ -0,0 +1,205 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CONFIG.C + * Purpose: Configuration of RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 64 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 168000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 10 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_5/Code/Template.uvoptx new file mode 100644 index 0000000..813128f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/Template.uvoptx @@ -0,0 +1,375 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U49FF6F066670534844360167 -O8398 -S6 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC168000000 -TP21 -TDS8053 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + + + + + + 1 + 0 + SP + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + OS Support\Event Viewer + 35905 + + + OS Support\System and Thread Viewer + 35904 + + + + + + + RTX + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_5/Code/Template.uvprojx new file mode 100644 index 0000000..045b13b --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/Template.uvprojx @@ -0,0 +1,547 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + STM32F40XX + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/platform.h new file mode 100644 index 0000000..dbb30e5 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 168000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_5/Code/main.c b/ST-DiscoveryF4/Contents/Module_5/Code/main.c new file mode 100644 index 0000000..7792b24 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code/main.c @@ -0,0 +1,86 @@ + + +#include +#include +#include + +#define RMIN CLK_FREQ/20 +#define RMAX CLK_FREQ/10 +#define RDIV 5 +#define RAMT (RMAX-RMIN)/RDIV + +OS_TID taskID0; +OS_TID taskID1; + +void Delay (uint32_t nCount) +{ + while(nCount--) + { + __NOP(); + } +} + +void Access(int colour){ + gpio_set(LED[colour],LED_ON); +} + +void Release(int colour){ + gpio_set(LED[colour],LED_OFF); +} + +int Check(int colour){ + return gpio_get(LED[colour]); +} + + + +__task void Task0(void){ + + /*Critical section starts from here*/ + gpio_set(LED[BLUE],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[BLUE],LED_OFF); + /*Critical section ends here*/ + + os_tsk_delete_self (); +} + +__task void Task1(void){ + + /*Critical section starts from here*/ + gpio_set(LED[GREEN],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[GREEN],LED_OFF); + /*Critical section ends here*/ + + os_tsk_delete_self (); +} + + +/*---------------------------------------------------------------------------- + The first task run by the OS and should do the initialization for other tasks + *----------------------------------------------------------------------------*/ +__task void init (void) { + + taskID0 = os_tsk_create( Task0, 0); + //taskID1 = os_tsk_create( Task1, 0); + + os_tsk_delete_self (); // Delete the init(self) task +} + +int main(void) +{ + + gpio_set_mode(LED[RED],Output); + gpio_set_mode(LED[GREEN],Output); + gpio_set_mode(LED[BLUE],Output); + Delay(RMIN); + os_sys_init(init); + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution.zip b/ST-DiscoveryF4/Contents/Module_5/Code_Solution.zip deleted file mode 100644 index ef18066cee4534cdb36e3832b59b95545bdb99b2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13306 zcmZ{r19T=!*Y9K7wkOVHV%xTDb7I?1Y)+hsZ992_iEU?M=g#@wyY4yfx6bWe-MhMa z{Z_A4RbBtRYwc2$0f)c<0Re#lsa5?gu2IfW90Uyl!iEO|g7~LaSyj_O#KGR&Ktztw zq)GG4VO0|4(qWO$qElYZ!Vw|mNb-iDU;%}DdT z&fahObWdIoiFSnR&y;H6ImSC2I>T3DE}a1yv?f>s*4BMCv&z^Mmd69@qNjfNf?d^u zMaxE;YVlhfMyLUqkPlUm=X|ELFFLmLocF%7BjAekhNp3DzZ9C!%RcVL=BZ~|9p7N= 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z%(*)4;0W`)Q@aYtyQ4M_N(CB}@wUYft&jx6|1-ep_*i7+DnpP-i8m6w={S*0}z$)w!X>abZG4b5ZBi zx_F8#&WRt`MIjs1wl2P-YQI8cQohk!IEWXWz)s&I%VG_GF=~gYdTAufC z@8NqA?=VFuPO4wW4Z7?y7T|CFgvo_Q=nhoGWhK^5eLoD~a2wlO@&{Fv0R_VV`Ty_c z_%kbjfP#?xW&RxhwYTG+=)dKb{ssI|j6X;9pY0+4E7SCU!~Z+=;4kby@C53A!T*zp z@K5^R7B2onll(Cgr2idin*0;}x486gl$zqdQOkd#{}zt@joMKDjs7P%`zQNvuK(XG z5B2|I|LeQ|rp14=hhP3?|5oOIe*531{lEE+KWV}L5dlRR$iEZ;1oqE~^JhtDlI5?b F{{u4Y^p*es diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/RTX_Conf_CM.c b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/RTX_Conf_CM.c new file mode 100644 index 0000000..1975563 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/RTX_Conf_CM.c @@ -0,0 +1,205 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CONFIG.C + * Purpose: Configuration of RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Task Configuration +// ===================== +// +// Number of concurrent running tasks <0-250> +// Define max. number of tasks that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 10 +#endif + +// Number of tasks with user-provided stack <0-250> +// Define the number of tasks that will use a bigger stack. +// The memory space for the stack is provided by the user. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Task stack size [bytes] <20-4096:8><#/4> +// Set the stack size for tasks which is assigned by the system. +// Default: 512 +#ifndef OS_STKSIZE + #define OS_STKSIZE 64 +#endif + +// Check for the stack overflow +// =============================== +// Include the stack checking code for a stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Run in privileged mode +// ========================= +// Run all Tasks in privileged mode. +// Default: Unprivileged +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// +// Tick Timer Configuration +// ============================= +// Hardware timer <0=> Core SysTick <1=> Peripheral Timer +// Define the on-chip timer used as a time-base for RTX. +// Default: Core SysTick +#ifndef OS_TIMER + #define OS_TIMER 0 +#endif + +// Timer clock value [Hz] <1-1000000000> +// Set the timer clock value for selected timer. +// Default: 6000000 (6MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 168000000 +#endif + +// Timer tick value [us] <1-1000000> +// Set the timer tick value for selected timer. +// Default: 10000 (10ms) +#ifndef OS_TICK + #define OS_TICK 10 +#endif + +// + +// System Configuration +// ======================= +// Round-Robin Task switching +// ============================= +// Enable Round-Robin Task switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Define how long a task will execute before a task switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// Number of user timers <0-250> +// Define max. number of user timers that will run at the same time. +// Default: 0 (User timers disabled) +#ifndef OS_TIMERCNT + #define OS_TIMERCNT 0 +#endif + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the iterrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +__task void os_idle_demon (void) { + /* The idle demon is a system task, running when no other task is ready */ + /* to run. The 'os_xxx' function calls are not allowed from this task. */ + + for (;;) { + /* HERE: include optional user code to be executed when no task runs.*/ + } +} + +/*--------------------------- os_tick_init ----------------------------------*/ + +#if (OS_TIMER != 0) +int os_tick_init (void) { + /* Initialize hardware timer as system tick timer. */ + /* ... */ + return (-1); /* Return IRQ number of timer (0..239) */ +} +#endif + +/*--------------------------- os_tick_irqack --------------------------------*/ + +#if (OS_TIMER != 0) +void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ + /* ... */ +} +#endif + +/*--------------------------- os_tmr_call -----------------------------------*/ + +void os_tmr_call (U16 info) { + /* This function is called when the user timer has expired. Parameter */ + /* 'info' holds the value, defined when the timer was created. */ + while(1){} + /* HERE: include optional user code to be executed on timeout. */ +} + + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (U32 err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/Template.uvoptx b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/Template.uvoptx new file mode 100644 index 0000000..eb5c3e4 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/Template.uvoptx @@ -0,0 +1,375 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + STM32F4Discovery + 0x4 + ARM-ADS + + 168000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + + 0 + User Manual (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f200.chm + + + 1 + Schematics (MCBSTM32F400) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\Keil\MCBSTM32F400\Documentation\mcbstm32f400-schematics.pdf + + + 2 + Getting Started (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00037368.pdf + + + 3 + User Manual (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\DM00039084.pdf + + + 4 + Bill of Materials (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_bom.zip + + + 5 + Gerber Files (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_gerber.zip + + + 6 + Schematics (STM32F4-Discovery) + C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.5.0\MDK\Boards\ST\STM32F4-Discovery\Documentation\stm32f4discovery_sch.zip + + + 7 + MCBSTM32F400 Evaluation Board Web Page (MCBSTM32F400) + http://www.keil.com/mcbstm32f400/ + + + 8 + STM32F4-Discovery Web Page (STM32F4-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF252419 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U-O8398 -O8398 -S3 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC168000000 -TP21 -TDS8053 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + + + + + + 1 + 0 + SP + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + OS Support\Event Viewer + 35905 + + + OS Support\System and Thread Viewer + 35904 + + + + + + + RTX + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + .\RTX_Conf_CM.c + RTX_Conf_CM.c + 0 + 0 + + + + + drivers + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + 0 + .\drivers\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + .\drivers\adc.h + adc.h + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + 0 + .\drivers\gpio.c + gpio.c + 0 + 0 + + + 2 + 5 + 5 + 0 + 0 + 0 + 0 + .\drivers\gpio.h + gpio.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 + 0 + 0 + .\drivers\platform.h + platform.h + 0 + 0 + + + + + src + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/Template.uvprojx b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/Template.uvprojx new file mode 100644 index 0000000..045b13b --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/Template.uvprojx @@ -0,0 +1,547 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + STM32F4Discovery + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + Keil.STM32F4xx_DFP.2.5.0 + http://www.keil.com/pack + IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(168000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$Flash\STM32F4xx_1024.FLM)) + 6103 + $$Device:STM32F407VG$Device\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VG$SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + Template + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + STM32F40XX + + C:\Keil_v5\ARM\RV31\INC;.\drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + RTX + + + RTX_Conf_CM.c + 1 + .\RTX_Conf_CM.c + + + + + drivers + + + adc.c + 1 + .\drivers\adc.c + + + adc.h + 5 + .\drivers\adc.h + + + gpio.c + 1 + .\drivers\gpio.c + + + gpio.h + 5 + .\drivers\gpio.h + + + platform.h + 5 + .\drivers\platform.h + + + + + src + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\MKL25Z128xxx4\startup_MKL25Z4.s + + + + + + RTE\Device\MKL25Z128xxx4\system_MKL25Z4.c + + + + + + RTE\Device\STM32F407VG\RTE_Device.h + + + + + + RTE\Device\STM32F407VG\startup_stm32f407xx.s + + + + + + + + RTE\Device\STM32F407VG\startup_stm32f40_41xxx.s + + + + + + RTE\Device\STM32F407VG\system_stm32f4xx.c + + + + + + + + + + diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/adc.c b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/adc.c new file mode 100644 index 0000000..1a1f91f --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/adc.c @@ -0,0 +1,44 @@ +#include +#include + +void adc_init(void) { + + //Enable the clock for ADC module and GPIO Port A + RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN; + RCC->APB2ENR|=RCC_APB2ENR_ADC1EN; + + //Configure the Port A pin 1 to be the Analogue Mode + GPIOA->MODER|=GPIO_MODER_MODER1; + GPIOA->PUPDR&=~(GPIO_PUPDR_PUPDR1); + + //Set the prescaler for the clock + RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; + + //Set ADC prescaler, divided by 2 + ADC->CCR|=ADC_CCR_ADCPRE_0; + + //Power up the ADC module + ADC1->CR2|=ADC_CR2_ADON; + + //480 cycles, better accuracy than 3 cycles + ADC1->SMPR1|=ADC_SMPR1_SMP16; + + //Select channel 1 as input + MODIFY_REG(ADC1->SQR3, ADC_SQR3_SQ1, ADC_SQR3_SQ1_0); + +} + +int adc_read(void) { + + //Software trigger the conversion + ADC1->CR2|=ADC_CR2_SWSTART; + + //Wait for the completion of the conversion + while(!(ADC1->SR&(1UL<<1))){} + + //Return the reading value + return ADC1->DR; + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/adc.h b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/adc.h new file mode 100644 index 0000000..e7e1733 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/adc.h @@ -0,0 +1,19 @@ +/*! + * \file adc.h + * \brief Internal analogue to digital converter (ADC) controller. + * \copyright ARM University Program © ARM Ltd 2014. + */ +#ifndef ADC_H +#define ADC_H + +/*! \brief Initializes the analogue to digital converter, and configures + * the appropriate GPIO pin. + */ +void adc_init(void); + +/*! \brief Reads the current value of the ADC. + * \return Potential of the pin, relative to ground. + */ +int adc_read(void); + +#endif // ADC_H diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/gpio.c b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/gpio.c new file mode 100644 index 0000000..a4c7746 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/gpio.c @@ -0,0 +1,59 @@ +#include +#include + +void gpio_toggle(Pin pin) { +} + +void gpio_set(Pin pin, int value) { + + GPIO_TypeDef* p = GET_PORT(pin); + uint32_t pin_index = GET_PIN_INDEX(pin); + + MODIFY_REG(p->ODR,1UL<IDR,(1<AHB1ENR|=1UL<MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Input: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case Output: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + break; + case PullUp: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 1UL<<((pin_index)*2)); + break; + case PullDown: + MODIFY_REG(p->MODER, 11UL<<((pin_index)*2), 0UL<<((pin_index)*2)); + MODIFY_REG(p->PUPDR, 11UL<<((pin_index)*2), 10UL<<((pin_index)*2)); + break; + } + +} + + + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/gpio.h b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/gpio.h new file mode 100644 index 0000000..ec13490 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/gpio.h @@ -0,0 +1,98 @@ +/*! + * \file gpio.h + * \brief Implements general purpose I/O. + * \copyright ARM University Program © ARM Ltd 2014. + * + * Exposes generic pin input / output controls. + * Use for any direct pin manipulation. + */ +#ifndef PINS_H +#define PINS_H + +#include + +/*! This enum describes the directional setup of a GPIO pin. */ +typedef enum { + Reset, //!< Resets the pin-mode to the default value. + Input, //!< Sets the pin as an input with no pull-up or pull-down. + Output, //!< Sets the pin as a low impedance output. + PullUp, //!< Enables the internal pull-up resistor. + PullDown //!< Enables the internal pull-down resistor. +} PinMode; + +/*! Defines the triggering mode of an interrupt. */ +typedef enum { + None, //!< Disables the interrupt. + Rising, //!< Enables an interrupt on the falling edge. + Falling //!< Enables an interrupt on the rising edge. +} TriggerMode; + +/*! \brief Toggles a GPIO pin's output. + * A pin which is currently high is set low + * and a pin which is currently low is set high. + * \param pin Pin to toggle. + */ +void gpio_toggle(Pin pin); + +/*! \brief Sets a pin to the specified logic level. + * \param pin Pin to set. + * \param value New logic level of the pin (0 is low, otherwise high). + */ +void gpio_set(Pin pin, int value); + +/*! \brief Get the current logic level of a GPIO pin. + * If the pin is high, this function will return a 1, + * else it will return 0. + * \param pin Pin to read. + * \return The logic level of the GPIO pin (0 if low, 1 if high). + */ +int gpio_get(Pin pin); + +/*! \brief Sets a range of sequential pins to the specified value. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \param value New value of the pins. + */ +void gpio_set_range(Pin pin_base, int count, int value); + +/*! \brief Returns the value of a range of sequential pins. + * \param pin_base Starting pin. + * \param count Number of pins to set. + * \returns Value of the pins. + */ +unsigned int gpio_get_range(Pin pin_base, int count); + +/*! \brief Configures the output mode of a GPIO pin. + * + * Used to set the GPIO as an input, output, and configure the + * possible pull-up or pull-down resistors. + * + * \param pin Pin to set. + * \param mode New output mode of the pin. + */ +void gpio_set_mode(Pin pin, PinMode mode); + +/*! \brief Configures the event which will cause an interrupt + * on a specified pin. + * + * \param pin Pin to trigger off. + * \param trig New triggering mode for the pin. + */ +void gpio_set_trigger(Pin pin, TriggerMode trig); + +/*! \brief Passes a callback function to the api which is called + * during the port's relevant interrupt. + * + * \warning The pin argument specifies the port which will be + * interrupted on, not an individual pin. It is advised + * check the \a status variable to determine which pin + * caused the interrupt. + * + * \sa gpio_set_trigger to configure and enable the interrupt. + * + * \param pin Pin which specifies the port to use. + * \param callback Callback function. + */ +void gpio_set_callback(Pin pin, void (*callback)(int status)); + +#endif // PINS_H diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/platform.h b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/platform.h new file mode 100644 index 0000000..dbb30e5 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/drivers/platform.h @@ -0,0 +1,37 @@ +#ifndef PLATFORM_H +#define PLATFORM_H + +#include + +typedef enum { + PA0 = (0 << 16) | 0,//User Switch + PA1 = (0 << 16) | 1,//ADC1 + PD12 = (3 << 16) | 12,//Green LED + PD13 = (3 << 16) | 13,//Orange LED + PD14 = (3 << 16) | 14,//Red LED + PD15 = (3 << 16) | 15,//Blue LED +} Pin; + +#define LED_NUM 4 + +#define LED_ON 1 +#define LED_OFF 0 + +static Pin LED[LED_NUM]={PD12,PD13,PD14,PD15}; +static Pin SWITCH = PA0; + +#define RED 2 +#define GREEN 0 +#define BLUE 3 +#define ORANGE 1 + +#define CLK_FREQ 168000000UL + +#define GET_PORT_INDEX(pin) ((pin) >> 16) +#define GET_PIN_INDEX(pin) ((pin) & 0xFF) + +#define GET_PORT(pin) ((GPIO_TypeDef*)(AHB1PERIPH_BASE + 0x0400 * GET_PORT_INDEX(pin))) + +#endif + +// *******************************ARM University Program Copyright © ARM Ltd 2014************************************* diff --git a/ST-DiscoveryF4/Contents/Module_5/Code_Solution/main.c b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/main.c new file mode 100644 index 0000000..95e1344 --- /dev/null +++ b/ST-DiscoveryF4/Contents/Module_5/Code_Solution/main.c @@ -0,0 +1,282 @@ + + +#include +#include +#include + +#define RMIN CLK_FREQ/20 +#define RMAX CLK_FREQ/10 +#define RDIV 5 +#define RAMT (RMAX-RMIN)/RDIV + + +OS_TID taskID0; +OS_TID taskID1; + +int token = 0 ; +int flag[2] = {0,0} ; + +void Delay (uint32_t nCount) +{ + while(nCount--) + { + __NOP(); + } +} + +void Access(int colour){ + gpio_set(LED[colour],LED_ON); +} + +void Release(int colour){ + gpio_set(LED[colour],LED_OFF); +} + +int Check(int colour){ + return gpio_get(LED[colour]); +} + + + + +__task void Task0(void){ + + + /*Critical section starts from here*/ + gpio_set(LED[BLUE],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[BLUE],LED_OFF); + /*Critical section ends here*/ + + + os_tsk_delete_self (); +} + +__task void Task1(void){ + + + /*Critical section starts from here*/ + gpio_set(LED[GREEN],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[GREEN],LED_OFF); + /*Critical section ends here*/ + + + os_tsk_delete_self (); +} + +//First Scheme +__task void Task0_1(void){ + + while(Check(RED)){} + //Delay(rand() % RDIV*RAMT + RMIN); + /*Critical section starts from here*/ + gpio_set(LED[BLUE],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[BLUE],LED_OFF); + /*Critical section ends here*/ + + os_tsk_delete_self (); +} + +__task void Task1_1(void){ + + while(Check(RED)){} + //Delay(rand() % RDIV*RAMT + RMIN); + /*Critical section starts from here*/ + gpio_set(LED[GREEN],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[GREEN],LED_OFF); + /*Critical section ends here*/ + + os_tsk_delete_self (); +} + +//Second Scheme +__task void Task0_2(void){ + + + while(token!=0){} + /*Critical section starts from here*/ + gpio_set(LED[BLUE],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[BLUE],LED_OFF); + /*Critical section ends here*/ + token=1-token; + + os_tsk_delete_self (); +} + +__task void Task1_2(void){ + + while(token!=1){} + /*Critical section starts from here*/ + gpio_set(LED[GREEN],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[GREEN],LED_OFF); + /*Critical section ends here*/ + token=1-token; + + os_tsk_delete_self (); +} + +//Third Scheme +__task void Task0_3(void){ + + flag[0]=1; + Delay(rand() % RDIV*RAMT + RMIN); + while(flag[1]){} + /*Critical section starts from here*/ + gpio_set(LED[BLUE],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[BLUE],LED_OFF); + /*Critical section ends here*/ + flag[0]=0; + + os_tsk_delete_self (); +} + +__task void Task1_3(void){ + + flag[1]=1; + Delay(rand() % RDIV*RAMT + RMIN); + while(flag[0]){} + /*Critical section starts from here*/ + gpio_set(LED[GREEN],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[GREEN],LED_OFF); + /*Critical section ends here*/ + flag[1]=0; + + os_tsk_delete_self (); +} + +//Fourth Scheme +__task void Task0_4(void){ + + flag[0]=1; + Delay(rand() % RDIV*RAMT + RMIN); + while(flag[1]){ + Delay(rand() % RDIV*RAMT + RMIN); + flag[0]=0; + Delay(500); + flag[0]=1; + } + /*Critical section starts from here*/ + gpio_set(LED[BLUE],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[BLUE],LED_OFF); + /*Critical section ends here*/ + flag[0]=0; + + os_tsk_delete_self (); +} + +__task void Task1_4(void){ + + flag[1]=1; + Delay(rand() % RDIV*RAMT + RMIN); + while(flag[0]){ + Delay(rand() % RDIV*RAMT + RMIN); + flag[1]=0; + Delay(500); + flag[1]=1; + } + /*Critical section starts from here*/ + gpio_set(LED[GREEN],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[GREEN],LED_OFF); + /*Critical section ends here*/ + flag[1]=0; + + os_tsk_delete_self (); +} + +//Dekker's Algorithm +__task void Task0_5(void){ + + flag[0]=1; + while(flag[1]){ + if(token==1){ + flag[0]=0; + while(token==1){} + flag[0]=1; + } + } + /*Critical section starts from here*/ + gpio_set(LED[BLUE],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[BLUE],LED_OFF); + /*Critical section ends here*/ + token=1-token; + flag[0]=0; + + os_tsk_delete_self (); +} + +__task void Task1_5(void){ + + flag[1]=1; + while(flag[0]){ + if(token==0){ + flag[1]=0; + while(token==1){} + flag[1]=1; + } + + } + /*Critical section starts from here*/ + gpio_set(LED[GREEN],LED_ON); + Access(RED); + Delay(rand() % RDIV*RAMT + RMIN); + Release(RED); + gpio_set(LED[GREEN],LED_OFF); + /*Critical section ends here*/ + flag[1]=0; + + os_tsk_delete_self (); +} + +/*---------------------------------------------------------------------------- + The first task run by the OS and should do the initialization for other tasks + *----------------------------------------------------------------------------*/ +__task void init (void) { + //Taskx_y is the xth scheme for task x + taskID0 = os_tsk_create(Task0_5, 0); + taskID1 = os_tsk_create(Task1_5, 0); + os_tsk_delete_self (); // Delete the init(self) task +} + +int main(void) +{ + gpio_set_mode(LED[RED],Output); + gpio_set_mode(LED[GREEN],Output); + gpio_set_mode(LED[BLUE],Output); + Delay(RMIN); + os_sys_init(init); + +} + +// *******************************ARM University Program Copyright © ARM Ltd 2014*************************************