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main.bgn
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Release 14.3 - Bitgen P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45.nph' in environment
C:\Xilinx\14.3\ISE_DS\ISE\.
"main" is an NCD, version 3.2, device xc6slx45, package fgg484, speed -2
Opened constraints file main.pcf.
Tue Dec 16 02:33:38 2014
C:\Xilinx\14.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 main.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 2** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | Yes |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| multipin_wakeup | No** |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No** |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| CrcCoverage | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| next_config_reboot | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | 0xFFFF |
+----------------------+----------------------+
| spi_buswidth | 1** |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 1 CONFIG constraint(s) processed from main.pcf.
CONFIG VCCAUX = "3.3"
Running DRC.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm> and
DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm> found no
EXTERN driver in CLKFB path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm> found
non-EXTERN block <BUFG> in CLKFB path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm> found NO
extern
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep46trigin<0> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<0> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<11> is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep46trigin<5> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<9> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<13> is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep46trigin<3> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<1> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<3> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<5> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<7> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<host/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_RAMD_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<host/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_RAMD_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[5].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[6].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[7].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[8].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[9].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[10].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[0].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[11].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[1].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[12].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[2].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[3].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[4].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
DRC detected 0 errors and 26 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "main.bit".
Bitstream generation is complete.