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main.bld
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Release 14.3 ngdbuild P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\14.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc xem6010.ucf -p xc6slx45-fgg484-2
main.ngc main.ngd
Reading NGO file
"C:/Users/jvoigts/Downloads/RHD2000InterfaceXEM6010_release_140226/RHD2000Interf
aceXEM6010/main.ngc" ...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/okWireOut.ngc"...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/okWireIn.ngc"...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/okTriggerIn.ngc"...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/okPipeOut.ngc"...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/okCoreHarness.ngc"...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/TFIFO64x8a_64x8b.ngc"...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/fifo_w16_2048_r64_512.ngc"...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/fifo_w64_512_r16_2048.ngc"...
Loading design module
"C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000Interf
aceXEM6010/multiplier_18x18.ngc"...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "xem6010.ucf" ...
WARNING:NgdBuild - The value of SIM_DEVICE on instance
'SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv' of type PLL_ADV has
been changed from 'VIRTEX5' to 'SPARTAN6' to correct post-ngdbuild and timing
simulation for this primitive. In order for functional simulation to be
correct, the value of SIM_DEVICE should be changed in this same manner in the
source netlist or constraint file.
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:178 - TNM 'okHostClk', used in period specification
'TS_okHostClk', was traced into DCM_SP instance host/hi_dcm. The following
new TNM groups and period specifications were generated at the DCM_SP
output(s):
CLK0: <TIMESPEC TS_host_dcm_clk0 = PERIOD "host_dcm_clk0" TS_okHostClk HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'SYS_CLK3', used in period specification
'TS_SYS_CLK3', was traced into PLL_ADV instance
SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv. The following new TNM
groups and period specifications were generated at the PLL_ADV output(s):
CLKOUT3: <TIMESPEC
TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD
"SDRAM_FIFO_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in" TS_SYS_CLK3 /
0.78125 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'SYS_CLK3', used in period specification
'TS_SYS_CLK3', was traced into PLL_ADV instance
SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv. The following new TNM
groups and period specifications were generated at the PLL_ADV output(s):
CLKOUT1: <TIMESPEC TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_180 =
PERIOD "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_180" TS_SYS_CLK3 /
6.25 PHASE 0.8 ns HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'SYS_CLK3', used in period specification
'TS_SYS_CLK3', was traced into PLL_ADV instance
SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv. The following new TNM
groups and period specifications were generated at the PLL_ADV output(s):
CLKOUT0: <TIMESPEC TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_0 =
PERIOD "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_0" TS_SYS_CLK3 /
6.25 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'SYS_CLK3', used in period specification
'TS_SYS_CLK3', was traced into PLL_ADV instance
SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv. The following new TNM
groups and period specifications were generated at the PLL_ADV output(s):
CLKOUT2: <TIMESPEC TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk0_bufg_in
= PERIOD "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk0_bufg_in" TS_SYS_CLK3
/ 1.5625 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'SYS_CLK3', used in period specification
'TS_SYS_CLK3', was traced into DCM_CLKGEN instance
variable_freq_clk_generator_inst/DCM_CLKGEN_1. The following new TNM groups
and period specifications were generated at the DCM_CLKGEN output(s):
CLKFXDV: <TIMESPEC TS_variable_freq_clk_generator_inst_clkout_i = PERIOD
"variable_freq_clk_generator_inst_clkout_i" TS_SYS_CLK3 / 0.84 HIGH 50%>
Done...
INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
host/hi_dcm to 20.830000 ns based on the period specification (<TIMESPEC
"TS_okHostClk" = PERIOD "okHostClk" 20.83 ns HIGH 50%;> [xem6010.ucf(48)]).
INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
variable_freq_clk_generator_inst/DCM_CLKGEN_1 to 10.000000 ns based on the
period specification (<TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 10 ns
HIGH 50 %;> [xem6010.ucf(131)]).
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive 'host/core0/core0/a0/pc0/read_strobe_flop'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'host/core0/core0/a0/pc0/k_write_strobe_flop' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive 'host/core0/core0/a0/pc0/interrupt_ack_flop'
has unconnected output pin
WARNING:NgdBuild:452 - logical net 'N981' has no driver
WARNING:NgdBuild:452 - logical net 'N985' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 6
Total memory usage is 221672 kilobytes
Writing NGD file "main.ngd" ...
Total REAL time to NGDBUILD completion: 8 sec
Total CPU time to NGDBUILD completion: 8 sec
Writing NGDBUILD log file "main.bld"...