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main.syr
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main.syr
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Release 14.3 - xst P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
--> Reading design: main.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "main.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "main"
Output Format : NGC
Target Device : xc6slx45-2-fgg484
---- Source Options
Top Module Name : main
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\iodrp_mcb_controller.v" into library work
Parsing module <iodrp_mcb_controller>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\iodrp_controller.v" into library work
Parsing module <iodrp_controller>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" into library work
Parsing module <mcb_soft_calibration>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration_top.v" into library work
Parsing module <mcb_soft_calibration_top>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_raw_wrapper.v" into library work
Parsing module <mcb_raw_wrapper>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\RAM_block.v" into library work
Parsing module <RAM_1024x16bit>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\multiplier_18x18.v" into library work
Parsing module <multiplier_18x18>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_wrapper.v" into library work
Parsing module <memc3_wrapper>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_infrastructure.v" into library work
Parsing module <memc3_infrastructure>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\fifo_w64_512_r16_2048.v" into library work
Parsing module <fifo_w64_512_r16_2048>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\fifo_w16_2048_r64_512.v" into library work
Parsing module <fifo_w16_2048_r64_512>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\ddr2_state_machine.v" into library work
Parsing module <ddr2_state_machine>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\variable_freq_clk_generator.v" into library work
Parsing module <variable_freq_clk_generator>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" into library work
Parsing module <SDRAM_FIFO>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\RAM_bank.v" into library work
Parsing module <RAM_bank>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\okLibrary.v" into library work
Parsing module <okHost>.
Parsing module <okCoreHarness>.
Parsing module <okWireIn>.
Parsing module <okWireOut>.
Parsing module <okTriggerIn>.
Parsing module <okTriggerOut>.
Parsing module <okPipeIn>.
Parsing module <okPipeOut>.
Parsing module <okBTPipeIn>.
Parsing module <okBTPipeOut>.
Parsing module <okWireOR>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\MISO_phase_selector.v" into library work
Parsing module <MISO_phase_selector>.
Parsing module <MISO_DDR_phase_selector>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\LED_controller.v" into library work
Parsing module <LED_controller>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\DAC_output_scalable_HPF.v" into library work
Parsing module <DAC_output_scalable_HPF>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\ADC_input.v" into library work
Parsing module <ADC_input>.
Analyzing Verilog file "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" into library work
Parsing module <main>.
Parsing module <command_selector>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating module <main>.
Elaborating module <OBUFDS>.
Elaborating module <IBUFDS>.
Elaborating module <LED_controller>.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\LED_controller.v" Line 100: Result of 17-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\LED_controller.v" Line 113: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\LED_controller.v" Line 130: Result of 17-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 683: Size mismatch in connection of port <led5>. Formal port size is 24-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 684: Size mismatch in connection of port <led6>. Formal port size is 24-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 687: Size mismatch in connection of port <led8>. Formal port size is 24-bit while actual signal size is 40-bit.
Elaborating module <variable_freq_clk_generator(M_DEFAULT=42,D_DEFAULT=25)>.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\variable_freq_clk_generator.v" Line 94: Result of 32-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\variable_freq_clk_generator.v" Line 95: Result of 32-bit expression is truncated to fit in 9-bit target.
Elaborating module <DCM_CLKGEN(CLKFXDV_DIVIDE=2,CLKFX_DIVIDE=25,CLKFX_MD_MAX=0.0,CLKFX_MULTIPLY=42,CLKIN_PERIOD=0.0,SPREAD_SPECTRUM="NONE",STARTUP_WAIT="FALSE")>.
Elaborating module <BUFG>.
Elaborating module <SDRAM_FIFO(C3_P0_MASK_SIZE=4,C3_P0_DATA_PORT_SIZE=32,C3_P1_MASK_SIZE=4,C3_P1_DATA_PORT_SIZE=32,DEBUG_EN=0,C3_MEMCLK_PERIOD=3200,C3_CALIB_SOFT_IP="TRUE",C3_SIMULATION="FALSE",C3_HW_TESTING="FALSE",C3_RST_ACT_LOW=0,C3_INPUT_CLK_TYPE="DIFFERENTIAL",C3_MEM_ADDR_ORDER="ROW_BANK_COLUMN",C3_NUM_DQ_PINS=16,C3_MEM_ADDR_WIDTH=13,C3_MEM_BANKADDR_WIDTH=3)>.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 266: Result of 5-bit expression is truncated to fit in 4-bit target.
Elaborating module <memc3_infrastructure(C_MEMCLK_PERIOD=3200,C_RST_ACT_LOW=0,C_INPUT_CLK_TYPE="DIFFERENTIAL")>.
Elaborating module <IBUFG>.
Elaborating module <PLL_ADV(BANDWIDTH="OPTIMIZED",CLKIN1_PERIOD=10,CLKIN2_PERIOD=10,CLKOUT0_DIVIDE=1,CLKOUT1_DIVIDE=1,CLKOUT2_DIVIDE=4,CLKOUT3_DIVIDE=8,CLKOUT4_DIVIDE=1,CLKOUT5_DIVIDE=1,CLKOUT0_PHASE=0.0,CLKOUT1_PHASE=180.0,CLKOUT2_PHASE=0.0,CLKOUT3_PHASE=0.0,CLKOUT4_PHASE=0.0,CLKOUT5_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKOUT1_DUTY_CYCLE=0.5,CLKOUT2_DUTY_CYCLE=0.5,CLKOUT3_DUTY_CYCLE=0.5,CLKOUT4_DUTY_CYCLE=0.5,CLKOUT5_DUTY_CYCLE=0.5,COMPENSATION="INTERNAL",DIVCLK_DIVIDE=4,CLKFBOUT_MULT=25,CLKFBOUT_PHASE=0.0,REF_JITTER=0.005)>.
Elaborating module <BUFPLL_MCB>.
Elaborating module
<memc3_wrapper(C_MEMCLK_PERIOD=3200,C_CALIB_SOFT_IP="TRUE",C_SIMULATION="FALSE",C_ARB_NUM_TIME_SLOTS=12,C_ARB_TIME_SLOT_0=3'b0,C_ARB_TIME_SLOT_1=3'b0,C_ARB_TIME_SLOT_2=3'b0,C_ARB_TIME_SLOT_3=3'b0,C_ARB_TIME_SLOT_4=3'b0,C_ARB_TIME_SLOT_5=3'b0,C_ARB_TIME_SLOT_6=3'b0,C_ARB_TIME_SLOT_7=3'b0,C_ARB_TIME_SLOT_8=3'b0,C_ARB_TIME_SLOT_9=3'b0,C_ARB_TIME_SLOT_10=3'b0,C_ARB_TIME_SLOT_11=3'b0,C_MEM_TRAS=40000,C_MEM_TRCD=15000,C_MEM_TREFI=7800000,C_MEM_TRFC=127500,C_MEM_TRP=15000,C_MEM_TWR=15000,C_MEM_TRTP=7500,C_MEM_TWTR=7500,C_MEM_ADDR_ORDER="ROW_BANK_COLUMN",C_NUM_DQ_PINS=16,C_MEM_TYPE="DDR2",C_MEM_DENSITY="1Gb",C_MEM_BURST_LEN=4,C_MEM_CAS_LATENCY=5,C_MEM_ADDR_WIDTH=13,C_MEM_BANKADDR_WIDTH=3,C_MEM_NUM_COL_BITS=10,C_MEM_DDR1_2_ODS="FULL",C_MEM_DDR2_RTT="50OHMS",C_MEM_DDR2_DIFF_DQS_EN="YES",C_MEM_DDR2_3_PA_SR="FULL",C_MEM_DDR2_3_HIGH_TEMP_SR="NORMAL",C_MEM_DDR3_CAS_LATENCY=6,C_MEM_DDR3_ODS="DIV6",C_MEM_DDR3_RTT="DIV2",C_MEM_DDR3_CAS_WR_LATENCY=5,C_MEM_DDR3_AUTO_SR="ENABLED",C_MEM_DDR3_DYN_WRT_ODT="OFF",C_MEM_MOBILE_PA_SR="
FULL",C_MEM_MDDR_ODS="FULL",C_MC_CALIB_BYPASS="NO",C_MC_CALIBRATION_MODE="CALIBRATION",C_MC_CALIBRATION_DELAY="HALF",C_SKIP_IN_TERM_CAL=0,C_SKIP_DYNAMIC_CAL=0,C_LDQSP_TAP_DELAY_VAL=0,C_LDQSN_TAP_DELAY_VAL=0,C_UDQSP_TAP_DELAY_VAL=0,C_UDQSN_TAP_DELAY_VAL=0,C_DQ0_TAP_DELAY_VAL=0,C_DQ1_TAP_DELAY_VAL=0,C_DQ2_TAP_DELAY_VAL=0,C_DQ3_TAP_DELAY_VAL=0,C_DQ4_TAP_DELAY_VAL=0,C_DQ5_TAP_DELAY_VAL=0,C_DQ6_TAP_DELAY_VAL=0,C_DQ7_TAP_DELAY_VAL=0,C_DQ8_TAP_DELAY_VAL=0,C_DQ9_TAP_DELAY_VAL=0,C_DQ10_TAP_DELAY_VAL=0,C_DQ11_TAP_DELAY_VAL=0,C_DQ12_TAP_DELAY_VAL=0,C_DQ13_TAP_DELAY_VAL=0,C_DQ14_TAP_DELAY_VAL=0,C_DQ15_TAP_DELAY_VAL=0)>.
WARNING:HDLCompiler:1016 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_raw_wrapper.v" Line 6346: Port BUSY is not connected to this instance
Elaborating module
<mcb_raw_wrapper(C_MEMCLK_PERIOD=3200,C_P0_MASK_SIZE=4,C_P0_DATA_PORT_SIZE=32,C_P1_MASK_SIZE=4,C_P1_DATA_PORT_SIZE=32,C_ARB_NUM_TIME_SLOTS=12,C_ARB_TIME_SLOT_0=18'b111111111111111000,C_ARB_TIME_SLOT_1=18'b111111111111111000,C_ARB_TIME_SLOT_2=18'b111111111111111000,C_ARB_TIME_SLOT_3=18'b111111111111111000,C_ARB_TIME_SLOT_4=18'b111111111111111000,C_ARB_TIME_SLOT_5=18'b111111111111111000,C_ARB_TIME_SLOT_6=18'b111111111111111000,C_ARB_TIME_SLOT_7=18'b111111111111111000,C_ARB_TIME_SLOT_8=18'b111111111111111000,C_ARB_TIME_SLOT_9=18'b111111111111111000,C_ARB_TIME_SLOT_10=18'b111111111111111000,C_ARB_TIME_SLOT_11=18'b111111111111111000,C_PORT_CONFIG="B32_B32_R32_R32_R32_R32",C_PORT_ENABLE=6'b01,C_MEM_TRAS=40000,C_MEM_TRCD=15000,C_MEM_TREFI=7800000,C_MEM_TRFC=127500,C_MEM_TRP=15000,C_MEM_TWR=15000,C_MEM_TRTP=7500,C_MEM_TWTR=7500,C_MEM_ADDR_ORDER="ROW_BANK_COLUMN",C_NUM_DQ_PINS=16,C_MEM_TYPE="DDR2",C_MEM_DENSITY="1Gb",C_MEM_BURST_LEN=4,C_MEM_CAS_LATENCY=5,C_MEM_ADDR_WIDTH=13,C_MEM_BANKADDR_WIDTH=3,C_MEM_NUM_COL_BITS=10
,C_MEM_DDR1_2_ODS="FULL",C_MEM_DDR2_RTT="50OHMS",C_MEM_DDR2_DIFF_DQS_EN="YES",C_MEM_DDR2_3_PA_SR="FULL",C_MEM_DDR2_3_HIGH_TEMP_SR="NORMAL",C_MEM_DDR3_CAS_LATENCY=6,C_MEM_DDR3_ODS="DIV6",C_MEM_DDR3_RTT="DIV2",C_MEM_DDR3_CAS_WR_LATENCY=5,C_MEM_DDR3_AUTO_SR="ENABLED",C_MEM_DDR3_DYN_WRT_ODT="OFF",C_MEM_MOBILE_PA_SR="FULL",C_MEM_MDDR_ODS="FULL",C_MC_CALIBRATION_CLK_DIV=1,C_MC_CALIBRATION_MODE="CALIBRATION",C_MC_CALIBRATION_DELAY="HALF",C_MC_CALIB_BYPASS="NO",C_MC_CALIBRATION_RA=16'b0,C_MC_CALIBRATION_BA=4'b0,C_MC_CALIBRATION_CA=12'b0,C_CALIB_SOFT_IP="TRUE",C_SKIP_IN_TERM_CAL=0,C_SKIP_DYNAMIC_CAL=0,C_MEM_TZQINIT_MAXCNT=10'b1000000000,C_SKIP_DYN_IN_TERM=1'b1,C_SIMULATION="FALSE",LDQSP_TAP_DELAY_VAL=0,UDQSP_TAP_DELAY_VAL=0,LDQSN_TAP_DELAY_VAL=0,UDQSN_TAP_DELAY_VAL=0,DQ0_TAP_DELAY_VAL=0,DQ1_TAP_DELAY_VAL=0,DQ2_TAP_DELAY_VAL=0,DQ3_TAP_DELAY_VAL=0,DQ4_TAP_DELAY_VAL=0,DQ5_TAP_DELAY_VAL=0,DQ6_TAP_DELAY_VAL=0,DQ7_TAP_DELAY_VAL=0,DQ8_TAP_DELAY_VAL=0,DQ9_TAP_DELAY_VAL=0,DQ10_TAP_DELAY_VAL=0,DQ11_TAP_DELAY_VAL=0,DQ12_TAP_DELA
Y_VAL=0,DQ13_TAP_DELAY_VAL=0,DQ14_TAP_DELAY_VAL=0,DQ15_TAP_DELAY_VAL=0)>.
WARNING:HDLCompiler:872 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_raw_wrapper.v" Line 685: Using initial value of allzero since it is never assigned
Elaborating module
<MCB(PORT_CONFIG="B32_B32_R32_R32_R32_R32",MEM_WIDTH=16,MEM_TYPE="DDR2",MEM_BURST_LEN=4,MEM_ADDR_ORDER="ROW_BANK_COLUMN",MEM_CAS_LATENCY=5,MEM_DDR3_CAS_LATENCY=6,MEM_DDR2_WRT_RECOVERY=32'sb0101,MEM_DDR3_WRT_RECOVERY=5,MEM_MOBILE_PA_SR="FULL",MEM_DDR1_2_ODS="FULL",MEM_DDR3_ODS="DIV6",MEM_DDR2_RTT="50OHMS",MEM_DDR3_RTT="DIV2",MEM_DDR3_ADD_LATENCY="OFF",MEM_DDR2_ADD_LATENCY=0,MEM_MOBILE_TC_SR=0,MEM_MDDR_ODS="FULL",MEM_DDR2_DIFF_DQS_EN="YES",MEM_DDR2_3_PA_SR="FULL",MEM_DDR3_CAS_WR_LATENCY=5,MEM_DDR3_AUTO_SR="ENABLED",MEM_DDR2_3_HIGH_TEMP_SR="NORMAL",MEM_DDR3_DYN_WRT_ODT="OFF",MEM_RA_SIZE=13,MEM_BA_SIZE=3,MEM_CA_SIZE=10,MEM_RAS_VAL=32'sb01101,MEM_RCD_VAL=32'sb0101,MEM_REFI_VAL=32'sb0100110000110,MEM_RFC_VAL=32'sb0101000,MEM_RP_VAL=32'sb0101,MEM_WR_VAL=32'sb0101,MEM_RTP_VAL=32'sb011,MEM_WTR_VAL=32'sb011,CAL_BYPASS="NO",CAL_RA=16'b0,CAL_BA=4'b0,CAL_CA=12'b0,CAL_CLK_DIV=1,CAL_DELAY="HALF",ARB_NUM_TIME_SLOTS=12,ARB_TIME_SLOT_0=18'b111111111111111000,ARB_TIME_SLOT_1=18'b111111111111111000,ARB_TIME_SLOT_2=18'b1111111111
11111000,ARB_TIME_SLOT_3=18'b111111111111111000,ARB_TIME_SLOT_4=18'b111111111111111000,ARB_TIME_SLOT_5=18'b111111111111111000,ARB_TIME_SLOT_6=18'b111111111111111000,ARB_TIME_SLOT_7=18'b111111111111111000,ARB_TIME_SLOT_8=18'b111111111111111000,ARB_TIME_SLOT_9=18'b111111111111111000,ARB_TIME_SLOT_10=18'b111111111111111000,ARB_TIME_SLOT_11=18'b111111111111111000)>.
Elaborating module <mcb_soft_calibration_top(C_MEM_TZQINIT_MAXCNT=10'b1000000000,C_MC_CALIBRATION_MODE="CALIBRATION",SKIP_IN_TERM_CAL=0,SKIP_DYNAMIC_CAL=0,SKIP_DYN_IN_TERM=1'b1,C_SIMULATION="FALSE",C_MEM_TYPE="DDR2")>.
Elaborating module <mcb_soft_calibration(C_MEM_TZQINIT_MAXCNT=10'b1000000000,C_MC_CALIBRATION_MODE="CALIBRATION",SKIP_IN_TERM_CAL=0,SKIP_DYNAMIC_CAL=0,SKIP_DYN_IN_TERM=1'b1,C_SIMULATION="FALSE",C_MEM_TYPE="DDR2")>.
WARNING:HDLCompiler:872 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 312: Using initial value of START_BROADCAST since it is never assigned
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 373: Assignment to Half_MV_DU ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 375: Assignment to Half_MV_DD ignored, since the identifier is never used
Elaborating module <iodrp_controller>.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\iodrp_controller.v" Line 186: Result of 4-bit expression is truncated to fit in 3-bit target.
Elaborating module <iodrp_mcb_controller>.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\iodrp_mcb_controller.v" Line 301: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\iodrp_mcb_controller.v" Line 312: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 408: Assignment to MCB_READ_DATA ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 654: Assignment to MCB_UODATAVALID_U ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 809: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 813: Result of 8-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 859: Result of 8-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 863: Result of 8-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 864: Result of 8-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration.v" Line 700: Assignment to IODRPCTRLR_USE_BKST ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\mcb_soft_calibration_top.v" Line 216: Assignment to Max_Value ignored, since the identifier is never used
Elaborating module <IOBUF>.
Elaborating module <IODRP2>.
Elaborating module <OSERDES2(BYPASS_GCLK_FF="TRUE",DATA_RATE_OQ="SDR",DATA_RATE_OT="SDR",OUTPUT_MODE="SINGLE_ENDED",SERDES_MODE="MASTER",DATA_WIDTH=2)>.
Elaborating module <OSERDES2(BYPASS_GCLK_FF="TRUE",DATA_RATE_OQ="SDR",DATA_RATE_OT="SDR",OUTPUT_MODE="SINGLE_ENDED",SERDES_MODE="MASTER",DATA_WIDTH=2,TRAIN_PATTERN=15)>.
Elaborating module <OSERDES2(BYPASS_GCLK_FF="TRUE",DATA_RATE_OQ="SDR",DATA_RATE_OT="SDR",OUTPUT_MODE="SINGLE_ENDED",SERDES_MODE="MASTER",DATA_WIDTH=2,TRAIN_PATTERN=5)>.
Elaborating module <OSERDES2(BYPASS_GCLK_FF="TRUE",DATA_RATE_OQ="SDR",DATA_RATE_OT="SDR",OUTPUT_MODE="SINGLE_ENDED",SERDES_MODE="SLAVE",DATA_WIDTH=2)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=7,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=7,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=6,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=6,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=14,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=14,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=5,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=5,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=4,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=4,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=0,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=0,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=1,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=1,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=15,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=15,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=3,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=3,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=2,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=2,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=8,ODELAY_VALUE=0,SERDES_MODE="MASTER",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODRP2_MCB(DATA_RATE="SDR",IDELAY_VALUE=0,MCB_ADDRESS=8,ODELAY_VALUE=0,SERDES_MODE="SLAVE",SIM_TAPDELAY_VALUE=10)>.
Elaborating module <IODELAY2(ODELAY_VALUE=0,DELAY_SRC="ODATAIN",SIM_TAPDELAY_VALUE=50)>.
Elaborating module <OBUFT>.
Elaborating module <OBUFTDS>.
Elaborating module <IOBUFDS>.
Elaborating module <PULLDOWN>.
Elaborating module <PULLUP>.
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_wrapper.v" Line 411: Assignment to uo_data ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_wrapper.v" Line 412: Assignment to uo_data_valid ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_wrapper.v" Line 414: Assignment to uo_cmd_ready_in ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_wrapper.v" Line 415: Assignment to uo_refrsh_flag ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_wrapper.v" Line 416: Assignment to uo_cal_start ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_wrapper.v" Line 417: Assignment to uo_sdo ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\memc3_wrapper.v" Line 418: Assignment to status ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 409: Assignment to c3_p0_cmd_empty ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 416: Assignment to c3_p0_wr_empty ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 417: Assignment to c3_p0_wr_count ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 418: Assignment to c3_p0_wr_underrun ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 419: Assignment to c3_p0_wr_error ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 423: Assignment to c3_p0_rd_full ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 425: Assignment to c3_p0_rd_count ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 426: Assignment to c3_p0_rd_overflow ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 427: Assignment to c3_p0_rd_error ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 429: Assignment to selfrefresh_mode ignored, since the identifier is never used
Elaborating module <ddr2_state_machine>.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\ddr2_state_machine.v" Line 137: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\ddr2_state_machine.v" Line 155: Result of 31-bit expression is truncated to fit in 30-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\ddr2_state_machine.v" Line 175: Result of 31-bit expression is truncated to fit in 30-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\ddr2_state_machine.v" Line 199: Result of 32-bit expression is truncated to fit in 6-bit target.
Elaborating module <fifo_w16_2048_r64_512>.
Elaborating module <fifo_w64_512_r16_2048>.
WARNING:HDLCompiler:634 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\SDRAM_FIFO.v" Line 234: Net <selfrefresh_enter> does not have a driver.
Elaborating module <RAM_bank>.
Elaborating module <RAM_1024x16bit>.
Elaborating module
<RAMB16BWER(DATA_WIDTH_A=18,DATA_WIDTH_B=18,DOA_REG=0,DOB_REG=0,EN_RSTRAM_A="TRUE",EN_RSTRAM_B="TRUE",INITP_00=256'b0,INITP_01=256'b0,INITP_02=256'b0,INITP_03=256'b0,INITP_04=256'b0,INITP_05=256'b0,INITP_06=256'b0,INITP_07=256'b0,INIT_00=256'b0,INIT_01=256'b0,INIT_02=256'b0,INIT_03=256'b0,INIT_04=256'b0,INIT_05=256'b0,INIT_06=256'b0,INIT_07=256'b0,INIT_08=256'b0,INIT_09=256'b0,INIT_0A=256'b0,INIT_0B=256'b0,INIT_0C=256'b0,INIT_0D=256'b0,INIT_0E=256'b0,INIT_0F=256'b0,INIT_10=256'b0,INIT_11=256'b0,INIT_12=256'b0,INIT_13=256'b0,INIT_14=256'b0,INIT_15=256'b0,INIT_16=256'b0,INIT_17=256'b0,INIT_18=256'b0,INIT_19=256'b0,INIT_1A=256'b0,INIT_1B=256'b0,INIT_1C=256'b0,INIT_1D=256'b0,INIT_1E=256'b0,INIT_1F=256'b0,INIT_20=256'b0,INIT_21=256'b0,INIT_22=256'b0,INIT_23=256'b0,INIT_24=256'b0,INIT_25=256'b0,INIT_26=256'b0,INIT_27=256'b0,INIT_28=256'b0,INIT_29=256'b0,INIT_2A=256'b0,INIT_2B=256'b0,INIT_2C=256'b0,INIT_2D=256'b0,INIT_2E=256'b0,INIT_2F=256'b0,INIT_30=256'b0,INIT_31=256'b0,INIT_32=256'b0,INIT_33=256'b0,INIT_34=256'b0
,INIT_35=256'b0,INIT_36=256'b0,INIT_37=256'b0,INIT_38=256'b0,INIT_39=256'b0,INIT_3A=256'b0,INIT_3B=256'b0,INIT_3C=256'b0,INIT_3D=256'b0,INIT_3E=256'b0,INIT_3F=256'b0,INIT_A=36'b0,INIT_B=36'b0,INIT_FILE="NONE",RSTTYPE="SYNC",RST_PRIORITY_A="CE",RST_PRIORITY_B="CE",SIM_COLLISION_CHECK="ALL",SIM_DEVICE="SPARTAN6",SRVAL_A=36'b0,SRVAL_B=36'b0,WRITE_MODE_A="WRITE_FIRST",WRITE_MODE_B="WRITE_FIRST")>.
Elaborating module <command_selector>.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 1070: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 1071: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 1072: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 1073: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2052: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2062: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2072: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2200: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2205: Result of 7-bit expression is truncated to fit in 6-bit target.
Elaborating module <DAC_output_scalable_HPF(ms_wait=99,ms_clk1_a=100,ms_clk11_a=140)>.
WARNING:HDLCompiler:413 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\DAC_output_scalable_HPF.v" Line 64: Result of 32-bit expression is truncated to fit in 19-bit target.
Elaborating module <multiplier_18x18>.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2296: Size mismatch in connection of port <noise_suppress>. Formal port size is 7-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2320: Size mismatch in connection of port <noise_suppress>. Formal port size is 7-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2344: Size mismatch in connection of port <noise_suppress>. Formal port size is 7-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2368: Size mismatch in connection of port <noise_suppress>. Formal port size is 7-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2392: Size mismatch in connection of port <noise_suppress>. Formal port size is 7-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" Line 2416: Size mismatch in connection of port <noise_suppress>. Formal port size is 7-bit while actual signal size is 32-bit.
Elaborating module <ADC_input(ms_wait=99,ms_clk1_a=100,ms_clk11_a=140)>.
Elaborating module <MISO_phase_selector>.
Elaborating module <MISO_DDR_phase_selector>.
WARNING:HDLCompiler:1016 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\okLibrary.v" Line 40: Port CLK180 is not connected to this instance
WARNING:HDLCompiler:1016 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\okLibrary.v" Line 68: Port BUSY is not connected to this instance
Elaborating module <okHost>.
Elaborating module <DCM_SP>.
Elaborating module <FDS>.
Elaborating module <FD>.
Elaborating module <IODELAY2(IDELAY_TYPE="FIXED",IDELAY_VALUE=50,DELAY_SRC="IDATAIN")>.
Elaborating module <FDRE>.
Elaborating module <OBUF>.
Elaborating module <okCoreHarness>.
Elaborating module <okWireOR(N=33)>.
Elaborating module <okWireIn>.
Elaborating module <okTriggerIn>.
Elaborating module <okWireOut>.
Elaborating module <okPipeOut>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <main>.
Related source file is "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v".
C3_P0_MASK_SIZE = 4
C3_P0_DATA_PORT_SIZE = 32
C3_P1_MASK_SIZE = 4
C3_P1_DATA_PORT_SIZE = 32
DEBUG_EN = 0
C3_MEMCLK_PERIOD = 3200
C3_CALIB_SOFT_IP = "TRUE"
C3_SIMULATION = "FALSE"
C3_HW_TESTING = "FALSE"
C3_RST_ACT_LOW = 0
C3_INPUT_CLK_TYPE = "DIFFERENTIAL"
C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN"
C3_NUM_DQ_PINS = 16
C3_MEM_ADDR_WIDTH = 13
C3_MEM_BANKADDR_WIDTH = 3
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 773: Output port <RAM_data_out_A> of the instance <RAM_bank_1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 808: Output port <RAM_data_out_A> of the instance <RAM_bank_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 830: Output port <RAM_data_out_A> of the instance <RAM_bank_3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2264: Output port <DAC_SYNC> of the instance <DAC_output_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2264: Output port <DAC_SCLK> of the instance <DAC_output_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2288: Output port <DAC_SYNC> of the instance <DAC_output_3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2288: Output port <DAC_SCLK> of the instance <DAC_output_3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2312: Output port <DAC_SYNC> of the instance <DAC_output_4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2312: Output port <DAC_SCLK> of the instance <DAC_output_4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2336: Output port <DAC_SYNC> of the instance <DAC_output_5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2336: Output port <DAC_SCLK> of the instance <DAC_output_5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2360: Output port <DAC_SYNC> of the instance <DAC_output_6> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2360: Output port <DAC_SCLK> of the instance <DAC_output_6> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2384: Output port <DAC_SYNC> of the instance <DAC_output_7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2384: Output port <DAC_SCLK> of the instance <DAC_output_7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2408: Output port <DAC_SYNC> of the instance <DAC_output_8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2408: Output port <DAC_SCLK> of the instance <DAC_output_8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2450: Output port <ADC_CS> of the instance <ADC_inout_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2450: Output port <ADC_SCLK> of the instance <ADC_inout_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2466: Output port <ADC_CS> of the instance <ADC_inout_3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2466: Output port <ADC_SCLK> of the instance <ADC_inout_3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2482: Output port <ADC_CS> of the instance <ADC_inout_4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2482: Output port <ADC_SCLK> of the instance <ADC_inout_4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2498: Output port <ADC_CS> of the instance <ADC_inout_5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2498: Output port <ADC_SCLK> of the instance <ADC_inout_5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2514: Output port <ADC_CS> of the instance <ADC_inout_6> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2514: Output port <ADC_SCLK> of the instance <ADC_inout_6> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2530: Output port <ADC_CS> of the instance <ADC_inout_7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2530: Output port <ADC_SCLK> of the instance <ADC_inout_7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2546: Output port <ADC_CS> of the instance <ADC_inout_8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\jvoigts\Downloads\RHD2000InterfaceXEM6010_release_140226\RHD2000InterfaceXEM6010\main.v" line 2546: Output port <ADC_SCLK> of the instance <ADC_inout_8> is unconnected or connected to loadless signal.
Found 10-bit register for signal <loop_aux_cmd_index_1>.
Found 10-bit register for signal <loop_aux_cmd_index_2>.
Found 10-bit register for signal <loop_aux_cmd_index_3>.
Found 16-bit register for signal <TTL_out_user>.
Found 16-bit register for signal <DAC_manual>.
Found 16-bit register for signal <DAC_thresh_1>.
Found 16-bit register for signal <DAC_thresh_2>.
Found 16-bit register for signal <DAC_thresh_3>.
Found 16-bit register for signal <DAC_thresh_4>.
Found 16-bit register for signal <DAC_thresh_5>.
Found 16-bit register for signal <DAC_thresh_6>.
Found 16-bit register for signal <DAC_thresh_7>.
Found 16-bit register for signal <DAC_thresh_8>.
Found 1-bit register for signal <DAC_thresh_pol_1>.
Found 1-bit register for signal <DAC_thresh_pol_2>.
Found 1-bit register for signal <DAC_thresh_pol_3>.
Found 1-bit register for signal <DAC_thresh_pol_4>.
Found 1-bit register for signal <DAC_thresh_pol_5>.
Found 1-bit register for signal <DAC_thresh_pol_6>.
Found 1-bit register for signal <DAC_thresh_pol_7>.
Found 1-bit register for signal <DAC_thresh_pol_8>.
Found 1-bit register for signal <HPF_en>.
Found 16-bit register for signal <HPF_coefficient>.
Found 1-bit register for signal <external_fast_settle_enable>.
Found 4-bit register for signal <external_fast_settle_channel>.
Found 1-bit register for signal <external_digout_enable_A>.
Found 1-bit register for signal <external_digout_enable_B>.
Found 1-bit register for signal <external_digout_enable_C>.
Found 1-bit register for signal <external_digout_enable_D>.
Found 4-bit register for signal <external_digout_channel_A>.
Found 4-bit register for signal <external_digout_channel_B>.
Found 4-bit register for signal <external_digout_channel_C>.
Found 4-bit register for signal <external_digout_channel_D>.
Found 32-bit register for signal <main_state>.
Found 32-bit register for signal <timestamp>.
Found 1-bit register for signal <sample_clk>.
Found 6-bit register for signal <channel>.
Found 1-bit register for signal <CS_b>.
Found 1-bit register for signal <SCLK>.
Found 1-bit register for signal <MOSI_A>.
Found 1-bit register for signal <MOSI_B>.
Found 1-bit register for signal <MOSI_C>.
Found 1-bit register for signal <MOSI_D>.
Found 16-bit register for signal <FIFO_data_in>.
Found 1-bit register for signal <FIFO_write_to>.
Found 6-bit register for signal <channel_MISO>.
Found 10-bit register for signal <aux_cmd_index_1>.
Found 10-bit register for signal <aux_cmd_index_2>.
Found 10-bit register for signal <aux_cmd_index_3>.
Found 10-bit register for signal <max_aux_cmd_index_1>.
Found 10-bit register for signal <max_aux_cmd_index_2>.
Found 10-bit register for signal <max_aux_cmd_index_3>.
Found 4-bit register for signal <aux_cmd_bank_1_A>.
Found 4-bit register for signal <aux_cmd_bank_1_B>.
Found 4-bit register for signal <aux_cmd_bank_1_C>.
Found 4-bit register for signal <aux_cmd_bank_1_D>.
Found 4-bit register for signal <aux_cmd_bank_2_A>.
Found 4-bit register for signal <aux_cmd_bank_2_B>.
Found 4-bit register for signal <aux_cmd_bank_2_C>.
Found 4-bit register for signal <aux_cmd_bank_2_D>.
Found 4-bit register for signal <aux_cmd_bank_3_A>.
Found 4-bit register for signal <aux_cmd_bank_3_B>.
Found 4-bit register for signal <aux_cmd_bank_3_C>.
Found 4-bit register for signal <aux_cmd_bank_3_D>.
Found 1-bit register for signal <data_stream_1_en>.
Found 1-bit register for signal <data_stream_2_en>.
Found 1-bit register for signal <data_stream_3_en>.
Found 1-bit register for signal <data_stream_4_en>.
Found 1-bit register for signal <data_stream_5_en>.
Found 1-bit register for signal <data_stream_6_en>.
Found 1-bit register for signal <data_stream_7_en>.
Found 1-bit register for signal <data_stream_8_en>.
Found 4-bit register for signal <data_stream_1_sel>.
Found 4-bit register for signal <data_stream_2_sel>.
Found 4-bit register for signal <data_stream_3_sel>.
Found 4-bit register for signal <data_stream_4_sel>.
Found 4-bit register for signal <data_stream_5_sel>.
Found 4-bit register for signal <data_stream_6_sel>.
Found 4-bit register for signal <data_stream_7_sel>.
Found 4-bit register for signal <data_stream_8_sel>.
Found 16-bit register for signal <DAC_pre_register_1>.
Found 16-bit register for signal <DAC_pre_register_2>.
Found 16-bit register for signal <DAC_pre_register_3>.
Found 16-bit register for signal <DAC_pre_register_4>.
Found 16-bit register for signal <DAC_pre_register_5>.
Found 16-bit register for signal <DAC_pre_register_6>.
Found 16-bit register for signal <DAC_pre_register_7>.
Found 16-bit register for signal <DAC_pre_register_8>.
Found 1-bit register for signal <SPI_running>.
Found 16-bit register for signal <MOSI_cmd_A>.
Found 16-bit register for signal <MOSI_cmd_B>.
Found 16-bit register for signal <MOSI_cmd_C>.
Found 16-bit register for signal <MOSI_cmd_D>.
Found 16-bit register for signal <data_stream_TTL_in>.
Found 16-bit register for signal <data_stream_TTL_out>.
Found 1-bit register for signal <external_fast_settle_prev>.
Found 1-bit register for signal <external_fast_settle>.
Found 1-bit register for signal <external_digout_A>.
Found 1-bit register for signal <external_digout_B>.
Found 1-bit register for signal <external_digout_C>.
Found 1-bit register for signal <external_digout_D>.
Found 16-bit register for signal <DAC_register_1>.
Found 16-bit register for signal <DAC_register_2>.
Found 16-bit register for signal <DAC_register_3>.
Found 16-bit register for signal <DAC_register_4>.
Found 16-bit register for signal <DAC_register_5>.
Found 16-bit register for signal <DAC_register_6>.
Found 16-bit register for signal <DAC_register_7>.
Found 16-bit register for signal <DAC_register_8>.
Found 10-bit register for signal <RAM_addr_rd>.
Found 4-bit register for signal <RAM_bank_sel_rd>.
Found 1-bit register for signal <in4x_A1<73>>.
Found 1-bit register for signal <in4x_A1<72>>.
Found 1-bit register for signal <in4x_A1<71>>.
Found 1-bit register for signal <in4x_A1<70>>.
Found 1-bit register for signal <in4x_A1<69>>.
Found 1-bit register for signal <in4x_A1<68>>.
Found 1-bit register for signal <in4x_A1<67>>.
Found 1-bit register for signal <in4x_A1<66>>.
Found 1-bit register for signal <in4x_A1<65>>.
Found 1-bit register for signal <in4x_A1<64>>.
Found 1-bit register for signal <in4x_A1<63>>.
Found 1-bit register for signal <in4x_A1<62>>.
Found 1-bit register for signal <in4x_A1<61>>.
Found 1-bit register for signal <in4x_A1<60>>.
Found 1-bit register for signal <in4x_A1<59>>.
Found 1-bit register for signal <in4x_A1<58>>.
Found 1-bit register for signal <in4x_A1<57>>.
Found 1-bit register for signal <in4x_A1<56>>.
Found 1-bit register for signal <in4x_A1<55>>.
Found 1-bit register for signal <in4x_A1<54>>.
Found 1-bit register for signal <in4x_A1<53>>.
Found 1-bit register for signal <in4x_A1<52>>.
Found 1-bit register for signal <in4x_A1<51>>.
Found 1-bit register for signal <in4x_A1<50>>.
Found 1-bit register for signal <in4x_A1<49>>.
Found 1-bit register for signal <in4x_A1<48>>.
Found 1-bit register for signal <in4x_A1<47>>.
Found 1-bit register for signal <in4x_A1<46>>.
Found 1-bit register for signal <in4x_A1<45>>.
Found 1-bit register for signal <in4x_A1<44>>.
Found 1-bit register for signal <in4x_A1<43>>.
Found 1-bit register for signal <in4x_A1<42>>.
Found 1-bit register for signal <in4x_A1<41>>.
Found 1-bit register for signal <in4x_A1<40>>.
Found 1-bit register for signal <in4x_A1<39>>.
Found 1-bit register for signal <in4x_A1<38>>.
Found 1-bit register for signal <in4x_A1<37>>.
Found 1-bit register for signal <in4x_A1<36>>.
Found 1-bit register for signal <in4x_A1<35>>.
Found 1-bit register for signal <in4x_A1<34>>.
Found 1-bit register for signal <in4x_A1<33>>.
Found 1-bit register for signal <in4x_A1<32>>.
Found 1-bit register for signal <in4x_A1<31>>.
Found 1-bit register for signal <in4x_A1<30>>.
Found 1-bit register for signal <in4x_A1<29>>.
Found 1-bit register for signal <in4x_A1<28>>.
Found 1-bit register for signal <in4x_A1<27>>.
Found 1-bit register for signal <in4x_A1<26>>.
Found 1-bit register for signal <in4x_A1<25>>.
Found 1-bit register for signal <in4x_A1<24>>.
Found 1-bit register for signal <in4x_A1<23>>.
Found 1-bit register for signal <in4x_A1<22>>.
Found 1-bit register for signal <in4x_A1<21>>.
Found 1-bit register for signal <in4x_A1<20>>.
Found 1-bit register for signal <in4x_A1<19>>.
Found 1-bit register for signal <in4x_A1<18>>.
Found 1-bit register for signal <in4x_A1<17>>.
Found 1-bit register for signal <in4x_A1<16>>.
Found 1-bit register for signal <in4x_A1<15>>.
Found 1-bit register for signal <in4x_A1<14>>.
Found 1-bit register for signal <in4x_A1<13>>.
Found 1-bit register for signal <in4x_A1<12>>.
Found 1-bit register for signal <in4x_A1<11>>.
Found 1-bit register for signal <in4x_A1<10>>.
Found 1-bit register for signal <in4x_A1<9>>.
Found 1-bit register for signal <in4x_A1<8>>.
Found 1-bit register for signal <in4x_A1<7>>.
Found 1-bit register for signal <in4x_A1<6>>.
Found 1-bit register for signal <in4x_A1<5>>.
Found 1-bit register for signal <in4x_A1<4>>.
Found 1-bit register for signal <in4x_A1<3>>.
Found 1-bit register for signal <in4x_A1<2>>.
Found 1-bit register for signal <in4x_A1<1>>.
Found 1-bit register for signal <in4x_A1<0>>.
Found 1-bit register for signal <in4x_A2<73>>.
Found 1-bit register for signal <in4x_A2<72>>.
Found 1-bit register for signal <in4x_A2<71>>.
Found 1-bit register for signal <in4x_A2<70>>.
Found 1-bit register for signal <in4x_A2<69>>.
Found 1-bit register for signal <in4x_A2<68>>.
Found 1-bit register for signal <in4x_A2<67>>.
Found 1-bit register for signal <in4x_A2<66>>.
Found 1-bit register for signal <in4x_A2<65>>.
Found 1-bit register for signal <in4x_A2<64>>.
Found 1-bit register for signal <in4x_A2<63>>.
Found 1-bit register for signal <in4x_A2<62>>.
Found 1-bit register for signal <in4x_A2<61>>.
Found 1-bit register for signal <in4x_A2<60>>.
Found 1-bit register for signal <in4x_A2<59>>.
Found 1-bit register for signal <in4x_A2<58>>.
Found 1-bit register for signal <in4x_A2<57>>.
Found 1-bit register for signal <in4x_A2<56>>.
Found 1-bit register for signal <in4x_A2<55>>.
Found 1-bit register for signal <in4x_A2<54>>.
Found 1-bit register for signal <in4x_A2<53>>.
Found 1-bit register for signal <in4x_A2<52>>.
Found 1-bit register for signal <in4x_A2<51>>.
Found 1-bit register for signal <in4x_A2<50>>.
Found 1-bit register for signal <in4x_A2<49>>.
Found 1-bit register for signal <in4x_A2<48>>.
Found 1-bit register for signal <in4x_A2<47>>.
Found 1-bit register for signal <in4x_A2<46>>.
Found 1-bit register for signal <in4x_A2<45>>.
Found 1-bit register for signal <in4x_A2<44>>.
Found 1-bit register for signal <in4x_A2<43>>.
Found 1-bit register for signal <in4x_A2<42>>.
Found 1-bit register for signal <in4x_A2<41>>.
Found 1-bit register for signal <in4x_A2<40>>.
Found 1-bit register for signal <in4x_A2<39>>.
Found 1-bit register for signal <in4x_A2<38>>.
Found 1-bit register for signal <in4x_A2<37>>.
Found 1-bit register for signal <in4x_A2<36>>.
Found 1-bit register for signal <in4x_A2<35>>.
Found 1-bit register for signal <in4x_A2<34>>.
Found 1-bit register for signal <in4x_A2<33>>.
Found 1-bit register for signal <in4x_A2<32>>.
Found 1-bit register for signal <in4x_A2<31>>.
Found 1-bit register for signal <in4x_A2<30>>.
Found 1-bit register for signal <in4x_A2<29>>.
Found 1-bit register for signal <in4x_A2<28>>.
Found 1-bit register for signal <in4x_A2<27>>.
Found 1-bit register for signal <in4x_A2<26>>.
Found 1-bit register for signal <in4x_A2<25>>.
Found 1-bit register for signal <in4x_A2<24>>.
Found 1-bit register for signal <in4x_A2<23>>.
Found 1-bit register for signal <in4x_A2<22>>.
Found 1-bit register for signal <in4x_A2<21>>.
Found 1-bit register for signal <in4x_A2<20>>.
Found 1-bit register for signal <in4x_A2<19>>.
Found 1-bit register for signal <in4x_A2<18>>.
Found 1-bit register for signal <in4x_A2<17>>.
Found 1-bit register for signal <in4x_A2<16>>.
Found 1-bit register for signal <in4x_A2<15>>.
Found 1-bit register for signal <in4x_A2<14>>.
Found 1-bit register for signal <in4x_A2<13>>.
Found 1-bit register for signal <in4x_A2<12>>.
Found 1-bit register for signal <in4x_A2<11>>.
Found 1-bit register for signal <in4x_A2<10>>.
Found 1-bit register for signal <in4x_A2<9>>.
Found 1-bit register for signal <in4x_A2<8>>.
Found 1-bit register for signal <in4x_A2<7>>.
Found 1-bit register for signal <in4x_A2<6>>.
Found 1-bit register for signal <in4x_A2<5>>.
Found 1-bit register for signal <in4x_A2<4>>.
Found 1-bit register for signal <in4x_A2<3>>.
Found 1-bit register for signal <in4x_A2<2>>.
Found 1-bit register for signal <in4x_A2<1>>.
Found 1-bit register for signal <in4x_A2<0>>.
Found 1-bit register for signal <in4x_B1<73>>.
Found 1-bit register for signal <in4x_B1<72>>.
Found 1-bit register for signal <in4x_B1<71>>.
Found 1-bit register for signal <in4x_B1<70>>.
Found 1-bit register for signal <in4x_B1<69>>.
Found 1-bit register for signal <in4x_B1<68>>.
Found 1-bit register for signal <in4x_B1<67>>.
Found 1-bit register for signal <in4x_B1<66>>.
Found 1-bit register for signal <in4x_B1<65>>.
Found 1-bit register for signal <in4x_B1<64>>.
Found 1-bit register for signal <in4x_B1<63>>.
Found 1-bit register for signal <in4x_B1<62>>.
Found 1-bit register for signal <in4x_B1<61>>.
Found 1-bit register for signal <in4x_B1<60>>.
Found 1-bit register for signal <in4x_B1<59>>.
Found 1-bit register for signal <in4x_B1<58>>.
Found 1-bit register for signal <in4x_B1<57>>.
Found 1-bit register for signal <in4x_B1<56>>.
Found 1-bit register for signal <in4x_B1<55>>.
Found 1-bit register for signal <in4x_B1<54>>.
Found 1-bit register for signal <in4x_B1<53>>.
Found 1-bit register for signal <in4x_B1<52>>.
Found 1-bit register for signal <in4x_B1<51>>.
Found 1-bit register for signal <in4x_B1<50>>.
Found 1-bit register for signal <in4x_B1<49>>.
Found 1-bit register for signal <in4x_B1<48>>.
Found 1-bit register for signal <in4x_B1<47>>.
Found 1-bit register for signal <in4x_B1<46>>.
Found 1-bit register for signal <in4x_B1<45>>.
Found 1-bit register for signal <in4x_B1<44>>.
Found 1-bit register for signal <in4x_B1<43>>.
Found 1-bit register for signal <in4x_B1<42>>.
Found 1-bit register for signal <in4x_B1<41>>.
Found 1-bit register for signal <in4x_B1<40>>.
Found 1-bit register for signal <in4x_B1<39>>.
Found 1-bit register for signal <in4x_B1<38>>.
Found 1-bit register for signal <in4x_B1<37>>.
Found 1-bit register for signal <in4x_B1<36>>.
Found 1-bit register for signal <in4x_B1<35>>.
Found 1-bit register for signal <in4x_B1<34>>.
Found 1-bit register for signal <in4x_B1<33>>.
Found 1-bit register for signal <in4x_B1<32>>.
Found 1-bit register for signal <in4x_B1<31>>.
Found 1-bit register for signal <in4x_B1<30>>.
Found 1-bit register for signal <in4x_B1<29>>.
Found 1-bit register for signal <in4x_B1<28>>.
Found 1-bit register for signal <in4x_B1<27>>.
Found 1-bit register for signal <in4x_B1<26>>.
Found 1-bit register for signal <in4x_B1<25>>.
Found 1-bit register for signal <in4x_B1<24>>.
Found 1-bit register for signal <in4x_B1<23>>.
Found 1-bit register for signal <in4x_B1<22>>.
Found 1-bit register for signal <in4x_B1<21>>.
Found 1-bit register for signal <in4x_B1<20>>.
Found 1-bit register for signal <in4x_B1<19>>.
Found 1-bit register for signal <in4x_B1<18>>.
Found 1-bit register for signal <in4x_B1<17>>.
Found 1-bit register for signal <in4x_B1<16>>.
Found 1-bit register for signal <in4x_B1<15>>.
Found 1-bit register for signal <in4x_B1<14>>.
Found 1-bit register for signal <in4x_B1<13>>.
Found 1-bit register for signal <in4x_B1<12>>.
Found 1-bit register for signal <in4x_B1<11>>.
Found 1-bit register for signal <in4x_B1<10>>.
Found 1-bit register for signal <in4x_B1<9>>.
Found 1-bit register for signal <in4x_B1<8>>.
Found 1-bit register for signal <in4x_B1<7>>.
Found 1-bit register for signal <in4x_B1<6>>.
Found 1-bit register for signal <in4x_B1<5>>.
Found 1-bit register for signal <in4x_B1<4>>.
Found 1-bit register for signal <in4x_B1<3>>.
Found 1-bit register for signal <in4x_B1<2>>.
Found 1-bit register for signal <in4x_B1<1>>.
Found 1-bit register for signal <in4x_B1<0>>.
Found 1-bit register for signal <in4x_B2<73>>.
Found 1-bit register for signal <in4x_B2<72>>.
Found 1-bit register for signal <in4x_B2<71>>.
Found 1-bit register for signal <in4x_B2<70>>.
Found 1-bit register for signal <in4x_B2<69>>.
Found 1-bit register for signal <in4x_B2<68>>.
Found 1-bit register for signal <in4x_B2<67>>.
Found 1-bit register for signal <in4x_B2<66>>.
Found 1-bit register for signal <in4x_B2<65>>.
Found 1-bit register for signal <in4x_B2<64>>.
Found 1-bit register for signal <in4x_B2<63>>.
Found 1-bit register for signal <in4x_B2<62>>.
Found 1-bit register for signal <in4x_B2<61>>.
Found 1-bit register for signal <in4x_B2<60>>.
Found 1-bit register for signal <in4x_B2<59>>.
Found 1-bit register for signal <in4x_B2<58>>.
Found 1-bit register for signal <in4x_B2<57>>.
Found 1-bit register for signal <in4x_B2<56>>.
Found 1-bit register for signal <in4x_B2<55>>.
Found 1-bit register for signal <in4x_B2<54>>.
Found 1-bit register for signal <in4x_B2<53>>.
Found 1-bit register for signal <in4x_B2<52>>.
Found 1-bit register for signal <in4x_B2<51>>.
Found 1-bit register for signal <in4x_B2<50>>.
Found 1-bit register for signal <in4x_B2<49>>.
Found 1-bit register for signal <in4x_B2<48>>.
Found 1-bit register for signal <in4x_B2<47>>.
Found 1-bit register for signal <in4x_B2<46>>.
Found 1-bit register for signal <in4x_B2<45>>.
Found 1-bit register for signal <in4x_B2<44>>.
Found 1-bit register for signal <in4x_B2<43>>.
Found 1-bit register for signal <in4x_B2<42>>.
Found 1-bit register for signal <in4x_B2<41>>.
Found 1-bit register for signal <in4x_B2<40>>.
Found 1-bit register for signal <in4x_B2<39>>.
Found 1-bit register for signal <in4x_B2<38>>.
Found 1-bit register for signal <in4x_B2<37>>.
Found 1-bit register for signal <in4x_B2<36>>.
Found 1-bit register for signal <in4x_B2<35>>.
Found 1-bit register for signal <in4x_B2<34>>.
Found 1-bit register for signal <in4x_B2<33>>.
Found 1-bit register for signal <in4x_B2<32>>.
Found 1-bit register for signal <in4x_B2<31>>.
Found 1-bit register for signal <in4x_B2<30>>.
Found 1-bit register for signal <in4x_B2<29>>.
Found 1-bit register for signal <in4x_B2<28>>.
Found 1-bit register for signal <in4x_B2<27>>.
Found 1-bit register for signal <in4x_B2<26>>.
Found 1-bit register for signal <in4x_B2<25>>.
Found 1-bit register for signal <in4x_B2<24>>.
Found 1-bit register for signal <in4x_B2<23>>.
Found 1-bit register for signal <in4x_B2<22>>.
Found 1-bit register for signal <in4x_B2<21>>.
Found 1-bit register for signal <in4x_B2<20>>.
Found 1-bit register for signal <in4x_B2<19>>.
Found 1-bit register for signal <in4x_B2<18>>.
Found 1-bit register for signal <in4x_B2<17>>.
Found 1-bit register for signal <in4x_B2<16>>.
Found 1-bit register for signal <in4x_B2<15>>.
Found 1-bit register for signal <in4x_B2<14>>.
Found 1-bit register for signal <in4x_B2<13>>.
Found 1-bit register for signal <in4x_B2<12>>.
Found 1-bit register for signal <in4x_B2<11>>.
Found 1-bit register for signal <in4x_B2<10>>.
Found 1-bit register for signal <in4x_B2<9>>.
Found 1-bit register for signal <in4x_B2<8>>.
Found 1-bit register for signal <in4x_B2<7>>.
Found 1-bit register for signal <in4x_B2<6>>.
Found 1-bit register for signal <in4x_B2<5>>.
Found 1-bit register for signal <in4x_B2<4>>.
Found 1-bit register for signal <in4x_B2<3>>.
Found 1-bit register for signal <in4x_B2<2>>.
Found 1-bit register for signal <in4x_B2<1>>.
Found 1-bit register for signal <in4x_B2<0>>.
Found 1-bit register for signal <in4x_C1<73>>.
Found 1-bit register for signal <in4x_C1<72>>.
Found 1-bit register for signal <in4x_C1<71>>.
Found 1-bit register for signal <in4x_C1<70>>.
Found 1-bit register for signal <in4x_C1<69>>.
Found 1-bit register for signal <in4x_C1<68>>.
Found 1-bit register for signal <in4x_C1<67>>.
Found 1-bit register for signal <in4x_C1<66>>.
Found 1-bit register for signal <in4x_C1<65>>.
Found 1-bit register for signal <in4x_C1<64>>.
Found 1-bit register for signal <in4x_C1<63>>.
Found 1-bit register for signal <in4x_C1<62>>.
Found 1-bit register for signal <in4x_C1<61>>.
Found 1-bit register for signal <in4x_C1<60>>.
Found 1-bit register for signal <in4x_C1<59>>.
Found 1-bit register for signal <in4x_C1<58>>.
Found 1-bit register for signal <in4x_C1<57>>.
Found 1-bit register for signal <in4x_C1<56>>.
Found 1-bit register for signal <in4x_C1<55>>.
Found 1-bit register for signal <in4x_C1<54>>.
Found 1-bit register for signal <in4x_C1<53>>.
Found 1-bit register for signal <in4x_C1<52>>.
Found 1-bit register for signal <in4x_C1<51>>.
Found 1-bit register for signal <in4x_C1<50>>.
Found 1-bit register for signal <in4x_C1<49>>.
Found 1-bit register for signal <in4x_C1<48>>.
Found 1-bit register for signal <in4x_C1<47>>.
Found 1-bit register for signal <in4x_C1<46>>.
Found 1-bit register for signal <in4x_C1<45>>.
Found 1-bit register for signal <in4x_C1<44>>.
Found 1-bit register for signal <in4x_C1<43>>.
Found 1-bit register for signal <in4x_C1<42>>.
Found 1-bit register for signal <in4x_C1<41>>.
Found 1-bit register for signal <in4x_C1<40>>.
Found 1-bit register for signal <in4x_C1<39>>.
Found 1-bit register for signal <in4x_C1<38>>.
Found 1-bit register for signal <in4x_C1<37>>.
Found 1-bit register for signal <in4x_C1<36>>.
Found 1-bit register for signal <in4x_C1<35>>.
Found 1-bit register for signal <in4x_C1<34>>.
Found 1-bit register for signal <in4x_C1<33>>.
Found 1-bit register for signal <in4x_C1<32>>.
Found 1-bit register for signal <in4x_C1<31>>.
Found 1-bit register for signal <in4x_C1<30>>.
Found 1-bit register for signal <in4x_C1<29>>.
Found 1-bit register for signal <in4x_C1<28>>.
Found 1-bit register for signal <in4x_C1<27>>.
Found 1-bit register for signal <in4x_C1<26>>.
Found 1-bit register for signal <in4x_C1<25>>.
Found 1-bit register for signal <in4x_C1<24>>.
Found 1-bit register for signal <in4x_C1<23>>.
Found 1-bit register for signal <in4x_C1<22>>.
Found 1-bit register for signal <in4x_C1<21>>.
Found 1-bit register for signal <in4x_C1<20>>.
Found 1-bit register for signal <in4x_C1<19>>.
Found 1-bit register for signal <in4x_C1<18>>.
Found 1-bit register for signal <in4x_C1<17>>.
Found 1-bit register for signal <in4x_C1<16>>.
Found 1-bit register for signal <in4x_C1<15>>.
Found 1-bit register for signal <in4x_C1<14>>.
Found 1-bit register for signal <in4x_C1<13>>.
Found 1-bit register for signal <in4x_C1<12>>.
Found 1-bit register for signal <in4x_C1<11>>.
Found 1-bit register for signal <in4x_C1<10>>.
Found 1-bit register for signal <in4x_C1<9>>.
Found 1-bit register for signal <in4x_C1<8>>.
Found 1-bit register for signal <in4x_C1<7>>.
Found 1-bit register for signal <in4x_C1<6>>.
Found 1-bit register for signal <in4x_C1<5>>.
Found 1-bit register for signal <in4x_C1<4>>.
Found 1-bit register for signal <in4x_C1<3>>.
Found 1-bit register for signal <in4x_C1<2>>.
Found 1-bit register for signal <in4x_C1<1>>.
Found 1-bit register for signal <in4x_C1<0>>.
Found 1-bit register for signal <in4x_C2<73>>.
Found 1-bit register for signal <in4x_C2<72>>.
Found 1-bit register for signal <in4x_C2<71>>.
Found 1-bit register for signal <in4x_C2<70>>.
Found 1-bit register for signal <in4x_C2<69>>.
Found 1-bit register for signal <in4x_C2<68>>.
Found 1-bit register for signal <in4x_C2<67>>.
Found 1-bit register for signal <in4x_C2<66>>.
Found 1-bit register for signal <in4x_C2<65>>.
Found 1-bit register for signal <in4x_C2<64>>.
Found 1-bit register for signal <in4x_C2<63>>.
Found 1-bit register for signal <in4x_C2<62>>.
Found 1-bit register for signal <in4x_C2<61>>.
Found 1-bit register for signal <in4x_C2<60>>.
Found 1-bit register for signal <in4x_C2<59>>.
Found 1-bit register for signal <in4x_C2<58>>.
Found 1-bit register for signal <in4x_C2<57>>.
Found 1-bit register for signal <in4x_C2<56>>.
Found 1-bit register for signal <in4x_C2<55>>.
Found 1-bit register for signal <in4x_C2<54>>.
Found 1-bit register for signal <in4x_C2<53>>.
Found 1-bit register for signal <in4x_C2<52>>.
Found 1-bit register for signal <in4x_C2<51>>.
Found 1-bit register for signal <in4x_C2<50>>.
Found 1-bit register for signal <in4x_C2<49>>.
Found 1-bit register for signal <in4x_C2<48>>.
Found 1-bit register for signal <in4x_C2<47>>.
Found 1-bit register for signal <in4x_C2<46>>.
Found 1-bit register for signal <in4x_C2<45>>.
Found 1-bit register for signal <in4x_C2<44>>.
Found 1-bit register for signal <in4x_C2<43>>.
Found 1-bit register for signal <in4x_C2<42>>.
Found 1-bit register for signal <in4x_C2<41>>.
Found 1-bit register for signal <in4x_C2<40>>.
Found 1-bit register for signal <in4x_C2<39>>.
Found 1-bit register for signal <in4x_C2<38>>.
Found 1-bit register for signal <in4x_C2<37>>.
Found 1-bit register for signal <in4x_C2<36>>.
Found 1-bit register for signal <in4x_C2<35>>.
Found 1-bit register for signal <in4x_C2<34>>.
Found 1-bit register for signal <in4x_C2<33>>.
Found 1-bit register for signal <in4x_C2<32>>.
Found 1-bit register for signal <in4x_C2<31>>.
Found 1-bit register for signal <in4x_C2<30>>.
Found 1-bit register for signal <in4x_C2<29>>.
Found 1-bit register for signal <in4x_C2<28>>.
Found 1-bit register for signal <in4x_C2<27>>.
Found 1-bit register for signal <in4x_C2<26>>.
Found 1-bit register for signal <in4x_C2<25>>.
Found 1-bit register for signal <in4x_C2<24>>.
Found 1-bit register for signal <in4x_C2<23>>.
Found 1-bit register for signal <in4x_C2<22>>.
Found 1-bit register for signal <in4x_C2<21>>.
Found 1-bit register for signal <in4x_C2<20>>.
Found 1-bit register for signal <in4x_C2<19>>.
Found 1-bit register for signal <in4x_C2<18>>.
Found 1-bit register for signal <in4x_C2<17>>.
Found 1-bit register for signal <in4x_C2<16>>.
Found 1-bit register for signal <in4x_C2<15>>.
Found 1-bit register for signal <in4x_C2<14>>.
Found 1-bit register for signal <in4x_C2<13>>.
Found 1-bit register for signal <in4x_C2<12>>.
Found 1-bit register for signal <in4x_C2<11>>.
Found 1-bit register for signal <in4x_C2<10>>.
Found 1-bit register for signal <in4x_C2<9>>.
Found 1-bit register for signal <in4x_C2<8>>.
Found 1-bit register for signal <in4x_C2<7>>.
Found 1-bit register for signal <in4x_C2<6>>.
Found 1-bit register for signal <in4x_C2<5>>.
Found 1-bit register for signal <in4x_C2<4>>.