main.twr

--------------------------------------------------------------------------------
Release 14.3 Trace  (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2
-n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf xem6010.ucf

Design file:              main.ncd
Physical constraint file: main.pcf
Device,package,speed:     xc6slx45,fgg484,C,-2 (PRODUCTION 1.23 2012-10-12)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

WARNING:Timing:3175 - hi_in<0> does not clock data to hi_out<1>
WARNING:Timing:3225 - Timing constraint COMP "hi_out<1>" OFFSET = OUT 11.93 ns 
   AFTER COMP "hi_in<0>" "RISING"; ignored during timing analysis
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_okHostClk = PERIOD TIMEGRP "okHostClk" 20.83 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  16.000ns.
--------------------------------------------------------------------------------

Paths for end point host/flop3 (SLICE_X31Y4.AX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     19.213ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/flop2 (FF)
  Destination:          host/flop3 (FF)
  Requirement:          20.830ns
  Data Path Delay:      1.344ns (Levels of Logic = 0)
  Clock Path Skew:      -0.238ns (0.516 - 0.754)
  Source Clock:         hi_in_0_IBUFG rising at 0.000ns
  Destination Clock:    hi_in_0_IBUFG rising at 20.830ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/flop2 to host/flop3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y3.DQ       Tcko                  0.525   host/rst2
                                                       host/flop2
    SLICE_X31Y4.AX       net (fanout=2)        0.705   host/rst2
    SLICE_X31Y4.CLK      Tdick                 0.114   host/rst4
                                                       host/flop3
    -------------------------------------------------  ---------------------------
    Total                                      1.344ns (0.639ns logic, 0.705ns route)
                                                       (47.5% logic, 52.5% route)

--------------------------------------------------------------------------------

Paths for end point host/flop4 (SLICE_X31Y4.DX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     19.387ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/flop3 (FF)
  Destination:          host/flop4 (FF)
  Requirement:          20.830ns
  Data Path Delay:      1.408ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         hi_in_0_IBUFG rising at 0.000ns
  Destination Clock:    hi_in_0_IBUFG rising at 20.830ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/flop3 to host/flop4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X31Y4.AQ       Tcko                  0.430   host/rst4
                                                       host/flop3
    SLICE_X31Y4.DX       net (fanout=2)        0.864   host/rst3
    SLICE_X31Y4.CLK      Tdick                 0.114   host/rst4
                                                       host/flop4
    -------------------------------------------------  ---------------------------
    Total                                      1.408ns (0.544ns logic, 0.864ns route)
                                                       (38.6% logic, 61.4% route)

--------------------------------------------------------------------------------

Paths for end point host/flop2 (SLICE_X30Y3.DX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     20.085ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/flop1 (FF)
  Destination:          host/flop2 (FF)
  Requirement:          20.830ns
  Data Path Delay:      1.094ns (Levels of Logic = 0)
  Clock Path Skew:      0.384ns (0.510 - 0.126)
  Source Clock:         hi_in_0_IBUFG rising at 0.000ns
  Destination Clock:    hi_in_0_IBUFG rising at 20.830ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/flop1 to host/flop2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y2.DQ       Tcko                  0.525   host/rst1
                                                       host/flop1
    SLICE_X30Y3.DX       net (fanout=1)        0.484   host/rst1
    SLICE_X30Y3.CLK      Tdick                 0.085   host/rst2
                                                       host/flop2
    -------------------------------------------------  ---------------------------
    Total                                      1.094ns (0.610ns logic, 0.484ns route)
                                                       (55.8% logic, 44.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_okHostClk = PERIOD TIMEGRP "okHostClk" 20.83 ns HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point host/flop2 (SLICE_X30Y3.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.229ns (requirement - (clock path skew + uncertainty - data path))
  Source:               host/flop1 (FF)
  Destination:          host/flop2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.489ns (Levels of Logic = 0)
  Clock Path Skew:      0.260ns (0.260 - 0.000)
  Source Clock:         hi_in_0_IBUFG rising at 20.830ns
  Destination Clock:    hi_in_0_IBUFG rising at 20.830ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: host/flop1 to host/flop2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y2.DQ       Tcko                  0.234   host/rst1
                                                       host/flop1
    SLICE_X30Y3.DX       net (fanout=1)        0.214   host/rst1
    SLICE_X30Y3.CLK      Tckdi       (-Th)    -0.041   host/rst2
                                                       host/flop2
    -------------------------------------------------  ---------------------------
    Total                                      0.489ns (0.275ns logic, 0.214ns route)
                                                       (56.2% logic, 43.8% route)

--------------------------------------------------------------------------------

Paths for end point host/flop4 (SLICE_X31Y4.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.672ns (requirement - (clock path skew + uncertainty - data path))
  Source:               host/flop3 (FF)
  Destination:          host/flop4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.672ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         hi_in_0_IBUFG rising at 20.830ns
  Destination Clock:    hi_in_0_IBUFG rising at 20.830ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: host/flop3 to host/flop4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X31Y4.AQ       Tcko                  0.198   host/rst4
                                                       host/flop3
    SLICE_X31Y4.DX       net (fanout=2)        0.415   host/rst3
    SLICE_X31Y4.CLK      Tckdi       (-Th)    -0.059   host/rst4
                                                       host/flop4
    -------------------------------------------------  ---------------------------
    Total                                      0.672ns (0.257ns logic, 0.415ns route)
                                                       (38.2% logic, 61.8% route)

--------------------------------------------------------------------------------

Paths for end point host/flop3 (SLICE_X31Y4.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.756ns (requirement - (clock path skew + uncertainty - data path))
  Source:               host/flop2 (FF)
  Destination:          host/flop3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.629ns (Levels of Logic = 0)
  Clock Path Skew:      -0.127ns (0.236 - 0.363)
  Source Clock:         hi_in_0_IBUFG rising at 20.830ns
  Destination Clock:    hi_in_0_IBUFG rising at 20.830ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: host/flop2 to host/flop3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X30Y3.DQ       Tcko                  0.234   host/rst2
                                                       host/flop2
    SLICE_X31Y4.AX       net (fanout=2)        0.336   host/rst2
    SLICE_X31Y4.CLK      Tckdi       (-Th)    -0.059   host/rst4
                                                       host/flop3
    -------------------------------------------------  ---------------------------
    Total                                      0.629ns (0.293ns logic, 0.336ns route)
                                                       (46.6% logic, 53.4% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_okHostClk = PERIOD TIMEGRP "okHostClk" 20.83 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.830ns (period - (min low pulse limit / (low pulse / period)))
  Period: 20.830ns
  Low pulse: 10.415ns
  Low pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50)
  Physical resource: host/hi_dcm/CLKIN
  Logical resource: host/hi_dcm/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: host/hi_dcm_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 4.830ns (period - (min high pulse limit / (high pulse / period)))
  Period: 20.830ns
  High pulse: 10.415ns
  High pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50)
  Physical resource: host/hi_dcm/CLKIN
  Logical resource: host/hi_dcm/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: host/hi_dcm_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 16.830ns (period - min period limit)
  Period: 20.830ns
  Min period limit: 4.000ns (250.000MHz) (Tdcmper_CLKIN)
  Physical resource: host/hi_dcm/CLKIN
  Logical resource: host/hi_dcm/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: host/hi_dcm_ML_NEW_DIVCLK
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 10 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 25369 paths analyzed, 318 endpoints analyzed, 40 failing endpoints
 40 timing errors detected. (40 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is 410.251ns.
--------------------------------------------------------------------------------

Paths for end point WS2812controller/GRB_reg_7 (SLICE_X31Y81.C2), 2825 paths
--------------------------------------------------------------------------------
Slack (setup path):     -19.092ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_8_0 (FF)
  Destination:          WS2812controller/GRB_reg_7 (FF)
  Requirement:          0.477ns
  Data Path Delay:      8.112ns (Levels of Logic = 12)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.272ns (2.354 - 13.626)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_8_0 to WS2812controller/GRB_reg_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X27Y88.DQ      Tcko                  0.430   DAC_register_8<0>
                                                       DAC_register_8_0
    SLICE_X26Y87.CX      net (fanout=3)        0.739   DAC_register_8<0>
    SLICE_X26Y87.COUT    Tcxcy                 0.117   DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X26Y88.CIN     net (fanout=1)        0.082   DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X26Y88.COUT    Tbyp                  0.093   DAC_register_8<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.COUT    Tbyp                  0.093   DAC_register_8<7>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y90.COUT    Tbyp                  0.093   DAC_thresh_8<12>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y91.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y91.BMUX    Tcinb                 0.310   DAC_output_8/n0206<17>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X24Y88.B3      net (fanout=50)       0.975   DAC_output_8/n0206<17>
    SLICE_X24Y88.B       Tilo                  0.235   DAC_thresh_8<3>
                                                       DAC_output_8/Mmux_HPF_output81
    SLICE_X24Y89.A5      net (fanout=3)        0.385   DAC_output_8/HPF_output<1>
    SLICE_X24Y89.COUT    Topcya                0.495   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_lutdi
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X24Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X24Y90.CMUX    Tcinc                 0.296   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X27Y89.C6      net (fanout=1)        0.555   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X27Y89.C       Tilo                  0.259   DAC_register_8<13>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<7>
    SLICE_X27Y88.B3      net (fanout=1)        0.554   DAC_output_8/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
    SLICE_X27Y88.B       Tilo                  0.259   DAC_register_8<0>
                                                       Mmux_TTL_out<7>11
    SLICE_X31Y81.A5      net (fanout=2)        1.077   TTL_out_7_OBUF
    SLICE_X31Y81.A       Tilo                  0.259   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133251
    SLICE_X31Y81.C2      net (fanout=1)        0.530   WS2812controller/Mmux__n013325
    SLICE_X31Y81.CLK     Tas                   0.264   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133252
                                                       WS2812controller/GRB_reg_7
    -------------------------------------------------  ---------------------------
    Total                                      8.112ns (3.203ns logic, 4.909ns route)
                                                       (39.5% logic, 60.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     -19.079ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_8_11 (FF)
  Destination:          WS2812controller/GRB_reg_7 (FF)
  Requirement:          0.477ns
  Data Path Delay:      8.092ns (Levels of Logic = 9)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.279ns (2.354 - 13.633)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_8_11 to WS2812controller/GRB_reg_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y91.DQ      Tcko                  0.476   DAC_register_8<11>
                                                       DAC_register_8_11
    SLICE_X26Y90.B5      net (fanout=5)        0.674   DAC_register_8<11>
    SLICE_X26Y90.COUT    Topcyb                0.483   DAC_thresh_8<12>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_lut<13>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y91.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y91.BMUX    Tcinb                 0.310   DAC_output_8/n0206<17>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X24Y88.B3      net (fanout=50)       0.975   DAC_output_8/n0206<17>
    SLICE_X24Y88.B       Tilo                  0.235   DAC_thresh_8<3>
                                                       DAC_output_8/Mmux_HPF_output81
    SLICE_X24Y89.A5      net (fanout=3)        0.385   DAC_output_8/HPF_output<1>
    SLICE_X24Y89.COUT    Topcya                0.495   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_lutdi
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X24Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X24Y90.CMUX    Tcinc                 0.296   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X27Y89.C6      net (fanout=1)        0.555   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X27Y89.C       Tilo                  0.259   DAC_register_8<13>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<7>
    SLICE_X27Y88.B3      net (fanout=1)        0.554   DAC_output_8/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
    SLICE_X27Y88.B       Tilo                  0.259   DAC_register_8<0>
                                                       Mmux_TTL_out<7>11
    SLICE_X31Y81.A5      net (fanout=2)        1.077   TTL_out_7_OBUF
    SLICE_X31Y81.A       Tilo                  0.259   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133251
    SLICE_X31Y81.C2      net (fanout=1)        0.530   WS2812controller/Mmux__n013325
    SLICE_X31Y81.CLK     Tas                   0.264   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133252
                                                       WS2812controller/GRB_reg_7
    -------------------------------------------------  ---------------------------
    Total                                      8.092ns (3.336ns logic, 4.756ns route)
                                                       (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -19.069ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_8_0 (FF)
  Destination:          WS2812controller/GRB_reg_7 (FF)
  Requirement:          0.477ns
  Data Path Delay:      8.089ns (Levels of Logic = 12)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.272ns (2.354 - 13.626)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_8_0 to WS2812controller/GRB_reg_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X27Y88.DQ      Tcko                  0.430   DAC_register_8<0>
                                                       DAC_register_8_0
    SLICE_X26Y87.CX      net (fanout=3)        0.739   DAC_register_8<0>
    SLICE_X26Y87.COUT    Tcxcy                 0.117   DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X26Y88.CIN     net (fanout=1)        0.082   DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X26Y88.COUT    Tbyp                  0.093   DAC_register_8<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.COUT    Tbyp                  0.093   DAC_register_8<7>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y90.COUT    Tbyp                  0.093   DAC_thresh_8<12>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y91.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y91.BMUX    Tcinb                 0.310   DAC_output_8/n0206<17>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X24Y88.B3      net (fanout=50)       0.975   DAC_output_8/n0206<17>
    SLICE_X24Y88.B       Tilo                  0.235   DAC_thresh_8<3>
                                                       DAC_output_8/Mmux_HPF_output81
    SLICE_X24Y89.A5      net (fanout=3)        0.385   DAC_output_8/HPF_output<1>
    SLICE_X24Y89.COUT    Topcya                0.472   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_lut<0>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X24Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X24Y90.CMUX    Tcinc                 0.296   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X27Y89.C6      net (fanout=1)        0.555   DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X27Y89.C       Tilo                  0.259   DAC_register_8<13>
                                                       DAC_output_8/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<7>
    SLICE_X27Y88.B3      net (fanout=1)        0.554   DAC_output_8/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
    SLICE_X27Y88.B       Tilo                  0.259   DAC_register_8<0>
                                                       Mmux_TTL_out<7>11
    SLICE_X31Y81.A5      net (fanout=2)        1.077   TTL_out_7_OBUF
    SLICE_X31Y81.A       Tilo                  0.259   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133251
    SLICE_X31Y81.C2      net (fanout=1)        0.530   WS2812controller/Mmux__n013325
    SLICE_X31Y81.CLK     Tas                   0.264   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133252
                                                       WS2812controller/GRB_reg_7
    -------------------------------------------------  ---------------------------
    Total                                      8.089ns (3.180ns logic, 4.909ns route)
                                                       (39.3% logic, 60.7% route)

--------------------------------------------------------------------------------

Paths for end point WS2812controller/GRB_reg_1 (SLICE_X31Y81.C5), 2825 paths
--------------------------------------------------------------------------------
Slack (setup path):     -18.996ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_2_6 (FF)
  Destination:          WS2812controller/GRB_reg_1 (FF)
  Requirement:          0.477ns
  Data Path Delay:      8.006ns (Levels of Logic = 10)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.282ns (2.354 - 13.636)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_2_6 to WS2812controller/GRB_reg_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y74.DQ      Tcko                  0.476   DAC_register_2<6>
                                                       DAC_register_2_6
    SLICE_X32Y72.A6      net (fanout=6)        0.803   DAC_register_2<6>
    SLICE_X32Y72.COUT    Topcya                0.472   DAC_register_2<3>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_lut<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.COUT    Tbyp                  0.091   TTL_out_user<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.BMUX    Tcinb                 0.277   DAC_register_2<6>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X33Y72.A6      net (fanout=36)       0.616   DAC_output_2/n0206<17>
    SLICE_X33Y72.A       Tilo                  0.259   DAC_output_2/HPF_output<0>
                                                       DAC_output_2/Mmux_HPF_output81
    SLICE_X36Y73.A5      net (fanout=3)        0.857   DAC_output_2/HPF_output<1>
    SLICE_X36Y73.COUT    Topcya                0.495   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_lutdi
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X36Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X36Y74.CMUX    Tcinc                 0.296   SPI_running
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X30Y75.D6      net (fanout=1)        0.637   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X30Y75.D       Tilo                  0.254   DAC_output_2/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<7>
    SLICE_X31Y72.D6      net (fanout=1)        0.541   DAC_output_2/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
    SLICE_X31Y72.D       Tilo                  0.259   data_stream_TTL_out<1>
                                                       Mmux_TTL_out<1>11
    SLICE_X31Y72.C6      net (fanout=2)        0.152   TTL_out_1_OBUF
    SLICE_X31Y72.C       Tilo                  0.259   data_stream_TTL_out<1>
                                                       WS2812controller/Mmux__n0133151
    SLICE_X31Y81.C5      net (fanout=1)        0.880   WS2812controller/Mmux__n013315
    SLICE_X31Y81.CLK     Tas                   0.373   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133153
                                                       WS2812controller/GRB_reg_1
    -------------------------------------------------  ---------------------------
    Total                                      8.006ns (3.511ns logic, 4.495ns route)
                                                       (43.9% logic, 56.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     -18.986ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_2_2 (FF)
  Destination:          WS2812controller/GRB_reg_1 (FF)
  Requirement:          0.477ns
  Data Path Delay:      8.001ns (Levels of Logic = 11)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.277ns (2.354 - 13.631)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_2_2 to WS2812controller/GRB_reg_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X34Y71.CQ      Tcko                  0.525   DAC_register_2<2>
                                                       DAC_register_2_2
    SLICE_X32Y71.AX      net (fanout=4)        0.767   DAC_register_2<2>
    SLICE_X32Y71.COUT    Taxcy                 0.281   DAC_register_2<0>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X32Y72.CIN     net (fanout=1)        0.082   DAC_output_2/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X32Y72.COUT    Tbyp                  0.091   DAC_register_2<3>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.COUT    Tbyp                  0.091   TTL_out_user<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.BMUX    Tcinb                 0.277   DAC_register_2<6>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X33Y72.A6      net (fanout=36)       0.616   DAC_output_2/n0206<17>
    SLICE_X33Y72.A       Tilo                  0.259   DAC_output_2/HPF_output<0>
                                                       DAC_output_2/Mmux_HPF_output81
    SLICE_X36Y73.A5      net (fanout=3)        0.857   DAC_output_2/HPF_output<1>
    SLICE_X36Y73.COUT    Topcya                0.495   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_lutdi
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X36Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X36Y74.CMUX    Tcinc                 0.296   SPI_running
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X30Y75.D6      net (fanout=1)        0.637   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X30Y75.D       Tilo                  0.254   DAC_output_2/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<7>
    SLICE_X31Y72.D6      net (fanout=1)        0.541   DAC_output_2/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
    SLICE_X31Y72.D       Tilo                  0.259   data_stream_TTL_out<1>
                                                       Mmux_TTL_out<1>11
    SLICE_X31Y72.C6      net (fanout=2)        0.152   TTL_out_1_OBUF
    SLICE_X31Y72.C       Tilo                  0.259   data_stream_TTL_out<1>
                                                       WS2812controller/Mmux__n0133151
    SLICE_X31Y81.C5      net (fanout=1)        0.880   WS2812controller/Mmux__n013315
    SLICE_X31Y81.CLK     Tas                   0.373   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133153
                                                       WS2812controller/GRB_reg_1
    -------------------------------------------------  ---------------------------
    Total                                      8.001ns (3.460ns logic, 4.541ns route)
                                                       (43.2% logic, 56.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -18.975ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_2_6 (FF)
  Destination:          WS2812controller/GRB_reg_1 (FF)
  Requirement:          0.477ns
  Data Path Delay:      7.985ns (Levels of Logic = 10)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.282ns (2.354 - 13.636)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_2_6 to WS2812controller/GRB_reg_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y74.DQ      Tcko                  0.476   DAC_register_2<6>
                                                       DAC_register_2_6
    SLICE_X32Y72.A6      net (fanout=6)        0.803   DAC_register_2<6>
    SLICE_X32Y72.COUT    Topcya                0.472   DAC_register_2<3>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_lut<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.COUT    Tbyp                  0.091   TTL_out_user<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.BMUX    Tcinb                 0.277   DAC_register_2<6>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X33Y72.C6      net (fanout=36)       0.719   DAC_output_2/n0206<17>
    SLICE_X33Y72.C       Tilo                  0.259   DAC_output_2/HPF_output<0>
                                                       DAC_output_2/Mmux_HPF_output17
    SLICE_X36Y73.A4      net (fanout=3)        0.733   DAC_output_2/HPF_output<0>
    SLICE_X36Y73.COUT    Topcya                0.495   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_lutdi
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X36Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<3>
    SLICE_X36Y74.CMUX    Tcinc                 0.296   SPI_running
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X30Y75.D6      net (fanout=1)        0.637   DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<6>
    SLICE_X30Y75.D       Tilo                  0.254   DAC_output_2/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
                                                       DAC_output_2/Mcompar_DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o_cy<7>
    SLICE_X31Y72.D6      net (fanout=1)        0.541   DAC_output_2/DAC_thrsh[15]_DAC_input_offset[15]_LessThan_12_o
    SLICE_X31Y72.D       Tilo                  0.259   data_stream_TTL_out<1>
                                                       Mmux_TTL_out<1>11
    SLICE_X31Y72.C6      net (fanout=2)        0.152   TTL_out_1_OBUF
    SLICE_X31Y72.C       Tilo                  0.259   data_stream_TTL_out<1>
                                                       WS2812controller/Mmux__n0133151
    SLICE_X31Y81.C5      net (fanout=1)        0.880   WS2812controller/Mmux__n013315
    SLICE_X31Y81.CLK     Tas                   0.373   WS2812controller/GRB_reg<1>
                                                       WS2812controller/Mmux__n0133153
                                                       WS2812controller/GRB_reg_1
    -------------------------------------------------  ---------------------------
    Total                                      7.985ns (3.511ns logic, 4.474ns route)
                                                       (44.0% logic, 56.0% route)

--------------------------------------------------------------------------------

Paths for end point WS2812controller/GRB_reg_2 (SLICE_X49Y93.D5), 2821 paths
--------------------------------------------------------------------------------
Slack (setup path):     -18.665ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_3_11 (FF)
  Destination:          WS2812controller/GRB_reg_2 (FF)
  Requirement:          0.477ns
  Data Path Delay:      7.694ns (Levels of Logic = 8)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.263ns (2.351 - 13.614)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_3_11 to WS2812controller/GRB_reg_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X53Y94.DQ      Tcko                  0.430   DAC_register_3<11>
                                                       DAC_register_3_11
    SLICE_X52Y92.B2      net (fanout=5)        0.922   DAC_register_3<11>
    SLICE_X52Y92.COUT    Topcyb                0.483   DAC_register_3<6>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_lut<13>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X52Y93.CIN     net (fanout=1)        0.003   DAC_output_3/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X52Y93.BMUX    Tcinb                 0.310   DAC_output_3/HPF_output<8>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X53Y90.D6      net (fanout=50)       0.674   DAC_output_3/n0206<17>
    SLICE_X53Y90.D       Tilo                  0.259   DAC_thresh_3<7>
                                                       DAC_output_3/Mmux_HPF_output81
    SLICE_X52Y94.A1      net (fanout=3)        1.420   DAC_output_3/HPF_output<1>
    SLICE_X52Y94.COUT    Topcya                0.482   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_lutdi
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
    SLICE_X52Y95.CIN     net (fanout=1)        0.003   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
    SLICE_X52Y95.CMUX    Tcinc                 0.302   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
    SLICE_X51Y93.C6      net (fanout=1)        0.833   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
    SLICE_X51Y93.C       Tilo                  0.259   data_stream_TTL_out<2>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<7>
    SLICE_X51Y93.D5      net (fanout=1)        0.234   DAC_output_3/DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o
    SLICE_X51Y93.D       Tilo                  0.259   data_stream_TTL_out<2>
                                                       Mmux_TTL_out<2>11
    SLICE_X49Y93.D5      net (fanout=2)        0.448   TTL_out_2_OBUF
    SLICE_X49Y93.CLK     Tas                   0.373   WS2812controller/GRB_reg<2>
                                                       WS2812controller/Mmux__n0133201
                                                       WS2812controller/GRB_reg_2
    -------------------------------------------------  ---------------------------
    Total                                      7.694ns (3.157ns logic, 4.537ns route)
                                                       (41.0% logic, 59.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     -18.657ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_3_11 (FF)
  Destination:          WS2812controller/GRB_reg_2 (FF)
  Requirement:          0.477ns
  Data Path Delay:      7.686ns (Levels of Logic = 8)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.263ns (2.351 - 13.614)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_3_11 to WS2812controller/GRB_reg_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X53Y94.DQ      Tcko                  0.430   DAC_register_3<11>
                                                       DAC_register_3_11
    SLICE_X52Y92.B2      net (fanout=5)        0.922   DAC_register_3<11>
    SLICE_X52Y92.COUT    Topcyb                0.483   DAC_register_3<6>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_lut<13>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X52Y93.CIN     net (fanout=1)        0.003   DAC_output_3/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X52Y93.BMUX    Tcinb                 0.310   DAC_output_3/HPF_output<8>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X53Y90.D6      net (fanout=50)       0.674   DAC_output_3/n0206<17>
    SLICE_X53Y90.D       Tilo                  0.259   DAC_thresh_3<7>
                                                       DAC_output_3/Mmux_HPF_output81
    SLICE_X52Y94.A1      net (fanout=3)        1.420   DAC_output_3/HPF_output<1>
    SLICE_X52Y94.COUT    Topcya                0.474   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_lut<0>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
    SLICE_X52Y95.CIN     net (fanout=1)        0.003   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
    SLICE_X52Y95.CMUX    Tcinc                 0.302   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
    SLICE_X51Y93.C6      net (fanout=1)        0.833   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
    SLICE_X51Y93.C       Tilo                  0.259   data_stream_TTL_out<2>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<7>
    SLICE_X51Y93.D5      net (fanout=1)        0.234   DAC_output_3/DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o
    SLICE_X51Y93.D       Tilo                  0.259   data_stream_TTL_out<2>
                                                       Mmux_TTL_out<2>11
    SLICE_X49Y93.D5      net (fanout=2)        0.448   TTL_out_2_OBUF
    SLICE_X49Y93.CLK     Tas                   0.373   WS2812controller/GRB_reg<2>
                                                       WS2812controller/Mmux__n0133201
                                                       WS2812controller/GRB_reg_2
    -------------------------------------------------  ---------------------------
    Total                                      7.686ns (3.149ns logic, 4.537ns route)
                                                       (41.0% logic, 59.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     -18.562ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_3_1 (FF)
  Destination:          WS2812controller/GRB_reg_2 (FF)
  Requirement:          0.477ns
  Data Path Delay:      7.598ns (Levels of Logic = 11)(Component delays alone exceeds constraint)
  Clock Path Skew:      -11.256ns (2.351 - 13.607)
  Source Clock:         dataclk rising at 59.523ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 60.000ns
  Clock Uncertainty:    0.185ns

  Clock Uncertainty:          0.185ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: DAC_register_3_1 to WS2812controller/GRB_reg_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y90.CQ      Tcko                  0.525   DAC_register_3<0>
                                                       DAC_register_3_1
    SLICE_X52Y89.DX      net (fanout=3)        0.817   DAC_register_3<1>
    SLICE_X52Y89.COUT    Tdxcy                 0.109   DAC_register_3<2>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X52Y90.CIN     net (fanout=1)        0.003   DAC_output_3/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X52Y90.COUT    Tbyp                  0.093   DAC_register_3<0>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X52Y91.CIN     net (fanout=1)        0.003   DAC_output_3/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X52Y91.COUT    Tbyp                  0.093   DAC_register_3<5>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X52Y92.CIN     net (fanout=1)        0.003   DAC_output_3/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X52Y92.COUT    Tbyp                  0.093   DAC_register_3<6>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X52Y93.CIN     net (fanout=1)        0.003   DAC_output_3/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X52Y93.BMUX    Tcinb                 0.310   DAC_output_3/HPF_output<8>
                                                       DAC_output_3/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X53Y90.D6      net (fanout=50)       0.674   DAC_output_3/n0206<17>
    SLICE_X53Y90.D       Tilo                  0.259   DAC_thresh_3<7>
                                                       DAC_output_3/Mmux_HPF_output81
    SLICE_X52Y94.A1      net (fanout=3)        1.420   DAC_output_3/HPF_output<1>
    SLICE_X52Y94.COUT    Topcya                0.482   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_lutdi
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
    SLICE_X52Y95.CIN     net (fanout=1)        0.003   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<3>
    SLICE_X52Y95.CMUX    Tcinc                 0.302   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
    SLICE_X51Y93.C6      net (fanout=1)        0.833   DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<6>
    SLICE_X51Y93.C       Tilo                  0.259   data_stream_TTL_out<2>
                                                       DAC_output_3/Mcompar_DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o_cy<7>
    SLICE_X51Y93.D5      net (fanout=1)        0.234   DAC_output_3/DAC_input_offset[15]_DAC_thrsh[15]_LessThan_13_o
    SLICE_X51Y93.D       Tilo                  0.259   data_stream_TTL_out<2>
                                                       Mmux_TTL_out<2>11
    SLICE_X49Y93.D5      net (fanout=2)        0.448   TTL_out_2_OBUF
    SLICE_X49Y93.CLK     Tas                   0.373   WS2812controller/GRB_reg<2>
                                                       WS2812controller/Mmux__n0133201
                                                       WS2812controller/GRB_reg_2
    -------------------------------------------------  ---------------------------
    Total                                      7.598ns (3.157ns logic, 4.441ns route)
                                                       (41.6% logic, 58.4% route)

--------------------------------------------------------------------------------

Hold Paths: TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 10 ns HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point WS2812controller/led_bit (SLICE_X34Y76.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.458ns (requirement - (clock path skew + uncertainty - data path))
  Source:               WS2812controller/led_bit (FF)
  Destination:          WS2812controller/led_bit (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.458ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 10.000ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: WS2812controller/led_bit to WS2812controller/led_bit
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X34Y76.AQ      Tcko                  0.234   WS2812controller/led_bit
                                                       WS2812controller/led_bit
    SLICE_X34Y76.A6      net (fanout=2)        0.027   WS2812controller/led_bit
    SLICE_X34Y76.CLK     Tah         (-Th)    -0.197   WS2812controller/led_bit
                                                       WS2812controller/led_bit_rstpot
                                                       WS2812controller/led_bit
    -------------------------------------------------  ---------------------------
    Total                                      0.458ns (0.431ns logic, 0.027ns route)
                                                       (94.1% logic, 5.9% route)

--------------------------------------------------------------------------------

Paths for end point WS2812controller/GRB_state_0 (SLICE_X33Y83.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.460ns (requirement - (clock path skew + uncertainty - data path))
  Source:               WS2812controller/GRB_state_0 (FF)
  Destination:          WS2812controller/GRB_state_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.460ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 10.000ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: WS2812controller/GRB_state_0 to WS2812controller/GRB_state_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y83.AQ      Tcko                  0.198   WS2812controller/GRB_state<4>
                                                       WS2812controller/GRB_state_0
    SLICE_X33Y83.A6      net (fanout=10)       0.047   WS2812controller/GRB_state<0>
    SLICE_X33Y83.CLK     Tah         (-Th)    -0.215   WS2812controller/GRB_state<4>
                                                       WS2812controller/Mcount_GRB_state_xor<0>11_INV_0
                                                       WS2812controller/GRB_state_0
    -------------------------------------------------  ---------------------------
    Total                                      0.460ns (0.413ns logic, 0.047ns route)
                                                       (89.8% logic, 10.2% route)

--------------------------------------------------------------------------------

Paths for end point WS2812controller/LED_state_15 (SLICE_X36Y81.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.464ns (requirement - (clock path skew + uncertainty - data path))
  Source:               WS2812controller/LED_state_15 (FF)
  Destination:          WS2812controller/LED_state_15 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.464ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 10.000ns
  Destination Clock:    SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg_BUFG rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: WS2812controller/LED_state_15 to WS2812controller/LED_state_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y81.DQ      Tcko                  0.200   WS2812controller/LED_state<15>
                                                       WS2812controller/LED_state_15
    SLICE_X36Y81.D6      net (fanout=3)        0.027   WS2812controller/LED_state<15>
    SLICE_X36Y81.CLK     Tah         (-Th)    -0.237   WS2812controller/LED_state<15>
                                                       WS2812controller/LED_state<15>_rt
                                                       WS2812controller/Mcount_LED_state_xor<15>
                                                       WS2812controller/LED_state_15
    -------------------------------------------------  ---------------------------
    Total                                      0.464ns (0.437ns logic, 0.027ns route)
                                                       (94.2% logic, 5.8% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 10 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.548ns (period - min period limit)
  Period: 1.600ns
  Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Logical resource: SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Location pin: PLL_ADV_X0Y1.CLKOUT0
  Clock network: SDRAM_FIFO_inst/memc3_infrastructure_inst/clk_2x_0
--------------------------------------------------------------------------------
Slack: 0.548ns (period - min period limit)
  Period: 1.600ns
  Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv/CLKOUT1
  Logical resource: SDRAM_FIFO_inst/memc3_infrastructure_inst/u_pll_adv/CLKOUT1
  Location pin: PLL_ADV_X0Y1.CLKOUT1
  Clock network: SDRAM_FIFO_inst/memc3_infrastructure_inst/clk_2x_180
--------------------------------------------------------------------------------
Slack: 4.660ns (period - (min low pulse limit / (low pulse / period)))
  Period: 10.000ns
  Low pulse: 5.000ns
  Low pulse limit: 2.670ns (Tdcmpw_CLKIN_100_150)
  Physical resource: variable_freq_clk_generator_inst/DCM_CLKGEN_1/CLKIN
  Logical resource: variable_freq_clk_generator_inst/DCM_CLKGEN_1/CLKIN
  Location pin: DCM_X0Y6.CLKIN
  Clock network: SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_host_dcm_clk0 = PERIOD TIMEGRP "host_dcm_clk0" 
TS_okHostClk HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 42956 paths analyzed, 7739 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  16.392ns.
--------------------------------------------------------------------------------

Paths for end point host/delays[15].fdreout0 (OLOGIC_X25Y1.D1), 30 paths
--------------------------------------------------------------------------------
Slack (setup path):     4.438ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_1 (FF)
  Destination:          host/delays[15].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      16.781ns (Levels of Logic = 4)
  Clock Path Skew:      0.524ns (1.170 - 0.646)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_1 to host/delays[15].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y20.AQ      Tcko                  0.430   ok1<20>
                                                       host/core0/core0/ti_addr_1
    SLICE_X40Y11.D5      net (fanout=54)       2.791   ok1<17>
    SLICE_X40Y11.D       Tilo                  0.235   host/okCH<0>
                                                       poa0/ok2<16>81
    SLICE_X40Y11.C5      net (fanout=1)        0.431   poa0/ok2<16>8
    SLICE_X40Y11.C       Tilo                  0.235   host/okCH<0>
                                                       poa0/ok2<16>83
    SLICE_X9Y46.A3       net (fanout=17)       4.538   host/core0/core0/hi_busy_rstpot
    SLICE_X9Y46.A        Tilo                  0.259   wireOR/ok2<91>4
                                                       wireOR/ok2<100>7
    SLICE_X9Y46.C2       net (fanout=1)        0.530   ok2<15>
    SLICE_X9Y46.CMUX     Tilo                  0.337   wireOR/ok2<91>4
                                                       host/core0/core0/Mmux_hi_dataout171
    OLOGIC_X25Y1.D1      net (fanout=1)        5.817   host/okCH<18>
    OLOGIC_X25Y1.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<15>
                                                       host/delays[15].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     16.781ns (2.674ns logic, 14.107ns route)
                                                       (15.9% logic, 84.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.794ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_4 (FF)
  Destination:          host/delays[15].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      16.425ns (Levels of Logic = 3)
  Clock Path Skew:      0.524ns (1.170 - 0.646)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_4 to host/delays[15].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y20.DQ      Tcko                  0.430   ok1<20>
                                                       host/core0/core0/ti_addr_4
    SLICE_X40Y11.C4      net (fanout=52)       3.101   ok1<20>
    SLICE_X40Y11.C       Tilo                  0.235   host/okCH<0>
                                                       poa0/ok2<16>83
    SLICE_X9Y46.A3       net (fanout=17)       4.538   host/core0/core0/hi_busy_rstpot
    SLICE_X9Y46.A        Tilo                  0.259   wireOR/ok2<91>4
                                                       wireOR/ok2<100>7
    SLICE_X9Y46.C2       net (fanout=1)        0.530   ok2<15>
    SLICE_X9Y46.CMUX     Tilo                  0.337   wireOR/ok2<91>4
                                                       host/core0/core0/Mmux_hi_dataout171
    OLOGIC_X25Y1.D1      net (fanout=1)        5.817   host/okCH<18>
    OLOGIC_X25Y1.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<15>
                                                       host/delays[15].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     16.425ns (2.439ns logic, 13.986ns route)
                                                       (14.8% logic, 85.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.959ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_6 (FF)
  Destination:          host/delays[15].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      16.258ns (Levels of Logic = 4)
  Clock Path Skew:      0.522ns (1.170 - 0.648)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_6 to host/delays[15].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y19.BQ      Tcko                  0.430   ok1<23>
                                                       host/core0/core0/ti_addr_6
    SLICE_X40Y11.D3      net (fanout=50)       2.268   ok1<22>
    SLICE_X40Y11.D       Tilo                  0.235   host/okCH<0>
                                                       poa0/ok2<16>81
    SLICE_X40Y11.C5      net (fanout=1)        0.431   poa0/ok2<16>8
    SLICE_X40Y11.C       Tilo                  0.235   host/okCH<0>
                                                       poa0/ok2<16>83
    SLICE_X9Y46.A3       net (fanout=17)       4.538   host/core0/core0/hi_busy_rstpot
    SLICE_X9Y46.A        Tilo                  0.259   wireOR/ok2<91>4
                                                       wireOR/ok2<100>7
    SLICE_X9Y46.C2       net (fanout=1)        0.530   ok2<15>
    SLICE_X9Y46.CMUX     Tilo                  0.337   wireOR/ok2<91>4
                                                       host/core0/core0/Mmux_hi_dataout171
    OLOGIC_X25Y1.D1      net (fanout=1)        5.817   host/okCH<18>
    OLOGIC_X25Y1.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<15>
                                                       host/delays[15].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     16.258ns (2.674ns logic, 13.584ns route)
                                                       (16.4% logic, 83.6% route)

--------------------------------------------------------------------------------

Paths for end point host/delays[2].fdreout0 (OLOGIC_X14Y3.D1), 57 paths
--------------------------------------------------------------------------------
Slack (setup path):     4.726ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_0 (FF)
  Destination:          host/delays[2].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      16.462ns (Levels of Logic = 4)
  Clock Path Skew:      0.493ns (1.171 - 0.678)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_0 to host/delays[2].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y15.DQ      Tcko                  0.525   ok1<16>
                                                       host/core0/core0/ti_addr_0
    SLICE_X19Y55.A1      net (fanout=55)       5.502   ok1<16>
    SLICE_X19Y55.A       Tilo                  0.259   ep1bwirein<3>
                                                       wo25/ti_addr[7]_ep_addr[7]_equal_2_o83
    SLICE_X19Y43.A3      net (fanout=4)        1.455   wo25/ti_addr[7]_ep_addr[7]_equal_2_o
    SLICE_X19Y43.A       Tilo                  0.259   wireOR/ok2<87>5
                                                       wireOR/ok2<87>6
    SLICE_X8Y43.A2       net (fanout=1)        1.345   wireOR/ok2<87>5
    SLICE_X8Y43.A        Tilo                  0.235   wireOR/ok2<87>4
                                                       wireOR/ok2<87>7
    SLICE_X8Y43.C1       net (fanout=1)        0.538   ok2<2>
    SLICE_X8Y43.CMUX     Tilo                  0.298   wireOR/ok2<87>4
                                                       host/core0/core0/Mmux_hi_dataout1411
    OLOGIC_X14Y3.D1      net (fanout=1)        4.868   host/okCH<5>
    OLOGIC_X14Y3.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<2>
                                                       host/delays[2].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     16.462ns (2.754ns logic, 13.708ns route)
                                                       (16.7% logic, 83.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.139ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_3 (FF)
  Destination:          host/delays[2].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      16.081ns (Levels of Logic = 4)
  Clock Path Skew:      0.525ns (1.171 - 0.646)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_3 to host/delays[2].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y20.CQ      Tcko                  0.430   ok1<20>
                                                       host/core0/core0/ti_addr_3
    SLICE_X19Y55.A4      net (fanout=53)       5.216   ok1<19>
    SLICE_X19Y55.A       Tilo                  0.259   ep1bwirein<3>
                                                       wo25/ti_addr[7]_ep_addr[7]_equal_2_o83
    SLICE_X19Y43.A3      net (fanout=4)        1.455   wo25/ti_addr[7]_ep_addr[7]_equal_2_o
    SLICE_X19Y43.A       Tilo                  0.259   wireOR/ok2<87>5
                                                       wireOR/ok2<87>6
    SLICE_X8Y43.A2       net (fanout=1)        1.345   wireOR/ok2<87>5
    SLICE_X8Y43.A        Tilo                  0.235   wireOR/ok2<87>4
                                                       wireOR/ok2<87>7
    SLICE_X8Y43.C1       net (fanout=1)        0.538   ok2<2>
    SLICE_X8Y43.CMUX     Tilo                  0.298   wireOR/ok2<87>4
                                                       host/core0/core0/Mmux_hi_dataout1411
    OLOGIC_X14Y3.D1      net (fanout=1)        4.868   host/okCH<5>
    OLOGIC_X14Y3.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<2>
                                                       host/delays[2].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     16.081ns (2.659ns logic, 13.422ns route)
                                                       (16.5% logic, 83.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.498ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_2 (FF)
  Destination:          host/delays[2].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      15.722ns (Levels of Logic = 4)
  Clock Path Skew:      0.525ns (1.171 - 0.646)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_2 to host/delays[2].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y20.BQ      Tcko                  0.430   ok1<20>
                                                       host/core0/core0/ti_addr_2
    SLICE_X19Y55.A2      net (fanout=53)       4.857   ok1<18>
    SLICE_X19Y55.A       Tilo                  0.259   ep1bwirein<3>
                                                       wo25/ti_addr[7]_ep_addr[7]_equal_2_o83
    SLICE_X19Y43.A3      net (fanout=4)        1.455   wo25/ti_addr[7]_ep_addr[7]_equal_2_o
    SLICE_X19Y43.A       Tilo                  0.259   wireOR/ok2<87>5
                                                       wireOR/ok2<87>6
    SLICE_X8Y43.A2       net (fanout=1)        1.345   wireOR/ok2<87>5
    SLICE_X8Y43.A        Tilo                  0.235   wireOR/ok2<87>4
                                                       wireOR/ok2<87>7
    SLICE_X8Y43.C1       net (fanout=1)        0.538   ok2<2>
    SLICE_X8Y43.CMUX     Tilo                  0.298   wireOR/ok2<87>4
                                                       host/core0/core0/Mmux_hi_dataout1411
    OLOGIC_X14Y3.D1      net (fanout=1)        4.868   host/okCH<5>
    OLOGIC_X14Y3.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<2>
                                                       host/delays[2].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     15.722ns (2.659ns logic, 13.063ns route)
                                                       (16.9% logic, 83.1% route)

--------------------------------------------------------------------------------

Paths for end point host/delays[14].fdreout0 (OLOGIC_X21Y3.D1), 30 paths
--------------------------------------------------------------------------------
Slack (setup path):     5.622ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_1 (FF)
  Destination:          host/delays[14].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      15.596ns (Levels of Logic = 4)
  Clock Path Skew:      0.523ns (1.169 - 0.646)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_1 to host/delays[14].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y20.AQ      Tcko                  0.430   ok1<20>
                                                       host/core0/core0/ti_addr_1
    SLICE_X40Y11.D5      net (fanout=54)       2.791   ok1<17>
    SLICE_X40Y11.D       Tilo                  0.235   host/okCH<0>
                                                       poa0/ok2<16>81
    SLICE_X40Y11.C5      net (fanout=1)        0.431   poa0/ok2<16>8
    SLICE_X40Y11.C       Tilo                  0.235   host/okCH<0>
                                                       poa0/ok2<16>83
    SLICE_X12Y39.A2      net (fanout=17)       3.728   host/core0/core0/hi_busy_rstpot
    SLICE_X12Y39.A       Tilo                  0.235   host/okCH<16>
                                                       wireOR/ok2<99>7
    SLICE_X12Y39.C2      net (fanout=1)        0.875   ok2<14>
    SLICE_X12Y39.CMUX    Tilo                  0.298   host/okCH<16>
                                                       host/core0/core0/Mmux_hi_dataout211
    OLOGIC_X21Y3.D1      net (fanout=1)        5.160   host/okCH<17>
    OLOGIC_X21Y3.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<14>
                                                       host/delays[14].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     15.596ns (2.611ns logic, 12.985ns route)
                                                       (16.7% logic, 83.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.978ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_4 (FF)
  Destination:          host/delays[14].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      15.240ns (Levels of Logic = 3)
  Clock Path Skew:      0.523ns (1.169 - 0.646)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_4 to host/delays[14].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y20.DQ      Tcko                  0.430   ok1<20>
                                                       host/core0/core0/ti_addr_4
    SLICE_X40Y11.C4      net (fanout=52)       3.101   ok1<20>
    SLICE_X40Y11.C       Tilo                  0.235   host/okCH<0>
                                                       poa0/ok2<16>83
    SLICE_X12Y39.A2      net (fanout=17)       3.728   host/core0/core0/hi_busy_rstpot
    SLICE_X12Y39.A       Tilo                  0.235   host/okCH<16>
                                                       wireOR/ok2<99>7
    SLICE_X12Y39.C2      net (fanout=1)        0.875   ok2<14>
    SLICE_X12Y39.CMUX    Tilo                  0.298   host/okCH<16>
                                                       host/core0/core0/Mmux_hi_dataout211
    OLOGIC_X21Y3.D1      net (fanout=1)        5.160   host/okCH<17>
    OLOGIC_X21Y3.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<14>
                                                       host/delays[14].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     15.240ns (2.376ns logic, 12.864ns route)
                                                       (15.6% logic, 84.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     6.103ns (requirement - (data path - clock path skew + uncertainty))
  Source:               host/core0/core0/ti_addr_7 (FF)
  Destination:          host/delays[14].fdreout0 (FF)
  Requirement:          20.830ns
  Data Path Delay:      15.113ns (Levels of Logic = 3)
  Clock Path Skew:      0.521ns (1.169 - 0.648)
  Source Clock:         ok1<24> rising at 0.000ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.135ns

  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: host/core0/core0/ti_addr_7 to host/delays[14].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y19.CQ      Tcko                  0.430   ok1<23>
                                                       host/core0/core0/ti_addr_7
    SLICE_X18Y46.C2      net (fanout=49)       4.589   ok1<23>
    SLICE_X18Y46.C       Tilo                  0.255   ok2x<51>
                                                       wo23/ti_addr[7]_ep_addr[7]_equal_2_o83
    SLICE_X12Y39.A1      net (fanout=16)       2.093   wo23/ti_addr[7]_ep_addr[7]_equal_2_o
    SLICE_X12Y39.A       Tilo                  0.235   host/okCH<16>
                                                       wireOR/ok2<99>7
    SLICE_X12Y39.C2      net (fanout=1)        0.875   ok2<14>
    SLICE_X12Y39.CMUX    Tilo                  0.298   host/okCH<16>
                                                       host/core0/core0/Mmux_hi_dataout211
    OLOGIC_X21Y3.D1      net (fanout=1)        5.160   host/okCH<17>
    OLOGIC_X21Y3.CLK0    Todck                 1.178   host/fdreout0_hi_dataout<14>
                                                       host/delays[14].fdreout0
    -------------------------------------------------  ---------------------------
    Total                                     15.113ns (2.396ns logic, 12.717ns route)
                                                       (15.9% logic, 84.1% route)

--------------------------------------------------------------------------------

Hold Paths: TS_host_dcm_clk0 = PERIOD TIMEGRP "host_dcm_clk0" TS_okHostClk HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/c0/baud_count_2 (SLICE_X16Y4.A5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.378ns (requirement - (clock path skew + uncertainty - data path))
  Source:               host/core0/core0/a0/c0/baud_count_3 (FF)
  Destination:          host/core0/core0/a0/c0/baud_count_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.380ns (Levels of Logic = 1)
  Clock Path Skew:      0.002ns (0.039 - 0.037)
  Source Clock:         ok1<24> rising at 20.830ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: host/core0/core0/a0/c0/baud_count_3 to host/core0/core0/a0/c0/baud_count_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y4.BQ       Tcko                  0.198   host/core0/core0/a0/c0/baud_count<3>
                                                       host/core0/core0/a0/c0/baud_count_3
    SLICE_X16Y4.A5       net (fanout=3)        0.061   host/core0/core0/a0/c0/baud_count<3>
    SLICE_X16Y4.CLK      Tah         (-Th)    -0.121   host/core0/core0/a0/c0/baud_en
                                                       host/core0/core0/a0/c0/Mcount_baud_count_xor<2>11
                                                       host/core0/core0/a0/c0/baud_count_2
    -------------------------------------------------  ---------------------------
    Total                                      0.380ns (0.319ns logic, 0.061ns route)
                                                       (83.9% logic, 16.1% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 (SLICE_X0Y41.C5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.382ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.382ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         ok1<24> rising at 20.830ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 to SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y41.CQ       Tcko                  0.200   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<3>
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2
    SLICE_X0Y41.C5       net (fanout=1)        0.061   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<2>
    SLICE_X0Y41.CLK      Tah         (-Th)    -0.121   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<3>
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<2>_rt
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2
    -------------------------------------------------  ---------------------------
    Total                                      0.382ns (0.321ns logic, 0.061ns route)
                                                       (84.0% logic, 16.0% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 (SLICE_X0Y41.B5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.392ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.392ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         ok1<24> rising at 20.830ns
  Destination Clock:    ok1<24> rising at 20.830ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 to SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y41.BQ       Tcko                  0.200   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<3>
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1
    SLICE_X0Y41.B5       net (fanout=1)        0.071   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<1>
    SLICE_X0Y41.CLK      Tah         (-Th)    -0.121   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<3>
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<1>_rt
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1
    -------------------------------------------------  ---------------------------
    Total                                      0.392ns (0.321ns logic, 0.071ns route)
                                                       (81.9% logic, 18.1% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_host_dcm_clk0 = PERIOD TIMEGRP "host_dcm_clk0" TS_okHostClk HIGH 50%;
--------------------------------------------------------------------------------
Slack: 14.840ns (period - min period limit)
  Period: 20.830ns
  Min period limit: 5.990ns (166.945MHz) (Tdcmper_PSCLK)
  Physical resource: variable_freq_clk_generator_inst/DCM_CLKGEN_1/PROGCLK
  Logical resource: variable_freq_clk_generator_inst/DCM_CLKGEN_1/PROGCLK
  Location pin: DCM_X0Y6.PSCLK
  Clock network: ok1<24>
--------------------------------------------------------------------------------
Slack: 17.260ns (period - min period limit)
  Period: 20.830ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: RAM_bank_3/RAM_block_10/RAMB16BWER_inst/CLKA
  Logical resource: RAM_bank_3/RAM_block_10/RAMB16BWER_inst/CLKA
  Location pin: RAMB16_X2Y22.CLKA
  Clock network: ok1<24>
--------------------------------------------------------------------------------
Slack: 17.260ns (period - min period limit)
  Period: 20.830ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: RAM_bank_2/RAM_block_11/RAMB16BWER_inst/CLKA
  Logical resource: RAM_bank_2/RAM_block_11/RAMB16BWER_inst/CLKA
  Location pin: RAMB16_X3Y8.CLKA
  Clock network: ok1<24>
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD       
  TIMEGRP         
"SDRAM_FIFO_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in"         
TS_SYS_CLK3 / 0.78125 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 13623 paths analyzed, 1298 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   9.919ns.
--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train (SLICE_X11Y107.SR), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.670ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1 (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train (FF)
  Requirement:          6.400ns
  Data Path Delay:      4.035ns (Levels of Logic = 1)
  Clock Path Skew:      -0.432ns (2.001 - 2.433)
  Source Clock:         SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.263ns

  Clock Uncertainty:          0.263ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.276ns
    Phase Error (PE):           0.120ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1 to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y80.AQ       Tcko                  0.430   SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_3
                                                       SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1
    SLICE_X6Y87.C3       net (fanout=1)        1.014   SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1
    SLICE_X6Y87.C        Tilo                  0.255   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1
    SLICE_X11Y107.SR     net (fanout=56)       2.069   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst
    SLICE_X11Y107.CLK    Trck                  0.267   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train
    -------------------------------------------------  ---------------------------
    Total                                      4.035ns (0.952ns logic, 3.083ns route)
                                                       (23.6% logic, 76.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     6.632ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train (FF)
  Requirement:          12.800ns
  Data Path Delay:      5.948ns (Levels of Logic = 1)
  Clock Path Skew:      -0.077ns (0.594 - 0.671)
  Source Clock:         SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.143ns

  Clock Uncertainty:          0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.276ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y64.AQ      Tcko                  0.476   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X6Y87.C2       net (fanout=3)        2.881   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X6Y87.C        Tilo                  0.255   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1
    SLICE_X11Y107.SR     net (fanout=56)       2.069   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst
    SLICE_X11Y107.CLK    Trck                  0.267   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train
    -------------------------------------------------  ---------------------------
    Total                                      5.948ns (0.998ns logic, 4.950ns route)
                                                       (16.8% logic, 83.2% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13 (SLICE_X12Y96.SR), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.972ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1 (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13 (FF)
  Requirement:          6.400ns
  Data Path Delay:      3.738ns (Levels of Logic = 1)
  Clock Path Skew:      -0.427ns (2.006 - 2.433)
  Source Clock:         SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.263ns

  Clock Uncertainty:          0.263ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.276ns
    Phase Error (PE):           0.120ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1 to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y80.AQ       Tcko                  0.430   SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_3
                                                       SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1
    SLICE_X6Y87.C3       net (fanout=1)        1.014   SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1
    SLICE_X6Y87.C        Tilo                  0.255   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1
    SLICE_X12Y96.SR      net (fanout=56)       1.806   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst
    SLICE_X12Y96.CLK     Trck                  0.233   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER<15>
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13
    -------------------------------------------------  ---------------------------
    Total                                      3.738ns (0.918ns logic, 2.820ns route)
                                                       (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     6.934ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13 (FF)
  Requirement:          12.800ns
  Data Path Delay:      5.651ns (Levels of Logic = 1)
  Clock Path Skew:      -0.072ns (0.599 - 0.671)
  Source Clock:         SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.143ns

  Clock Uncertainty:          0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.276ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y64.AQ      Tcko                  0.476   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X6Y87.C2       net (fanout=3)        2.881   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X6Y87.C        Tilo                  0.255   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1
    SLICE_X12Y96.SR      net (fanout=56)       1.806   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst
    SLICE_X12Y96.CLK     Trck                  0.233   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER<15>
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13
    -------------------------------------------------  ---------------------------
    Total                                      5.651ns (0.964ns logic, 4.687ns route)
                                                       (17.1% logic, 82.9% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_12 (SLICE_X12Y96.SR), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.983ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1 (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_12 (FF)
  Requirement:          6.400ns
  Data Path Delay:      3.727ns (Levels of Logic = 1)
  Clock Path Skew:      -0.427ns (2.006 - 2.433)
  Source Clock:         SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.263ns

  Clock Uncertainty:          0.263ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.276ns
    Phase Error (PE):           0.120ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1 to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y80.AQ       Tcko                  0.430   SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_3
                                                       SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1
    SLICE_X6Y87.C3       net (fanout=1)        1.014   SDRAM_FIFO_inst/memc3_infrastructure_inst/powerup_pll_locked_1
    SLICE_X6Y87.C        Tilo                  0.255   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1
    SLICE_X12Y96.SR      net (fanout=56)       1.806   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst
    SLICE_X12Y96.CLK     Trck                  0.222   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER<15>
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_12
    -------------------------------------------------  ---------------------------
    Total                                      3.727ns (0.907ns logic, 2.820ns route)
                                                       (24.3% logic, 75.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     6.945ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_12 (FF)
  Requirement:          12.800ns
  Data Path Delay:      5.640ns (Levels of Logic = 1)
  Clock Path Skew:      -0.072ns (0.599 - 0.671)
  Source Clock:         SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.143ns

  Clock Uncertainty:          0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.276ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y64.AQ      Tcko                  0.476   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X6Y87.C2       net (fanout=3)        2.881   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X6Y87.C        Tilo                  0.255   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1
    SLICE_X12Y96.SR      net (fanout=56)       1.806   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst
    SLICE_X12Y96.CLK     Trck                  0.222   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER<15>
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_12
    -------------------------------------------------  ---------------------------
    Total                                      5.640ns (0.953ns logic, 4.687ns route)
                                                       (16.9% logic, 83.1% route)

--------------------------------------------------------------------------------

Hold Paths: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD
        TIMEGRP
        "SDRAM_FIFO_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in"
        TS_SYS_CLK3 / 0.78125 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_3 (SLICE_X7Y89.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.389ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.394ns (Levels of Logic = 0)
  Clock Path Skew:      0.005ns (0.034 - 0.029)
  Source Clock:         SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y88.AQ       Tcko                  0.234   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
    SLICE_X7Y89.SR       net (fanout=61)       0.291   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
    SLICE_X7Y89.CLK      Tcksr       (-Th)     0.131   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg<5>
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_3
    -------------------------------------------------  ---------------------------
    Total                                      0.394ns (0.103ns logic, 0.291ns route)
                                                       (26.1% logic, 73.9% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_5 (SLICE_X7Y89.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.393ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.398ns (Levels of Logic = 0)
  Clock Path Skew:      0.005ns (0.034 - 0.029)
  Source Clock:         SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y88.AQ       Tcko                  0.234   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
    SLICE_X7Y89.SR       net (fanout=61)       0.291   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
    SLICE_X7Y89.CLK      Tcksr       (-Th)     0.127   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg<5>
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_5
    -------------------------------------------------  ---------------------------
    Total                                      0.398ns (0.107ns logic, 0.291ns route)
                                                       (26.9% logic, 73.1% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_4 (SLICE_X7Y89.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.399ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg (FF)
  Destination:          SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.404ns (Levels of Logic = 0)
  Clock Path Skew:      0.005ns (0.034 - 0.029)
  Source Clock:         SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Destination Clock:    SDRAM_FIFO_inst/c3_mcb_drp_clk rising at 12.800ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg to SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y88.AQ       Tcko                  0.234   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
    SLICE_X7Y89.SR       net (fanout=61)       0.291   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
    SLICE_X7Y89.CLK      Tcksr       (-Th)     0.121   SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg<5>
                                                       SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/shift_through_reg_4
    -------------------------------------------------  ---------------------------
    Total                                      0.404ns (0.113ns logic, 0.291ns route)
                                                       (28.0% logic, 72.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD
        TIMEGRP
        "SDRAM_FIFO_inst_memc3_infrastructure_inst_mcb_drp_clk_bufg_in"
        TS_SYS_CLK3 / 0.78125 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 10.134ns (period - min period limit)
  Period: 12.800ns
  Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
  Physical resource: SDRAM_FIFO_inst/memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Logical resource: SDRAM_FIFO_inst/memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Location pin: BUFGMUX_X2Y2.I0
  Clock network: SDRAM_FIFO_inst/memc3_infrastructure_inst/mcb_drp_clk_bufg_in
--------------------------------------------------------------------------------
Slack: 11.401ns (period - min period limit)
  Period: 12.800ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_MODE_R3/CLK
  Logical resource: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2/CLK
  Location pin: SLICE_X2Y87.CLK
  Clock network: SDRAM_FIFO_inst/c3_mcb_drp_clk
--------------------------------------------------------------------------------
Slack: 11.800ns (period - min period limit)
  Period: 12.800ns
  Min period limit: 1.000ns (1000.000MHz) (Tmcbcper_UICLK)
  Physical resource: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Logical resource: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Location pin: MCB_X0Y1.UICLK
  Clock network: SDRAM_FIFO_inst/c3_mcb_drp_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_180 = 
PERIOD TIMEGRP         "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_180" 
TS_SYS_CLK3 /         6.25 PHASE 0.8 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.599ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP
        "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_180" TS_SYS_CLK3 /
        6.25 PHASE 0.8 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.600ns
  Min period limit: 1.599ns (625.391MHz) (Tmcbcper_PLLCLK)
  Physical resource: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Logical resource: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Location pin: MCB_X0Y1.PLLCLK1
  Clock network: SDRAM_FIFO_inst/c3_sysclk_2x_180
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_0 = 
PERIOD TIMEGRP         "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_0" 
TS_SYS_CLK3 /         6.25 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.599ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP
        "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk_2x_0" TS_SYS_CLK3 /
        6.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.600ns
  Min period limit: 1.599ns (625.391MHz) (Tmcbcper_PLLCLK)
  Physical resource: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Logical resource: SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Location pin: MCB_X0Y1.PLLCLK0
  Clock network: SDRAM_FIFO_inst/c3_sysclk_2x
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk0_bufg_in = 
PERIOD TIMEGRP         "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk0_bufg_in" 
TS_SYS_CLK3 /         1.5625 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 4315 paths analyzed, 2048 endpoints analyzed, 9 failing endpoints
 9 timing errors detected. (9 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is 3509.440ns.
--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_8 (SLICE_X15Y69.CX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     -10.947ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_8 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_8 (FF)
  Requirement:          0.020ns
  Data Path Delay:      1.435ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
  Clock Path Skew:      -9.133ns (4.521 - 13.654)
  Source Clock:         dataclk rising at 1702.380ns
  Destination Clock:    SDRAM_FIFO_inst/c3_clk0 rising at 1702.400ns
  Clock Uncertainty:    0.399ns

  Clock Uncertainty:          0.399ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.244ns
    Phase Error (PE):           0.271ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_8 to SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y69.DMUX    Tshcko                0.576   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<9>
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_8
    SLICE_X15Y69.CX      net (fanout=1)        0.745   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<8>
    SLICE_X15Y69.CLK     Tdick                 0.114   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<9>
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_8
    -------------------------------------------------  ---------------------------
    Total                                      1.435ns (0.690ns logic, 0.745ns route)
                                                       (48.1% logic, 51.9% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 (SLICE_X15Y70.AX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     -10.880ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 (FF)
  Requirement:          0.020ns
  Data Path Delay:      1.365ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
  Clock Path Skew:      -9.136ns (4.518 - 13.654)
  Source Clock:         dataclk rising at 1702.380ns
  Destination Clock:    SDRAM_FIFO_inst/c3_clk0 rising at 1702.400ns
  Clock Uncertainty:    0.399ns

  Clock Uncertainty:          0.399ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.244ns
    Phase Error (PE):           0.271ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 to SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y69.AMUX    Tshcko                0.576   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<9>
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2
    SLICE_X15Y70.AX      net (fanout=1)        0.675   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<2>
    SLICE_X15Y70.CLK     Tdick                 0.114   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<5>
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2
    -------------------------------------------------  ---------------------------
    Total                                      1.365ns (0.690ns logic, 0.675ns route)
                                                       (50.5% logic, 49.5% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9 (SLICE_X15Y69.DX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     -10.856ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_9 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9 (FF)
  Requirement:          0.020ns
  Data Path Delay:      1.344ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
  Clock Path Skew:      -9.133ns (4.521 - 13.654)
  Source Clock:         dataclk rising at 1702.380ns
  Destination Clock:    SDRAM_FIFO_inst/c3_clk0 rising at 1702.400ns
  Clock Uncertainty:    0.399ns

  Clock Uncertainty:          0.399ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.244ns
    Phase Error (PE):           0.271ns

  Maximum Data Path at Slow Process Corner: SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_9 to SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y69.DQ      Tcko                  0.525   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<9>
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_9
    SLICE_X15Y69.DX      net (fanout=1)        0.705   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc<9>
    SLICE_X15Y69.CLK     Tdick                 0.114   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<9>
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9
    -------------------------------------------------  ---------------------------
    Total                                      1.344ns (0.639ns logic, 0.705ns route)
                                                       (47.5% logic, 52.5% route)

--------------------------------------------------------------------------------

Hold Paths: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP
        "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk0_bufg_in" TS_SYS_CLK3 /
        1.5625 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X0Y28.DIA9), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.271ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_42 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.277ns (Levels of Logic = 0)
  Clock Path Skew:      0.006ns (0.068 - 0.062)
  Source Clock:         SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Destination Clock:    SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_42 to SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y56.DQ       Tcko                  0.198   SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_42
                                                       SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_42
    RAMB16_X0Y28.DIA9    net (fanout=2)        0.132   SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_42
    RAMB16_X0Y28.CLKA    Trckd_DIA   (-Th)     0.053   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.277ns (0.145ns logic, 0.132ns route)
                                                       (52.3% logic, 47.7% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X0Y26.DIA23), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.295ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_23 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.303ns (Levels of Logic = 0)
  Clock Path Skew:      0.008ns (0.070 - 0.062)
  Source Clock:         SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Destination Clock:    SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_23 to SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y55.BQ       Tcko                  0.198   SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_25
                                                       SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_23
    RAMB16_X0Y26.DIA23   net (fanout=2)        0.158   SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_23
    RAMB16_X0Y26.CLKA    Trckd_DIA   (-Th)     0.053   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.303ns (0.145ns logic, 0.158ns route)
                                                       (47.9% logic, 52.1% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X0Y28.DIA27), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.311ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_12 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.312ns (Levels of Logic = 0)
  Clock Path Skew:      0.001ns (0.068 - 0.067)
  Source Clock:         SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Destination Clock:    SDRAM_FIFO_inst/c3_clk0 rising at 6.400ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_12 to SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y58.BQ       Tcko                  0.234   SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_14
                                                       SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_12
    RAMB16_X0Y28.DIA27   net (fanout=2)        0.131   SDRAM_FIFO_inst/ddr2_state_machine_inst/ob_data_12
    RAMB16_X0Y28.CLKA    Trckd_DIA   (-Th)     0.053   SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.312ns (0.181ns logic, 0.131ns route)
                                                       (58.0% logic, 42.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_SDRAM_FIFO_inst_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP
        "SDRAM_FIFO_inst_memc3_infrastructure_inst_clk0_bufg_in" TS_SYS_CLK3 /
        1.5625 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.830ns (period - min period limit)
  Period: 6.400ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X0Y28.CLKA
  Clock network: SDRAM_FIFO_inst/c3_clk0
--------------------------------------------------------------------------------
Slack: 2.830ns (period - min period limit)
  Period: 6.400ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: SDRAM_FIFO_inst/okPipeOut_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X0Y26.CLKA
  Clock network: SDRAM_FIFO_inst/c3_clk0
--------------------------------------------------------------------------------
Slack: 2.830ns (period - min period limit)
  Period: 6.400ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  Logical resource: SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  Location pin: RAMB16_X1Y30.CLKB
  Clock network: SDRAM_FIFO_inst/c3_clk0
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_variable_freq_clk_generator_inst_clkout_i = PERIOD 
TIMEGRP         "variable_freq_clk_generator_inst_clkout_i" TS_SYS_CLK3 / 0.84 
HIGH         50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 10905534 paths analyzed, 7518 endpoints analyzed, 117 failing endpoints
 117 timing errors detected. (117 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  16.321ns.
--------------------------------------------------------------------------------

Paths for end point DAC_output_8/DAC_DIN (SLICE_X32Y87.A5), 1104332 paths
--------------------------------------------------------------------------------
Slack (setup path):     -4.417ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_8_0 (FF)
  Destination:          DAC_output_8/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      16.231ns (Levels of Logic = 18)
  Clock Path Skew:      -0.055ns (0.580 - 0.635)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_8_0 to DAC_output_8/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X27Y88.DQ      Tcko                  0.430   DAC_register_8<0>
                                                       DAC_register_8_0
    SLICE_X26Y87.CX      net (fanout=3)        0.739   DAC_register_8<0>
    SLICE_X26Y87.COUT    Tcxcy                 0.117   DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X26Y88.CIN     net (fanout=1)        0.082   DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X26Y88.COUT    Tbyp                  0.093   DAC_register_8<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.BMUX    Tcinb                 0.310   DAC_register_8<7>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X25Y89.B5      net (fanout=4)        0.938   DAC_output_8/n0206<9>
    SLICE_X25Y89.B       Tilo                  0.259   DAC_register_8<12>
                                                       DAC_output_8/Mmux_HPF_output141
    SLICE_X28Y89.DX      net (fanout=3)        1.628   DAC_output_8/HPF_output<7>
    SLICE_X28Y89.COUT    Tdxcy                 0.121   DAC_output_8/Msub_subtract_result_cy<7>
                                                       DAC_output_8/Msub_subtract_result_cy<7>
    SLICE_X28Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Msub_subtract_result_cy<7>
    SLICE_X28Y90.COUT    Tbyp                  0.091   DAC_output_8/Msub_subtract_result_cy<11>
                                                       DAC_output_8/Msub_subtract_result_cy<11>
    SLICE_X28Y91.CIN     net (fanout=1)        0.003   DAC_output_8/Msub_subtract_result_cy<11>
    SLICE_X28Y91.BMUX    Tcinb                 0.277   DAC_output_8/subtract_result<15>
                                                       DAC_output_8/Msub_subtract_result_xor<15>
    SLICE_X30Y90.D5      net (fanout=2)        0.956   DAC_output_8/subtract_result<13>
    SLICE_X30Y90.D       Tilo                  0.254   DAC_output_8/DAC_input_suppressed<13>
                                                       DAC_output_8/Mmux_DAC_input_suppressed51
    SLICE_X31Y90.D5      net (fanout=14)       0.472   DAC_output_8/DAC_input_suppressed<13>
    SLICE_X31Y90.D       Tilo                  0.259   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X31Y90.C6      net (fanout=24)       0.199   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X31Y90.C       Tilo                  0.259   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X32Y89.A2      net (fanout=24)       0.949   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X32Y89.A       Tilo                  0.235   DAC_output_8/Mmux_DAC_input_scaled<0>_3
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X30Y91.B4      net (fanout=9)        0.897   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X30Y91.B       Tilo                  0.254   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
                                                       DAC_output_8/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o161
    SLICE_X30Y91.C6      net (fanout=1)        0.269   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
    SLICE_X30Y91.CMUX    Tilo                  0.430   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
                                                       DAC_output_8/Mmux_DAC_input_scaled<13>_3
                                                       DAC_output_8/Mmux_DAC_input_scaled<13>_2_f7
    SLICE_X17Y86.B1      net (fanout=1)        2.024   DAC_output_8/DAC_input_scaled<13>
    SLICE_X17Y86.B       Tilo                  0.259   DAC_output_7/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_8/SF1312
    SLICE_X17Y86.C4      net (fanout=1)        0.320   DAC_output_8/SF1312
    SLICE_X17Y86.C       Tilo                  0.259   DAC_output_7/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_8/SF1313
    SLICE_X32Y87.D5      net (fanout=2)        1.284   DAC_output_8/SF131
    SLICE_X32Y87.D       Tilo                  0.235   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X32Y87.B1      net (fanout=1)        0.543   DAC_output_8/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X32Y87.B       Tilo                  0.235   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X32Y87.A5      net (fanout=1)        0.196   DAC_output_8/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X32Y87.CLK     Tas                   0.349   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_8/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     16.231ns (4.726ns logic, 11.505ns route)
                                                       (29.1% logic, 70.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     -4.390ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_8_3 (FF)
  Destination:          DAC_output_8/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      16.204ns (Levels of Logic = 17)
  Clock Path Skew:      -0.055ns (0.580 - 0.635)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_8_3 to DAC_output_8/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y88.DQ      Tcko                  0.525   DAC_register_8<3>
                                                       DAC_register_8_3
    SLICE_X26Y88.B5      net (fanout=3)        0.426   DAC_register_8<3>
    SLICE_X26Y88.COUT    Topcyb                0.483   DAC_register_8<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_lut<5>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.BMUX    Tcinb                 0.310   DAC_register_8<7>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X25Y89.B5      net (fanout=4)        0.938   DAC_output_8/n0206<9>
    SLICE_X25Y89.B       Tilo                  0.259   DAC_register_8<12>
                                                       DAC_output_8/Mmux_HPF_output141
    SLICE_X28Y89.DX      net (fanout=3)        1.628   DAC_output_8/HPF_output<7>
    SLICE_X28Y89.COUT    Tdxcy                 0.121   DAC_output_8/Msub_subtract_result_cy<7>
                                                       DAC_output_8/Msub_subtract_result_cy<7>
    SLICE_X28Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Msub_subtract_result_cy<7>
    SLICE_X28Y90.COUT    Tbyp                  0.091   DAC_output_8/Msub_subtract_result_cy<11>
                                                       DAC_output_8/Msub_subtract_result_cy<11>
    SLICE_X28Y91.CIN     net (fanout=1)        0.003   DAC_output_8/Msub_subtract_result_cy<11>
    SLICE_X28Y91.BMUX    Tcinb                 0.277   DAC_output_8/subtract_result<15>
                                                       DAC_output_8/Msub_subtract_result_xor<15>
    SLICE_X30Y90.D5      net (fanout=2)        0.956   DAC_output_8/subtract_result<13>
    SLICE_X30Y90.D       Tilo                  0.254   DAC_output_8/DAC_input_suppressed<13>
                                                       DAC_output_8/Mmux_DAC_input_suppressed51
    SLICE_X31Y90.D5      net (fanout=14)       0.472   DAC_output_8/DAC_input_suppressed<13>
    SLICE_X31Y90.D       Tilo                  0.259   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X31Y90.C6      net (fanout=24)       0.199   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X31Y90.C       Tilo                  0.259   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X32Y89.A2      net (fanout=24)       0.949   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X32Y89.A       Tilo                  0.235   DAC_output_8/Mmux_DAC_input_scaled<0>_3
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X30Y91.B4      net (fanout=9)        0.897   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X30Y91.B       Tilo                  0.254   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
                                                       DAC_output_8/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o161
    SLICE_X30Y91.C6      net (fanout=1)        0.269   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
    SLICE_X30Y91.CMUX    Tilo                  0.430   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
                                                       DAC_output_8/Mmux_DAC_input_scaled<13>_3
                                                       DAC_output_8/Mmux_DAC_input_scaled<13>_2_f7
    SLICE_X17Y86.B1      net (fanout=1)        2.024   DAC_output_8/DAC_input_scaled<13>
    SLICE_X17Y86.B       Tilo                  0.259   DAC_output_7/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_8/SF1312
    SLICE_X17Y86.C4      net (fanout=1)        0.320   DAC_output_8/SF1312
    SLICE_X17Y86.C       Tilo                  0.259   DAC_output_7/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_8/SF1313
    SLICE_X32Y87.D5      net (fanout=2)        1.284   DAC_output_8/SF131
    SLICE_X32Y87.D       Tilo                  0.235   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X32Y87.B1      net (fanout=1)        0.543   DAC_output_8/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X32Y87.B       Tilo                  0.235   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X32Y87.A5      net (fanout=1)        0.196   DAC_output_8/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X32Y87.CLK     Tas                   0.349   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_8/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     16.204ns (5.094ns logic, 11.110ns route)
                                                       (31.4% logic, 68.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     -4.368ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_8_0 (FF)
  Destination:          DAC_output_8/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      16.182ns (Levels of Logic = 20)
  Clock Path Skew:      -0.055ns (0.580 - 0.635)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_8_0 to DAC_output_8/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X27Y88.DQ      Tcko                  0.430   DAC_register_8<0>
                                                       DAC_register_8_0
    SLICE_X26Y87.CX      net (fanout=3)        0.739   DAC_register_8<0>
    SLICE_X26Y87.COUT    Tcxcy                 0.117   DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X26Y88.CIN     net (fanout=1)        0.082   DAC_output_8/Madd_n0206_Madd_Madd_cy<3>
    SLICE_X26Y88.COUT    Tbyp                  0.093   DAC_register_8<3>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y89.COUT    Tbyp                  0.093   DAC_register_8<7>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y90.COUT    Tbyp                  0.093   DAC_thresh_8<12>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y91.CIN     net (fanout=1)        0.003   DAC_output_8/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y91.BMUX    Tcinb                 0.310   DAC_output_8/n0206<17>
                                                       DAC_output_8/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X25Y89.B6      net (fanout=50)       0.697   DAC_output_8/n0206<17>
    SLICE_X25Y89.B       Tilo                  0.259   DAC_register_8<12>
                                                       DAC_output_8/Mmux_HPF_output141
    SLICE_X28Y89.DX      net (fanout=3)        1.628   DAC_output_8/HPF_output<7>
    SLICE_X28Y89.COUT    Tdxcy                 0.121   DAC_output_8/Msub_subtract_result_cy<7>
                                                       DAC_output_8/Msub_subtract_result_cy<7>
    SLICE_X28Y90.CIN     net (fanout=1)        0.003   DAC_output_8/Msub_subtract_result_cy<7>
    SLICE_X28Y90.COUT    Tbyp                  0.091   DAC_output_8/Msub_subtract_result_cy<11>
                                                       DAC_output_8/Msub_subtract_result_cy<11>
    SLICE_X28Y91.CIN     net (fanout=1)        0.003   DAC_output_8/Msub_subtract_result_cy<11>
    SLICE_X28Y91.BMUX    Tcinb                 0.277   DAC_output_8/subtract_result<15>
                                                       DAC_output_8/Msub_subtract_result_xor<15>
    SLICE_X30Y90.D5      net (fanout=2)        0.956   DAC_output_8/subtract_result<13>
    SLICE_X30Y90.D       Tilo                  0.254   DAC_output_8/DAC_input_suppressed<13>
                                                       DAC_output_8/Mmux_DAC_input_suppressed51
    SLICE_X31Y90.D5      net (fanout=14)       0.472   DAC_output_8/DAC_input_suppressed<13>
    SLICE_X31Y90.D       Tilo                  0.259   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X31Y90.C6      net (fanout=24)       0.199   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X31Y90.C       Tilo                  0.259   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X32Y89.A2      net (fanout=24)       0.949   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X32Y89.A       Tilo                  0.235   DAC_output_8/Mmux_DAC_input_scaled<0>_3
                                                       DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X30Y91.B4      net (fanout=9)        0.897   DAC_output_8/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X30Y91.B       Tilo                  0.254   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
                                                       DAC_output_8/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o161
    SLICE_X30Y91.C6      net (fanout=1)        0.269   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
    SLICE_X30Y91.CMUX    Tilo                  0.430   DAC_output_8/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
                                                       DAC_output_8/Mmux_DAC_input_scaled<13>_3
                                                       DAC_output_8/Mmux_DAC_input_scaled<13>_2_f7
    SLICE_X17Y86.B1      net (fanout=1)        2.024   DAC_output_8/DAC_input_scaled<13>
    SLICE_X17Y86.B       Tilo                  0.259   DAC_output_7/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_8/SF1312
    SLICE_X17Y86.C4      net (fanout=1)        0.320   DAC_output_8/SF1312
    SLICE_X17Y86.C       Tilo                  0.259   DAC_output_7/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_8/SF1313
    SLICE_X32Y87.D5      net (fanout=2)        1.284   DAC_output_8/SF131
    SLICE_X32Y87.D       Tilo                  0.235   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X32Y87.B1      net (fanout=1)        0.543   DAC_output_8/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X32Y87.B       Tilo                  0.235   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X32Y87.A5      net (fanout=1)        0.196   DAC_output_8/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X32Y87.CLK     Tas                   0.349   DAC_output_8/DAC_DIN
                                                       DAC_output_8/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_8/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     16.182ns (4.912ns logic, 11.270ns route)
                                                       (30.4% logic, 69.6% route)

--------------------------------------------------------------------------------

Paths for end point DAC_output_6/DAC_DIN (SLICE_X35Y102.A5), 1089819 paths
--------------------------------------------------------------------------------
Slack (setup path):     -4.180ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_6_2 (FF)
  Destination:          DAC_output_6/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      16.006ns (Levels of Logic = 19)
  Clock Path Skew:      -0.043ns (0.585 - 0.628)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_6_2 to DAC_output_6/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y100.DQ     Tcko                  0.525   DAC_register_6<2>
                                                       DAC_register_6_2
    SLICE_X26Y100.A6     net (fanout=3)        0.816   DAC_register_6<2>
    SLICE_X26Y100.COUT   Topcya                0.474   DAC_register_6<2>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_lut<4>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y101.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y101.COUT   Tbyp                  0.093   DAC_register_6<4>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y102.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y102.COUT   Tbyp                  0.093   DAC_register_6<6>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y103.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y103.BMUX   Tcinb                 0.310   DAC_output_6/n0206<17>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X29Y100.D6     net (fanout=50)       0.720   DAC_output_6/n0206<17>
    SLICE_X29Y100.D      Tilo                  0.259   DAC_thresh_6<15>
                                                       DAC_output_6/Mmux_HPF_output141
    SLICE_X24Y102.DX     net (fanout=3)        1.513   DAC_output_6/HPF_output<7>
    SLICE_X24Y102.COUT   Tdxcy                 0.121   DAC_output_6/Msub_subtract_result_cy<7>
                                                       DAC_output_6/Msub_subtract_result_cy<7>
    SLICE_X24Y103.CIN    net (fanout=1)        0.003   DAC_output_6/Msub_subtract_result_cy<7>
    SLICE_X24Y103.COUT   Tbyp                  0.091   DAC_output_6/Msub_subtract_result_cy<11>
                                                       DAC_output_6/Msub_subtract_result_cy<11>
    SLICE_X24Y104.CIN    net (fanout=1)        0.082   DAC_output_6/Msub_subtract_result_cy<11>
    SLICE_X24Y104.DMUX   Tcind                 0.289   DAC_output_6/subtract_result<15>
                                                       DAC_output_6/Msub_subtract_result_xor<15>
    SLICE_X29Y106.B3     net (fanout=30)       1.111   DAC_output_6/subtract_result<15>
    SLICE_X29Y106.B      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/Mmux_DAC_input_suppressed61
    SLICE_X29Y106.D2     net (fanout=17)       0.580   DAC_output_6/DAC_input_suppressed<14>
    SLICE_X29Y106.D      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X29Y106.C6     net (fanout=22)       0.185   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X29Y106.C      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X30Y105.A6     net (fanout=24)       0.864   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X30Y105.A      Tilo                  0.254   DAC_output_6/Mmux_DAC_input_scaled<0>_3
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X32Y106.B1     net (fanout=9)        1.414   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X32Y106.B      Tilo                  0.235   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
                                                       DAC_output_6/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o171
    SLICE_X32Y106.C5     net (fanout=1)        0.431   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
    SLICE_X32Y106.CMUX   Tilo                  0.403   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
                                                       DAC_output_6/Mmux_DAC_input_scaled<14>_3
                                                       DAC_output_6/Mmux_DAC_input_scaled<14>_2_f7
    SLICE_X39Y105.B5     net (fanout=1)        0.979   DAC_output_6/DAC_input_scaled<14>
    SLICE_X39Y105.B      Tilo                  0.259   DAC_output_5/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_6/SF1312
    SLICE_X39Y105.C4     net (fanout=1)        0.320   DAC_output_6/SF1312
    SLICE_X39Y105.C      Tilo                  0.259   DAC_output_5/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_6/SF1313
    SLICE_X35Y102.D6     net (fanout=2)        0.873   DAC_output_6/SF131
    SLICE_X35Y102.D      Tilo                  0.259   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X35Y102.B2     net (fanout=1)        0.543   DAC_output_6/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X35Y102.B      Tilo                  0.259   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X35Y102.A5     net (fanout=1)        0.230   DAC_output_6/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X35Y102.CLK    Tas                   0.373   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_6/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     16.006ns (5.333ns logic, 10.673ns route)
                                                       (33.3% logic, 66.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     -4.113ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_6_2 (FF)
  Destination:          DAC_output_6/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      15.939ns (Levels of Logic = 19)
  Clock Path Skew:      -0.043ns (0.585 - 0.628)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_6_2 to DAC_output_6/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y100.DQ     Tcko                  0.525   DAC_register_6<2>
                                                       DAC_register_6_2
    SLICE_X26Y100.AX     net (fanout=3)        0.975   DAC_register_6<2>
    SLICE_X26Y100.COUT   Taxcy                 0.248   DAC_register_6<2>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y101.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y101.COUT   Tbyp                  0.093   DAC_register_6<4>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y102.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y102.COUT   Tbyp                  0.093   DAC_register_6<6>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y103.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y103.BMUX   Tcinb                 0.310   DAC_output_6/n0206<17>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X29Y100.D6     net (fanout=50)       0.720   DAC_output_6/n0206<17>
    SLICE_X29Y100.D      Tilo                  0.259   DAC_thresh_6<15>
                                                       DAC_output_6/Mmux_HPF_output141
    SLICE_X24Y102.DX     net (fanout=3)        1.513   DAC_output_6/HPF_output<7>
    SLICE_X24Y102.COUT   Tdxcy                 0.121   DAC_output_6/Msub_subtract_result_cy<7>
                                                       DAC_output_6/Msub_subtract_result_cy<7>
    SLICE_X24Y103.CIN    net (fanout=1)        0.003   DAC_output_6/Msub_subtract_result_cy<7>
    SLICE_X24Y103.COUT   Tbyp                  0.091   DAC_output_6/Msub_subtract_result_cy<11>
                                                       DAC_output_6/Msub_subtract_result_cy<11>
    SLICE_X24Y104.CIN    net (fanout=1)        0.082   DAC_output_6/Msub_subtract_result_cy<11>
    SLICE_X24Y104.DMUX   Tcind                 0.289   DAC_output_6/subtract_result<15>
                                                       DAC_output_6/Msub_subtract_result_xor<15>
    SLICE_X29Y106.B3     net (fanout=30)       1.111   DAC_output_6/subtract_result<15>
    SLICE_X29Y106.B      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/Mmux_DAC_input_suppressed61
    SLICE_X29Y106.D2     net (fanout=17)       0.580   DAC_output_6/DAC_input_suppressed<14>
    SLICE_X29Y106.D      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X29Y106.C6     net (fanout=22)       0.185   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X29Y106.C      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X30Y105.A6     net (fanout=24)       0.864   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X30Y105.A      Tilo                  0.254   DAC_output_6/Mmux_DAC_input_scaled<0>_3
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X32Y106.B1     net (fanout=9)        1.414   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X32Y106.B      Tilo                  0.235   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
                                                       DAC_output_6/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o171
    SLICE_X32Y106.C5     net (fanout=1)        0.431   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
    SLICE_X32Y106.CMUX   Tilo                  0.403   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
                                                       DAC_output_6/Mmux_DAC_input_scaled<14>_3
                                                       DAC_output_6/Mmux_DAC_input_scaled<14>_2_f7
    SLICE_X39Y105.B5     net (fanout=1)        0.979   DAC_output_6/DAC_input_scaled<14>
    SLICE_X39Y105.B      Tilo                  0.259   DAC_output_5/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_6/SF1312
    SLICE_X39Y105.C4     net (fanout=1)        0.320   DAC_output_6/SF1312
    SLICE_X39Y105.C      Tilo                  0.259   DAC_output_5/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_6/SF1313
    SLICE_X35Y102.D6     net (fanout=2)        0.873   DAC_output_6/SF131
    SLICE_X35Y102.D      Tilo                  0.259   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X35Y102.B2     net (fanout=1)        0.543   DAC_output_6/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X35Y102.B      Tilo                  0.259   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X35Y102.A5     net (fanout=1)        0.230   DAC_output_6/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X35Y102.CLK    Tas                   0.373   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_6/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     15.939ns (5.107ns logic, 10.832ns route)
                                                       (32.0% logic, 68.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     -3.961ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_6_2 (FF)
  Destination:          DAC_output_6/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      15.787ns (Levels of Logic = 19)
  Clock Path Skew:      -0.043ns (0.585 - 0.628)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_6_2 to DAC_output_6/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y100.DQ     Tcko                  0.525   DAC_register_6<2>
                                                       DAC_register_6_2
    SLICE_X26Y100.A6     net (fanout=3)        0.816   DAC_register_6<2>
    SLICE_X26Y100.COUT   Topcya                0.474   DAC_register_6<2>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_lut<4>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y101.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X26Y101.COUT   Tbyp                  0.093   DAC_register_6<4>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y102.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X26Y102.COUT   Tbyp                  0.093   DAC_register_6<6>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y103.CIN    net (fanout=1)        0.003   DAC_output_6/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X26Y103.BMUX   Tcinb                 0.310   DAC_output_6/n0206<17>
                                                       DAC_output_6/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X29Y100.D6     net (fanout=50)       0.720   DAC_output_6/n0206<17>
    SLICE_X29Y100.D      Tilo                  0.259   DAC_thresh_6<15>
                                                       DAC_output_6/Mmux_HPF_output141
    SLICE_X24Y102.DX     net (fanout=3)        1.513   DAC_output_6/HPF_output<7>
    SLICE_X24Y102.COUT   Tdxcy                 0.121   DAC_output_6/Msub_subtract_result_cy<7>
                                                       DAC_output_6/Msub_subtract_result_cy<7>
    SLICE_X24Y103.CIN    net (fanout=1)        0.003   DAC_output_6/Msub_subtract_result_cy<7>
    SLICE_X24Y103.COUT   Tbyp                  0.091   DAC_output_6/Msub_subtract_result_cy<11>
                                                       DAC_output_6/Msub_subtract_result_cy<11>
    SLICE_X24Y104.CIN    net (fanout=1)        0.082   DAC_output_6/Msub_subtract_result_cy<11>
    SLICE_X24Y104.CMUX   Tcinc                 0.289   DAC_output_6/subtract_result<15>
                                                       DAC_output_6/Msub_subtract_result_xor<15>
    SLICE_X29Y106.B5     net (fanout=2)        0.892   DAC_output_6/subtract_result<14>
    SLICE_X29Y106.B      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/Mmux_DAC_input_suppressed61
    SLICE_X29Y106.D2     net (fanout=17)       0.580   DAC_output_6/DAC_input_suppressed<14>
    SLICE_X29Y106.D      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X29Y106.C6     net (fanout=22)       0.185   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X29Y106.C      Tilo                  0.259   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X30Y105.A6     net (fanout=24)       0.864   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X30Y105.A      Tilo                  0.254   DAC_output_6/Mmux_DAC_input_scaled<0>_3
                                                       DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X32Y106.B1     net (fanout=9)        1.414   DAC_output_6/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X32Y106.B      Tilo                  0.235   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
                                                       DAC_output_6/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o171
    SLICE_X32Y106.C5     net (fanout=1)        0.431   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
    SLICE_X32Y106.CMUX   Tilo                  0.403   DAC_output_6/DAC_input_suppressed[15]_DAC_input_suppressed[7]_MUX_752_o
                                                       DAC_output_6/Mmux_DAC_input_scaled<14>_3
                                                       DAC_output_6/Mmux_DAC_input_scaled<14>_2_f7
    SLICE_X39Y105.B5     net (fanout=1)        0.979   DAC_output_6/DAC_input_scaled<14>
    SLICE_X39Y105.B      Tilo                  0.259   DAC_output_5/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_6/SF1312
    SLICE_X39Y105.C4     net (fanout=1)        0.320   DAC_output_6/SF1312
    SLICE_X39Y105.C      Tilo                  0.259   DAC_output_5/main_state[31]_GND_66_o_Select_51_o12
                                                       DAC_output_6/SF1313
    SLICE_X35Y102.D6     net (fanout=2)        0.873   DAC_output_6/SF131
    SLICE_X35Y102.D      Tilo                  0.259   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X35Y102.B2     net (fanout=1)        0.543   DAC_output_6/main_state[31]_GND_66_o_Select_51_o11
    SLICE_X35Y102.B      Tilo                  0.259   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X35Y102.A5     net (fanout=1)        0.230   DAC_output_6/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X35Y102.CLK    Tas                   0.373   DAC_output_6/DAC_DIN
                                                       DAC_output_6/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_6/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     15.787ns (5.333ns logic, 10.454ns route)
                                                       (33.8% logic, 66.2% route)

--------------------------------------------------------------------------------

Paths for end point DAC_output_2/DAC_DIN (SLICE_X23Y74.A5), 1767147 paths
--------------------------------------------------------------------------------
Slack (setup path):     -3.672ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_2_6 (FF)
  Destination:          DAC_output_2/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      15.528ns (Levels of Logic = 18)
  Clock Path Skew:      -0.013ns (0.632 - 0.645)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_2_6 to DAC_output_2/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y74.DQ      Tcko                  0.476   DAC_register_2<6>
                                                       DAC_register_2_6
    SLICE_X32Y72.A6      net (fanout=6)        0.803   DAC_register_2<6>
    SLICE_X32Y72.COUT    Topcya                0.472   DAC_register_2<3>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_lut<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.COUT    Tbyp                  0.091   TTL_out_user<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.BMUX    Tcinb                 0.277   DAC_register_2<6>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X33Y74.A5      net (fanout=36)       1.212   DAC_output_2/n0206<17>
    SLICE_X33Y74.A       Tilo                  0.259   WS2812controller/GRB_reg<9>
                                                       DAC_output_2/Mmux_multiplier_in181
    SLICE_X34Y72.D5      net (fanout=3)        1.399   DAC_output_2/multiplier_in<9>
    SLICE_X34Y72.COUT    Topcyd                0.312   DAC_register_2<9>
                                                       DAC_output_2/Madd_add_result_lut<7>
                                                       DAC_output_2/Madd_add_result_cy<7>
    SLICE_X34Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_add_result_cy<7>
    SLICE_X34Y73.COUT    Tbyp                  0.093   DAC_output_2/Madd_add_result_cy<11>
                                                       DAC_output_2/Madd_add_result_cy<11>
    SLICE_X34Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_add_result_cy<11>
    SLICE_X34Y74.DMUX    Tcind                 0.320   DAC_register_2<14>
                                                       DAC_output_2/Madd_add_result_xor<15>
    SLICE_X33Y71.B3      net (fanout=91)       1.083   DAC_output_2/add_result<15>
    SLICE_X33Y71.B       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[12]_MUX_663_o
                                                       DAC_output_2/Mmux_DAC_input_suppressed41
    SLICE_X29Y74.D6      net (fanout=7)        1.104   DAC_output_2/DAC_input_suppressed<12>
    SLICE_X29Y74.D       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X29Y74.C6      net (fanout=22)       0.191   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X29Y74.C       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X28Y75.A2      net (fanout=24)       0.756   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X28Y75.A       Tilo                  0.235   DAC_thresh_pol_2
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X28Y74.B4      net (fanout=9)        0.528   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X28Y74.B       Tilo                  0.235   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[5]_MUX_754_o
                                                       DAC_output_2/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o151
    SLICE_X28Y74.C6      net (fanout=1)        0.261   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[5]_MUX_754_o
    SLICE_X28Y74.CMUX    Tilo                  0.403   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[5]_MUX_754_o
                                                       DAC_output_2/Mmux_DAC_input_scaled<12>_3
                                                       DAC_output_2/Mmux_DAC_input_scaled<12>_2_f7
    SLICE_X25Y69.B3      net (fanout=1)        1.068   DAC_output_2/DAC_input_scaled<12>
    SLICE_X25Y69.B       Tilo                  0.259   DAC_output_2/SF131
                                                       DAC_output_2/SF1312
    SLICE_X25Y69.C4      net (fanout=1)        0.320   DAC_output_2/SF1312
    SLICE_X25Y69.C       Tilo                  0.259   DAC_output_2/SF131
                                                       DAC_output_2/SF1313
    SLICE_X23Y74.C5      net (fanout=2)        0.850   DAC_output_2/SF131
    SLICE_X23Y74.C       Tilo                  0.259   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o12
    SLICE_X23Y74.B4      net (fanout=1)        0.352   DAC_output_2/main_state[31]_GND_66_o_Select_51_o12
    SLICE_X23Y74.B       Tilo                  0.259   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X23Y74.A5      net (fanout=1)        0.230   DAC_output_2/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X23Y74.CLK     Tas                   0.373   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_2/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     15.528ns (5.359ns logic, 10.169ns route)
                                                       (34.5% logic, 65.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     -3.662ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_2_2 (FF)
  Destination:          DAC_output_2/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      15.523ns (Levels of Logic = 19)
  Clock Path Skew:      -0.008ns (0.632 - 0.640)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_2_2 to DAC_output_2/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X34Y71.CQ      Tcko                  0.525   DAC_register_2<2>
                                                       DAC_register_2_2
    SLICE_X32Y71.AX      net (fanout=4)        0.767   DAC_register_2<2>
    SLICE_X32Y71.COUT    Taxcy                 0.281   DAC_register_2<0>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X32Y72.CIN     net (fanout=1)        0.082   DAC_output_2/Madd_n0206_Madd_Madd_cy<7>
    SLICE_X32Y72.COUT    Tbyp                  0.091   DAC_register_2<3>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.COUT    Tbyp                  0.091   TTL_out_user<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.BMUX    Tcinb                 0.277   DAC_register_2<6>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X33Y74.A5      net (fanout=36)       1.212   DAC_output_2/n0206<17>
    SLICE_X33Y74.A       Tilo                  0.259   WS2812controller/GRB_reg<9>
                                                       DAC_output_2/Mmux_multiplier_in181
    SLICE_X34Y72.D5      net (fanout=3)        1.399   DAC_output_2/multiplier_in<9>
    SLICE_X34Y72.COUT    Topcyd                0.312   DAC_register_2<9>
                                                       DAC_output_2/Madd_add_result_lut<7>
                                                       DAC_output_2/Madd_add_result_cy<7>
    SLICE_X34Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_add_result_cy<7>
    SLICE_X34Y73.COUT    Tbyp                  0.093   DAC_output_2/Madd_add_result_cy<11>
                                                       DAC_output_2/Madd_add_result_cy<11>
    SLICE_X34Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_add_result_cy<11>
    SLICE_X34Y74.DMUX    Tcind                 0.320   DAC_register_2<14>
                                                       DAC_output_2/Madd_add_result_xor<15>
    SLICE_X33Y71.B3      net (fanout=91)       1.083   DAC_output_2/add_result<15>
    SLICE_X33Y71.B       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[12]_MUX_663_o
                                                       DAC_output_2/Mmux_DAC_input_suppressed41
    SLICE_X29Y74.D6      net (fanout=7)        1.104   DAC_output_2/DAC_input_suppressed<12>
    SLICE_X29Y74.D       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X29Y74.C6      net (fanout=22)       0.191   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X29Y74.C       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X28Y75.A2      net (fanout=24)       0.756   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X28Y75.A       Tilo                  0.235   DAC_thresh_pol_2
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X28Y74.B4      net (fanout=9)        0.528   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X28Y74.B       Tilo                  0.235   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[5]_MUX_754_o
                                                       DAC_output_2/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o151
    SLICE_X28Y74.C6      net (fanout=1)        0.261   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[5]_MUX_754_o
    SLICE_X28Y74.CMUX    Tilo                  0.403   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[5]_MUX_754_o
                                                       DAC_output_2/Mmux_DAC_input_scaled<12>_3
                                                       DAC_output_2/Mmux_DAC_input_scaled<12>_2_f7
    SLICE_X25Y69.B3      net (fanout=1)        1.068   DAC_output_2/DAC_input_scaled<12>
    SLICE_X25Y69.B       Tilo                  0.259   DAC_output_2/SF131
                                                       DAC_output_2/SF1312
    SLICE_X25Y69.C4      net (fanout=1)        0.320   DAC_output_2/SF1312
    SLICE_X25Y69.C       Tilo                  0.259   DAC_output_2/SF131
                                                       DAC_output_2/SF1313
    SLICE_X23Y74.C5      net (fanout=2)        0.850   DAC_output_2/SF131
    SLICE_X23Y74.C       Tilo                  0.259   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o12
    SLICE_X23Y74.B4      net (fanout=1)        0.352   DAC_output_2/main_state[31]_GND_66_o_Select_51_o12
    SLICE_X23Y74.B       Tilo                  0.259   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X23Y74.A5      net (fanout=1)        0.230   DAC_output_2/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X23Y74.CLK     Tas                   0.373   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_2/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     15.523ns (5.308ns logic, 10.215ns route)
                                                       (34.2% logic, 65.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -3.645ns (requirement - (data path - clock path skew + uncertainty))
  Source:               DAC_register_2_6 (FF)
  Destination:          DAC_output_2/DAC_DIN (FF)
  Requirement:          11.904ns
  Data Path Delay:      15.501ns (Levels of Logic = 18)
  Clock Path Skew:      -0.013ns (0.632 - 0.645)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 11.904ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: DAC_register_2_6 to DAC_output_2/DAC_DIN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y74.DQ      Tcko                  0.476   DAC_register_2<6>
                                                       DAC_register_2_6
    SLICE_X32Y72.A6      net (fanout=6)        0.803   DAC_register_2<6>
    SLICE_X32Y72.COUT    Topcya                0.472   DAC_register_2<3>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_lut<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<11>
    SLICE_X32Y73.COUT    Tbyp                  0.091   TTL_out_user<8>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_n0206_Madd_Madd_cy<15>
    SLICE_X32Y74.BMUX    Tcinb                 0.277   DAC_register_2<6>
                                                       DAC_output_2/Madd_n0206_Madd_Madd_xor<17>
    SLICE_X33Y74.A5      net (fanout=36)       1.212   DAC_output_2/n0206<17>
    SLICE_X33Y74.A       Tilo                  0.259   WS2812controller/GRB_reg<9>
                                                       DAC_output_2/Mmux_multiplier_in181
    SLICE_X34Y72.D5      net (fanout=3)        1.399   DAC_output_2/multiplier_in<9>
    SLICE_X34Y72.COUT    Topcyd                0.312   DAC_register_2<9>
                                                       DAC_output_2/Madd_add_result_lut<7>
                                                       DAC_output_2/Madd_add_result_cy<7>
    SLICE_X34Y73.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_add_result_cy<7>
    SLICE_X34Y73.COUT    Tbyp                  0.093   DAC_output_2/Madd_add_result_cy<11>
                                                       DAC_output_2/Madd_add_result_cy<11>
    SLICE_X34Y74.CIN     net (fanout=1)        0.003   DAC_output_2/Madd_add_result_cy<11>
    SLICE_X34Y74.DMUX    Tcind                 0.320   DAC_register_2<14>
                                                       DAC_output_2/Madd_add_result_xor<15>
    SLICE_X33Y71.B3      net (fanout=91)       1.083   DAC_output_2/add_result<15>
    SLICE_X33Y71.B       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[12]_MUX_663_o
                                                       DAC_output_2/Mmux_DAC_input_suppressed41
    SLICE_X29Y74.D6      net (fanout=7)        1.104   DAC_output_2/DAC_input_suppressed<12>
    SLICE_X29Y74.D       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o7111
    SLICE_X29Y74.C6      net (fanout=22)       0.191   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
    SLICE_X29Y74.C       Tilo                  0.259   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o711
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o712
    SLICE_X28Y75.A2      net (fanout=24)       0.756   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o71
    SLICE_X28Y75.A       Tilo                  0.235   DAC_thresh_pol_2
                                                       DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o73
    SLICE_X26Y75.A6      net (fanout=9)        0.403   DAC_output_2/DAC_input_suppressed[14]_DAC_input_suppressed[15]_equal_24_o
    SLICE_X26Y75.A       Tilo                  0.254   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[9]_MUX_708_o
                                                       DAC_output_2/Mmux_DAC_input_suppressed[15]_DAC_input_suppressed[0]_MUX_759_o161
    SLICE_X26Y75.C1      net (fanout=1)        0.540   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[6]_MUX_753_o
    SLICE_X26Y75.CMUX    Tilo                  0.430   DAC_output_2/DAC_input_suppressed[15]_DAC_input_suppressed[9]_MUX_708_o
                                                       DAC_output_2/Mmux_DAC_input_scaled<13>_3
                                                       DAC_output_2/Mmux_DAC_input_scaled<13>_2_f7
    SLICE_X25Y69.B6      net (fanout=1)        0.841   DAC_output_2/DAC_input_scaled<13>
    SLICE_X25Y69.B       Tilo                  0.259   DAC_output_2/SF131
                                                       DAC_output_2/SF1312
    SLICE_X25Y69.C4      net (fanout=1)        0.320   DAC_output_2/SF1312
    SLICE_X25Y69.C       Tilo                  0.259   DAC_output_2/SF131
                                                       DAC_output_2/SF1313
    SLICE_X23Y74.C5      net (fanout=2)        0.850   DAC_output_2/SF131
    SLICE_X23Y74.C       Tilo                  0.259   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o12
    SLICE_X23Y74.B4      net (fanout=1)        0.352   DAC_output_2/main_state[31]_GND_66_o_Select_51_o12
    SLICE_X23Y74.B       Tilo                  0.259   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X23Y74.A5      net (fanout=1)        0.230   DAC_output_2/main_state[31]_GND_66_o_Select_51_o13
    SLICE_X23Y74.CLK     Tas                   0.373   DAC_output_2/DAC_DIN
                                                       DAC_output_2/main_state[31]_GND_66_o_Select_51_o17
                                                       DAC_output_2/DAC_DIN
    -------------------------------------------------  ---------------------------
    Total                                     15.501ns (5.405ns logic, 10.096ns route)
                                                       (34.9% logic, 65.1% route)

--------------------------------------------------------------------------------

Hold Paths: TS_variable_freq_clk_generator_inst_clkout_i = PERIOD TIMEGRP
        "variable_freq_clk_generator_inst_clkout_i" TS_SYS_CLK3 / 0.84 HIGH
        50%;
--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 (SLICE_X20Y60.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.385ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.385ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 to SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y60.CQ      Tcko                  0.200   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1
    SLICE_X20Y60.DX      net (fanout=2)        0.137   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1
    SLICE_X20Y60.CLK     Tckdi       (-Th)    -0.048   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2
    -------------------------------------------------  ---------------------------
    Total                                      0.385ns (0.248ns logic, 0.137ns route)
                                                       (64.4% logic, 35.6% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 (SLICE_X20Y60.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.386ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg (FF)
  Destination:          SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.388ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.040 - 0.038)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg to SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X21Y60.AMUX    Tshcko                0.244   DAC_output_1/HPF_output<0>
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg
    SLICE_X20Y60.CX      net (fanout=2)        0.096   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg
    SLICE_X20Y60.CLK     Tckdi       (-Th)    -0.048   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1
    -------------------------------------------------  ---------------------------
    Total                                      0.388ns (0.292ns logic, 0.096ns route)
                                                       (75.3% logic, 24.7% route)

--------------------------------------------------------------------------------

Paths for end point SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X1Y30.ADDRA11), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.390ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc0.count_d2_9 (FF)
  Destination:          SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.393ns (Levels of Logic = 0)
  Clock Path Skew:      0.003ns (0.076 - 0.073)
  Source Clock:         dataclk rising at 0.000ns
  Destination Clock:    dataclk rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc0.count_d2_9 to SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y61.BQ      Tcko                  0.198   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc0.count_d2<10>
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc0.count_d2_9
    RAMB16_X1Y30.ADDRA11 net (fanout=5)        0.261   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc0.count_d2<9>
    RAMB16_X1Y30.CLKA    Trckc_ADDRA (-Th)     0.066   SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.393ns (0.132ns logic, 0.261ns route)
                                                       (33.6% logic, 66.4% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_variable_freq_clk_generator_inst_clkout_i = PERIOD TIMEGRP
        "variable_freq_clk_generator_inst_clkout_i" TS_SYS_CLK3 / 0.84 HIGH
        50%;
--------------------------------------------------------------------------------
Slack: 8.334ns (period - min period limit)
  Period: 11.904ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: RAM_bank_3/RAM_block_10/RAMB16BWER_inst/CLKB
  Logical resource: RAM_bank_3/RAM_block_10/RAMB16BWER_inst/CLKB
  Location pin: RAMB16_X2Y22.CLKB
  Clock network: dataclk
--------------------------------------------------------------------------------
Slack: 8.334ns (period - min period limit)
  Period: 11.904ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: RAM_bank_2/RAM_block_11/RAMB16BWER_inst/CLKB
  Logical resource: RAM_bank_2/RAM_block_11/RAMB16BWER_inst/CLKB
  Location pin: RAMB16_X3Y8.CLKB
  Clock network: dataclk
--------------------------------------------------------------------------------
Slack: 8.334ns (period - min period limit)
  Period: 11.904ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: RAM_bank_1/RAM_block_12/RAMB16BWER_inst/CLKB
  Logical resource: RAM_bank_1/RAM_block_12/RAMB16BWER_inst/CLKB
  Location pin: RAMB16_X1Y24.CLKB
  Clock network: dataclk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_out<1>" OFFSET = OUT 11.93 ns AFTER COMP "hi_in<0>" 
"RISING";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_out<0>" OFFSET = OUT 11.93 ns AFTER COMP "hi_in<0>" 
"RISING";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   8.797ns.
--------------------------------------------------------------------------------

Paths for end point hi_out<0> (Y19.PAD), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  3.133ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               host/core0/core0/hi_busy (FF)
  Destination:          hi_out<0> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Requirement:          11.930ns
  Data Path Delay:      6.913ns (Levels of Logic = 1)
  Clock Path Delay:     1.609ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/hi_busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.557   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.933   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.232   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -7.467   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.207   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X40Y11.CLK     net (fanout=557)      1.748   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.609ns (-5.511ns logic, 7.120ns route)

  Maximum Data Path at Slow Process Corner: host/core0/core0/hi_busy to hi_out<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y11.CQ      Tcko                  0.476   host/okCH<0>
                                                       host/core0/core0/hi_busy
    Y19.O                net (fanout=1)        3.715   host/okCH<0>
    Y19.PAD              Tioop                 2.722   hi_out<0>
                                                       host/obuf0
                                                       hi_out<0>
    -------------------------------------------------  ---------------------------
    Total                                      6.913ns (3.198ns logic, 3.715ns route)
                                                       (46.3% logic, 53.7% route)

--------------------------------------------------------------------------------

Fastest Paths: COMP "hi_out<0>" OFFSET = OUT 11.93 ns AFTER COMP "hi_in<0>" "RISING";
--------------------------------------------------------------------------------

Paths for end point hi_out<0> (Y19.PAD), 1 path
--------------------------------------------------------------------------------
Delay (fastest paths):  4.326ns (clock arrival + clock path + data path - uncertainty)
  Source:               host/core0/core0/hi_busy (FF)
  Destination:          hi_out<0> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Data Path Delay:      3.503ns (Levels of Logic = 1)
  Clock Path Delay:     1.098ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/hi_busy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.763   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.327   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.372   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.643   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.394   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X40Y11.CLK     net (fanout=557)      0.704   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.098ns (-1.699ns logic, 2.797ns route)

  Minimum Data Path at Fast Process Corner: host/core0/core0/hi_busy to hi_out<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y11.CQ      Tcko                  0.200   host/okCH<0>
                                                       host/core0/core0/hi_busy
    Y19.O                net (fanout=1)        1.907   host/okCH<0>
    Y19.PAD              Tioop                 1.396   hi_out<0>
                                                       host/obuf0
                                                       hi_out<0>
    -------------------------------------------------  ---------------------------
    Total                                      3.503ns (1.596ns logic, 1.907ns route)
                                                       (45.6% logic, 54.4% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_in<7>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE 
COMP "hi_in<0>"         "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 249 paths analyzed, 249 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is  11.590ns.
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_4 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     1.740ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<7> (PAD)
  Destination:          host/core0/core0/a0/d0/div_4 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      12.650ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<7> to host/core0/core0/a0/d0/div_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB3.I                Tiopi                 1.557   hi_in<7>
                                                       hi_in<7>
                                                       hi_in_7_IBUF
                                                       ProtoComp215.IMUX.18
    SLICE_X11Y22.D2      net (fanout=15)       5.379   hi_in_7_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.379   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_4
    -------------------------------------------------  ---------------------------
    Total                                     12.650ns (2.273ns logic, 10.377ns route)
                                                       (18.0% logic, 82.0% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_2 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     1.765ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<7> (PAD)
  Destination:          host/core0/core0/a0/d0/div_2 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      12.625ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<7> to host/core0/core0/a0/d0/div_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB3.I                Tiopi                 1.557   hi_in<7>
                                                       hi_in<7>
                                                       hi_in_7_IBUF
                                                       ProtoComp215.IMUX.18
    SLICE_X11Y22.D2      net (fanout=15)       5.379   hi_in_7_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.354   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_2
    -------------------------------------------------  ---------------------------
    Total                                     12.625ns (2.248ns logic, 10.377ns route)
                                                       (17.8% logic, 82.2% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_3 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     1.770ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<7> (PAD)
  Destination:          host/core0/core0/a0/d0/div_3 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      12.620ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<7> to host/core0/core0/a0/d0/div_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB3.I                Tiopi                 1.557   hi_in<7>
                                                       hi_in<7>
                                                       hi_in_7_IBUF
                                                       ProtoComp215.IMUX.18
    SLICE_X11Y22.D2      net (fanout=15)       5.379   hi_in_7_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.349   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_3
    -------------------------------------------------  ---------------------------
    Total                                     12.620ns (2.243ns logic, 10.377ns route)
                                                       (17.8% logic, 82.2% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Hold Paths: COMP "hi_in<7>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"
        "RISING";
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/ti_wireupdate (SLICE_X22Y12.A4), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      8.799ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<7> (PAD)
  Destination:          host/core0/core0/ti_wireupdate (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      2.742ns (Levels of Logic = 2)
  Clock Path Delay:     1.168ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<7> to host/core0/core0/ti_wireupdate
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB3.I                Tiopi                 0.763   hi_in<7>
                                                       hi_in<7>
                                                       hi_in_7_IBUF
                                                       ProtoComp215.IMUX.18
    SLICE_X22Y12.A4      net (fanout=15)       1.782   hi_in_7_IBUF
    SLICE_X22Y12.CLK     Tah         (-Th)    -0.197   ok1<28>
                                                       host/core0/core0/Mmux_GND_2_o_host_datain[1]_MUX_727_o11
                                                       host/core0/core0/ti_wireupdate
    -------------------------------------------------  ---------------------------
    Total                                      2.742ns (0.960ns logic, 1.782ns route)
                                                       (35.0% logic, 65.0% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/ti_wireupdate
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X22Y12.CLK     net (fanout=557)      0.747   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.168ns (-1.826ns logic, 2.994ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd2 (SLICE_X22Y16.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.083ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<7> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd2 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.003ns (Levels of Logic = 2)
  Clock Path Delay:     1.145ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<7> to host/core0/core0/state_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB3.I                Tiopi                 0.763   hi_in<7>
                                                       hi_in<7>
                                                       hi_in_7_IBUF
                                                       ProtoComp215.IMUX.18
    SLICE_X22Y16.A6      net (fanout=15)       2.043   hi_in_7_IBUF
    SLICE_X22Y16.CLK     Tah         (-Th)    -0.197   host/core0/core0/state_FSM_FFd2
                                                       host/core0/core0/state_FSM_FFd2_rstpot
                                                       host/core0/core0/state_FSM_FFd2
    -------------------------------------------------  ---------------------------
    Total                                      3.003ns (0.960ns logic, 2.043ns route)
                                                       (32.0% logic, 68.0% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X22Y16.CLK     net (fanout=557)      0.724   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.145ns (-1.826ns logic, 2.971ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd11 (SLICE_X22Y18.A4), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.126ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<7> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd11 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.044ns (Levels of Logic = 2)
  Clock Path Delay:     1.143ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<7> to host/core0/core0/state_FSM_FFd11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB3.I                Tiopi                 0.763   hi_in<7>
                                                       hi_in<7>
                                                       hi_in_7_IBUF
                                                       ProtoComp215.IMUX.18
    SLICE_X22Y18.A4      net (fanout=15)       2.150   hi_in_7_IBUF
    SLICE_X22Y18.CLK     Tah         (-Th)    -0.131   host/core0/core0/state_FSM_FFd12
                                                       host/core0/core0/state_FSM_FFd11_rstpot
                                                       host/core0/core0/state_FSM_FFd11
    -------------------------------------------------  ---------------------------
    Total                                      3.044ns (0.894ns logic, 2.150ns route)
                                                       (29.4% logic, 70.6% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X22Y18.CLK     net (fanout=557)      0.722   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.143ns (-1.826ns logic, 2.969ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_in<6>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE 
COMP "hi_in<0>"         "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 249 paths analyzed, 249 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is  10.653ns.
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_4 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.677ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<6> (PAD)
  Destination:          host/core0/core0/a0/d0/div_4 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.713ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<6> to host/core0/core0/a0/d0/div_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y3.I                 Tiopi                 1.557   hi_in<6>
                                                       hi_in<6>
                                                       hi_in_6_IBUF
                                                       ProtoComp215.IMUX.17
    SLICE_X11Y22.D1      net (fanout=14)       4.442   hi_in_6_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.379   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_4
    -------------------------------------------------  ---------------------------
    Total                                     11.713ns (2.273ns logic, 9.440ns route)
                                                       (19.4% logic, 80.6% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_2 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.702ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<6> (PAD)
  Destination:          host/core0/core0/a0/d0/div_2 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.688ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<6> to host/core0/core0/a0/d0/div_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y3.I                 Tiopi                 1.557   hi_in<6>
                                                       hi_in<6>
                                                       hi_in_6_IBUF
                                                       ProtoComp215.IMUX.17
    SLICE_X11Y22.D1      net (fanout=14)       4.442   hi_in_6_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.354   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_2
    -------------------------------------------------  ---------------------------
    Total                                     11.688ns (2.248ns logic, 9.440ns route)
                                                       (19.2% logic, 80.8% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_3 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.707ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<6> (PAD)
  Destination:          host/core0/core0/a0/d0/div_3 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.683ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<6> to host/core0/core0/a0/d0/div_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y3.I                 Tiopi                 1.557   hi_in<6>
                                                       hi_in<6>
                                                       hi_in_6_IBUF
                                                       ProtoComp215.IMUX.17
    SLICE_X11Y22.D1      net (fanout=14)       4.442   hi_in_6_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.349   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_3
    -------------------------------------------------  ---------------------------
    Total                                     11.683ns (2.243ns logic, 9.440ns route)
                                                       (19.2% logic, 80.8% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Hold Paths: COMP "hi_in<6>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"
        "RISING";
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/ti_wireupdate (SLICE_X22Y12.A2), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.161ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<6> (PAD)
  Destination:          host/core0/core0/ti_wireupdate (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.104ns (Levels of Logic = 2)
  Clock Path Delay:     1.168ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<6> to host/core0/core0/ti_wireupdate
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y3.I                 Tiopi                 0.763   hi_in<6>
                                                       hi_in<6>
                                                       hi_in_6_IBUF
                                                       ProtoComp215.IMUX.17
    SLICE_X22Y12.A2      net (fanout=14)       2.144   hi_in_6_IBUF
    SLICE_X22Y12.CLK     Tah         (-Th)    -0.197   ok1<28>
                                                       host/core0/core0/Mmux_GND_2_o_host_datain[1]_MUX_727_o11
                                                       host/core0/core0/ti_wireupdate
    -------------------------------------------------  ---------------------------
    Total                                      3.104ns (0.960ns logic, 2.144ns route)
                                                       (30.9% logic, 69.1% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/ti_wireupdate
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X22Y12.CLK     net (fanout=557)      0.747   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.168ns (-1.826ns logic, 2.994ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/ti_reset (SLICE_X23Y15.A5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.168ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<6> (PAD)
  Destination:          host/core0/core0/ti_reset (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.114ns (Levels of Logic = 2)
  Clock Path Delay:     1.171ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<6> to host/core0/core0/ti_reset
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y3.I                 Tiopi                 0.763   hi_in<6>
                                                       hi_in<6>
                                                       hi_in_6_IBUF
                                                       ProtoComp215.IMUX.17
    SLICE_X23Y15.A5      net (fanout=14)       2.196   hi_in_6_IBUF
    SLICE_X23Y15.CLK     Tah         (-Th)    -0.155   host/core0/core0/_n0201_inv
                                                       host/core0/core0/Mmux_GND_2_o_host_datain[0]_MUX_726_o11
                                                       host/core0/core0/ti_reset
    -------------------------------------------------  ---------------------------
    Total                                      3.114ns (0.918ns logic, 2.196ns route)
                                                       (29.5% logic, 70.5% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/ti_reset
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X23Y15.CLK     net (fanout=557)      0.750   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.171ns (-1.826ns logic, 2.997ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/ti_reset (SLICE_X23Y15.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.284ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<6> (PAD)
  Destination:          host/core0/core0/ti_reset (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.230ns (Levels of Logic = 2)
  Clock Path Delay:     1.171ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<6> to host/core0/core0/ti_reset
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y3.I                 Tiopi                 0.763   hi_in<6>
                                                       hi_in<6>
                                                       hi_in_6_IBUF
                                                       ProtoComp215.IMUX.17
    SLICE_X23Y15.D4      net (fanout=14)       2.229   hi_in_6_IBUF
    SLICE_X23Y15.DMUX    Tilo                  0.203   host/core0/core0/_n0201_inv
                                                       host/core0/core0/state[31]_GND_2_o_equal_69_o_inv1_01
    SLICE_X23Y15.SR      net (fanout=2)        0.173   host/core0/core0/state[31]_GND_2_o_equal_69_o_inv1_0
    SLICE_X23Y15.CLK     Tcksr       (-Th)     0.138   host/core0/core0/_n0201_inv
                                                       host/core0/core0/ti_reset
    -------------------------------------------------  ---------------------------
    Total                                      3.230ns (0.828ns logic, 2.402ns route)
                                                       (25.6% logic, 74.4% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/ti_reset
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X23Y15.CLK     net (fanout=557)      0.750   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.171ns (-1.826ns logic, 2.997ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_in<5>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE 
COMP "hi_in<0>"         "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 249 paths analyzed, 249 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is  10.493ns.
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_4 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.837ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<5> (PAD)
  Destination:          host/core0/core0/a0/d0/div_4 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.553ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<5> to host/core0/core0/a0/d0/div_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB4.I                Tiopi                 1.557   hi_in<5>
                                                       hi_in<5>
                                                       hi_in_5_IBUF
                                                       ProtoComp215.IMUX.16
    SLICE_X11Y22.D3      net (fanout=14)       4.282   hi_in_5_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.379   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_4
    -------------------------------------------------  ---------------------------
    Total                                     11.553ns (2.273ns logic, 9.280ns route)
                                                       (19.7% logic, 80.3% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_2 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.862ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<5> (PAD)
  Destination:          host/core0/core0/a0/d0/div_2 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.528ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<5> to host/core0/core0/a0/d0/div_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB4.I                Tiopi                 1.557   hi_in<5>
                                                       hi_in<5>
                                                       hi_in_5_IBUF
                                                       ProtoComp215.IMUX.16
    SLICE_X11Y22.D3      net (fanout=14)       4.282   hi_in_5_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.354   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_2
    -------------------------------------------------  ---------------------------
    Total                                     11.528ns (2.248ns logic, 9.280ns route)
                                                       (19.5% logic, 80.5% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_3 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.867ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<5> (PAD)
  Destination:          host/core0/core0/a0/d0/div_3 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.523ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<5> to host/core0/core0/a0/d0/div_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB4.I                Tiopi                 1.557   hi_in<5>
                                                       hi_in<5>
                                                       hi_in_5_IBUF
                                                       ProtoComp215.IMUX.16
    SLICE_X11Y22.D3      net (fanout=14)       4.282   hi_in_5_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.349   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_3
    -------------------------------------------------  ---------------------------
    Total                                     11.523ns (2.243ns logic, 9.280ns route)
                                                       (19.5% logic, 80.5% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Hold Paths: COMP "hi_in<5>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"
        "RISING";
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/ti_wireupdate (SLICE_X22Y12.A3), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.002ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<5> (PAD)
  Destination:          host/core0/core0/ti_wireupdate (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      2.945ns (Levels of Logic = 2)
  Clock Path Delay:     1.168ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<5> to host/core0/core0/ti_wireupdate
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB4.I                Tiopi                 0.763   hi_in<5>
                                                       hi_in<5>
                                                       hi_in_5_IBUF
                                                       ProtoComp215.IMUX.16
    SLICE_X22Y12.A3      net (fanout=14)       1.985   hi_in_5_IBUF
    SLICE_X22Y12.CLK     Tah         (-Th)    -0.197   ok1<28>
                                                       host/core0/core0/Mmux_GND_2_o_host_datain[1]_MUX_727_o11
                                                       host/core0/core0/ti_wireupdate
    -------------------------------------------------  ---------------------------
    Total                                      2.945ns (0.960ns logic, 1.985ns route)
                                                       (32.6% logic, 67.4% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/ti_wireupdate
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X22Y12.CLK     net (fanout=557)      0.747   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.168ns (-1.826ns logic, 2.994ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/ti_reset (SLICE_X23Y15.A4), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.192ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<5> (PAD)
  Destination:          host/core0/core0/ti_reset (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.138ns (Levels of Logic = 2)
  Clock Path Delay:     1.171ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<5> to host/core0/core0/ti_reset
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB4.I                Tiopi                 0.763   hi_in<5>
                                                       hi_in<5>
                                                       hi_in_5_IBUF
                                                       ProtoComp215.IMUX.16
    SLICE_X23Y15.A4      net (fanout=14)       2.220   hi_in_5_IBUF
    SLICE_X23Y15.CLK     Tah         (-Th)    -0.155   host/core0/core0/_n0201_inv
                                                       host/core0/core0/Mmux_GND_2_o_host_datain[0]_MUX_726_o11
                                                       host/core0/core0/ti_reset
    -------------------------------------------------  ---------------------------
    Total                                      3.138ns (0.918ns logic, 2.220ns route)
                                                       (29.3% logic, 70.7% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/ti_reset
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X23Y15.CLK     net (fanout=557)      0.750   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.171ns (-1.826ns logic, 2.997ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd2 (SLICE_X22Y16.A3), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.272ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<5> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd2 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.192ns (Levels of Logic = 2)
  Clock Path Delay:     1.145ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<5> to host/core0/core0/state_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB4.I                Tiopi                 0.763   hi_in<5>
                                                       hi_in<5>
                                                       hi_in_5_IBUF
                                                       ProtoComp215.IMUX.16
    SLICE_X22Y16.A3      net (fanout=14)       2.232   hi_in_5_IBUF
    SLICE_X22Y16.CLK     Tah         (-Th)    -0.197   host/core0/core0/state_FSM_FFd2
                                                       host/core0/core0/state_FSM_FFd2_rstpot
                                                       host/core0/core0/state_FSM_FFd2
    -------------------------------------------------  ---------------------------
    Total                                      3.192ns (0.960ns logic, 2.232ns route)
                                                       (30.1% logic, 69.9% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X22Y16.CLK     net (fanout=557)      0.724   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.145ns (-1.826ns logic, 2.971ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_in<4>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE 
COMP "hi_in<0>"         "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 249 paths analyzed, 249 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is  10.257ns.
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_4 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     3.073ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<4> (PAD)
  Destination:          host/core0/core0/a0/d0/div_4 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.317ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<4> to host/core0/core0/a0/d0/div_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AA4.I                Tiopi                 1.557   hi_in<4>
                                                       hi_in<4>
                                                       hi_in_4_IBUF
                                                       ProtoComp215.IMUX.15
    SLICE_X11Y22.D4      net (fanout=14)       4.046   hi_in_4_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.379   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_4
    -------------------------------------------------  ---------------------------
    Total                                     11.317ns (2.273ns logic, 9.044ns route)
                                                       (20.1% logic, 79.9% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_2 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     3.098ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<4> (PAD)
  Destination:          host/core0/core0/a0/d0/div_2 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.292ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<4> to host/core0/core0/a0/d0/div_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AA4.I                Tiopi                 1.557   hi_in<4>
                                                       hi_in<4>
                                                       hi_in_4_IBUF
                                                       ProtoComp215.IMUX.15
    SLICE_X11Y22.D4      net (fanout=14)       4.046   hi_in_4_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.354   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_2
    -------------------------------------------------  ---------------------------
    Total                                     11.292ns (2.248ns logic, 9.044ns route)
                                                       (19.9% logic, 80.1% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/a0/d0/div_3 (SLICE_X3Y70.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     3.103ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<4> (PAD)
  Destination:          host/core0/core0/a0/d0/div_3 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          13.330ns
  Data Path Delay:      11.287ns (Levels of Logic = 2)
  Clock Path Delay:     1.335ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<4> to host/core0/core0/a0/d0/div_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AA4.I                Tiopi                 1.557   hi_in<4>
                                                       hi_in<4>
                                                       hi_in_4_IBUF
                                                       ProtoComp215.IMUX.15
    SLICE_X11Y22.D4      net (fanout=14)       4.046   hi_in_4_IBUF
    SLICE_X11Y22.DMUX    Tilo                  0.337   host/core0/core0/hi_addr[3]_GND_2_o_equal_34_o_0
                                                       host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o21
    SLICE_X3Y70.SR       net (fanout=31)       4.998   host/core0/core0/hi_addr[3]_GND_2_o_equal_30_o2
    SLICE_X3Y70.CLK      Trck                  0.349   host/core0/core0/a0/d0/div<4>
                                                       host/core0/core0/a0/d0/div_3
    -------------------------------------------------  ---------------------------
    Total                                     11.287ns (2.243ns logic, 9.044ns route)
                                                       (19.9% logic, 80.1% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/a0/d0/div_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X3Y70.CLK      net (fanout=557)      1.412   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.335ns (-4.752ns logic, 6.087ns route)

--------------------------------------------------------------------------------

Hold Paths: COMP "hi_in<4>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"
        "RISING";
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/ti_wireupdate (SLICE_X22Y12.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      8.829ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<4> (PAD)
  Destination:          host/core0/core0/ti_wireupdate (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      2.772ns (Levels of Logic = 2)
  Clock Path Delay:     1.168ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<4> to host/core0/core0/ti_wireupdate
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AA4.I                Tiopi                 0.763   hi_in<4>
                                                       hi_in<4>
                                                       hi_in_4_IBUF
                                                       ProtoComp215.IMUX.15
    SLICE_X22Y12.A6      net (fanout=14)       1.812   hi_in_4_IBUF
    SLICE_X22Y12.CLK     Tah         (-Th)    -0.197   ok1<28>
                                                       host/core0/core0/Mmux_GND_2_o_host_datain[1]_MUX_727_o11
                                                       host/core0/core0/ti_wireupdate
    -------------------------------------------------  ---------------------------
    Total                                      2.772ns (0.960ns logic, 1.812ns route)
                                                       (34.6% logic, 65.4% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/ti_wireupdate
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X22Y12.CLK     net (fanout=557)      0.747   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.168ns (-1.826ns logic, 2.994ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/ti_reset (SLICE_X23Y15.A3), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.172ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<4> (PAD)
  Destination:          host/core0/core0/ti_reset (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.118ns (Levels of Logic = 2)
  Clock Path Delay:     1.171ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<4> to host/core0/core0/ti_reset
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AA4.I                Tiopi                 0.763   hi_in<4>
                                                       hi_in<4>
                                                       hi_in_4_IBUF
                                                       ProtoComp215.IMUX.15
    SLICE_X23Y15.A3      net (fanout=14)       2.200   hi_in_4_IBUF
    SLICE_X23Y15.CLK     Tah         (-Th)    -0.155   host/core0/core0/_n0201_inv
                                                       host/core0/core0/Mmux_GND_2_o_host_datain[0]_MUX_726_o11
                                                       host/core0/core0/ti_reset
    -------------------------------------------------  ---------------------------
    Total                                      3.118ns (0.918ns logic, 2.200ns route)
                                                       (29.4% logic, 70.6% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/ti_reset
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X23Y15.CLK     net (fanout=557)      0.750   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.171ns (-1.826ns logic, 2.997ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd2 (SLICE_X22Y16.A5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<4> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd2 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          7.500ns
  Data Path Delay:      3.158ns (Levels of Logic = 2)
  Clock Path Delay:     1.145ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<4> to host/core0/core0/state_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AA4.I                Tiopi                 0.763   hi_in<4>
                                                       hi_in<4>
                                                       hi_in_4_IBUF
                                                       ProtoComp215.IMUX.15
    SLICE_X22Y16.A5      net (fanout=14)       2.198   hi_in_4_IBUF
    SLICE_X22Y16.CLK     Tah         (-Th)    -0.197   host/core0/core0/state_FSM_FFd2
                                                       host/core0/core0/state_FSM_FFd2_rstpot
                                                       host/core0/core0/state_FSM_FFd2
    -------------------------------------------------  ---------------------------
    Total                                      3.158ns (0.960ns logic, 2.198ns route)
                                                       (30.4% logic, 69.6% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X22Y16.CLK     net (fanout=557)      0.724   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.145ns (-1.826ns logic, 2.971ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_in<3>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE 
COMP "hi_in<0>"         "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   5.330ns.
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd14 (SLICE_X25Y16.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     8.800ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<3> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd14 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      6.379ns (Levels of Logic = 2)
  Clock Path Delay:     1.324ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<3> to host/core0/core0/state_FSM_FFd14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB8.I                Tiopi                 1.557   hi_in<3>
                                                       hi_in<3>
                                                       hi_in_3_IBUF
                                                       ProtoComp215.IMUX.14
    SLICE_X22Y15.D4      net (fanout=1)        3.396   hi_in_3_IBUF
    SLICE_X22Y15.DMUX    Tilo                  0.326   host/core0/core0/hi_cmd<2>_2
                                                       host/core0/core0/hi_cmd<2>_01
    SLICE_X25Y16.SR      net (fanout=2)        0.632   host/core0/core0/hi_cmd<2>_0
    SLICE_X25Y16.CLK     Tsrck                 0.468   host/core0/core0/state_FSM_FFd14
                                                       host/core0/core0/state_FSM_FFd14
    -------------------------------------------------  ---------------------------
    Total                                      6.379ns (2.351ns logic, 4.028ns route)
                                                       (36.9% logic, 63.1% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y16.CLK     net (fanout=557)      1.401   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.324ns (-4.752ns logic, 6.076ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd16 (SLICE_X24Y16.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     8.850ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<3> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd16 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      6.329ns (Levels of Logic = 2)
  Clock Path Delay:     1.324ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<3> to host/core0/core0/state_FSM_FFd16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB8.I                Tiopi                 1.557   hi_in<3>
                                                       hi_in<3>
                                                       hi_in_3_IBUF
                                                       ProtoComp215.IMUX.14
    SLICE_X22Y15.D4      net (fanout=1)        3.396   hi_in_3_IBUF
    SLICE_X22Y15.DMUX    Tilo                  0.326   host/core0/core0/hi_cmd<2>_2
                                                       host/core0/core0/hi_cmd<2>_01
    SLICE_X24Y16.SR      net (fanout=2)        0.632   host/core0/core0/hi_cmd<2>_0
    SLICE_X24Y16.CLK     Tsrck                 0.418   host/core0/core0/state_FSM_FFd16
                                                       host/core0/core0/state_FSM_FFd16
    -------------------------------------------------  ---------------------------
    Total                                      6.329ns (2.301ns logic, 4.028ns route)
                                                       (36.4% logic, 63.6% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X24Y16.CLK     net (fanout=557)      1.401   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.324ns (-4.752ns logic, 6.076ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd9 (SLICE_X25Y15.SR), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     8.957ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<3> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd9 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      6.251ns (Levels of Logic = 2)
  Clock Path Delay:     1.353ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<3> to host/core0/core0/state_FSM_FFd9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB8.I                Tiopi                 1.557   hi_in<3>
                                                       hi_in<3>
                                                       hi_in_3_IBUF
                                                       ProtoComp215.IMUX.14
    SLICE_X22Y15.D4      net (fanout=1)        3.396   hi_in_3_IBUF
    SLICE_X22Y15.D       Tilo                  0.254   host/core0/core0/hi_cmd<2>_2
                                                       host/core0/core0/hi_cmd<2>_21
    SLICE_X25Y15.SR      net (fanout=1)        0.576   host/core0/core0/hi_cmd<2>_2
    SLICE_X25Y15.CLK     Tsrck                 0.468   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd9
    -------------------------------------------------  ---------------------------
    Total                                      6.251ns (2.279ns logic, 3.972ns route)
                                                       (36.5% logic, 63.5% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y15.CLK     net (fanout=557)      1.430   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.353ns (-4.752ns logic, 6.105ns route)

--------------------------------------------------------------------------------

Hold Paths: COMP "hi_in<3>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"
        "RISING";
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd6 (SLICE_X25Y15.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      7.897ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<3> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd6 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      2.645ns (Levels of Logic = 2)
  Clock Path Delay:     1.173ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<3> to host/core0/core0/state_FSM_FFd6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB8.I                Tiopi                 0.763   hi_in<3>
                                                       hi_in<3>
                                                       hi_in_3_IBUF
                                                       ProtoComp215.IMUX.14
    SLICE_X22Y15.D4      net (fanout=1)        1.592   hi_in_3_IBUF
    SLICE_X22Y15.D       Tilo                  0.156   host/core0/core0/hi_cmd<2>_2
                                                       host/core0/core0/hi_cmd<2>_21
    SLICE_X25Y15.SR      net (fanout=1)        0.265   host/core0/core0/hi_cmd<2>_2
    SLICE_X25Y15.CLK     Tcksr       (-Th)     0.131   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd6
    -------------------------------------------------  ---------------------------
    Total                                      2.645ns (0.788ns logic, 1.857ns route)
                                                       (29.8% logic, 70.2% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y15.CLK     net (fanout=557)      0.752   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.173ns (-1.826ns logic, 2.999ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd9 (SLICE_X25Y15.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      7.901ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<3> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd9 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      2.649ns (Levels of Logic = 2)
  Clock Path Delay:     1.173ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<3> to host/core0/core0/state_FSM_FFd9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB8.I                Tiopi                 0.763   hi_in<3>
                                                       hi_in<3>
                                                       hi_in_3_IBUF
                                                       ProtoComp215.IMUX.14
    SLICE_X22Y15.D4      net (fanout=1)        1.592   hi_in_3_IBUF
    SLICE_X22Y15.D       Tilo                  0.156   host/core0/core0/hi_cmd<2>_2
                                                       host/core0/core0/hi_cmd<2>_21
    SLICE_X25Y15.SR      net (fanout=1)        0.265   host/core0/core0/hi_cmd<2>_2
    SLICE_X25Y15.CLK     Tcksr       (-Th)     0.127   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd9
    -------------------------------------------------  ---------------------------
    Total                                      2.649ns (0.792ns logic, 1.857ns route)
                                                       (29.9% logic, 70.1% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y15.CLK     net (fanout=557)      0.752   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.173ns (-1.826ns logic, 2.999ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd14 (SLICE_X25Y16.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      8.002ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<3> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd14 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      2.721ns (Levels of Logic = 2)
  Clock Path Delay:     1.144ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<3> to host/core0/core0/state_FSM_FFd14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB8.I                Tiopi                 0.763   hi_in<3>
                                                       hi_in<3>
                                                       hi_in_3_IBUF
                                                       ProtoComp215.IMUX.14
    SLICE_X22Y15.D4      net (fanout=1)        1.592   hi_in_3_IBUF
    SLICE_X22Y15.DMUX    Tilo                  0.191   host/core0/core0/hi_cmd<2>_2
                                                       host/core0/core0/hi_cmd<2>_01
    SLICE_X25Y16.SR      net (fanout=2)        0.302   host/core0/core0/hi_cmd<2>_0
    SLICE_X25Y16.CLK     Tcksr       (-Th)     0.127   host/core0/core0/state_FSM_FFd14
                                                       host/core0/core0/state_FSM_FFd14
    -------------------------------------------------  ---------------------------
    Total                                      2.721ns (0.827ns logic, 1.894ns route)
                                                       (30.4% logic, 69.6% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y16.CLK     net (fanout=557)      0.723   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.144ns (-1.826ns logic, 2.970ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_in<2>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE 
COMP "hi_in<0>"         "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   6.044ns.
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd17 (SLICE_X24Y15.C4), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     8.086ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<2> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd17 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      7.122ns (Levels of Logic = 4)
  Clock Path Delay:     1.353ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<2> to host/core0/core0/state_FSM_FFd17
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB7.I                Tiopi                 1.557   hi_in<2>
                                                       hi_in<2>
                                                       hi_in_2_IBUF
                                                       ProtoComp215.IMUX.13
    SLICE_X25Y15.D5      net (fanout=2)        3.676   hi_in_2_IBUF
    SLICE_X25Y15.DMUX    Tilo                  0.337   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd17-In2
    SLICE_X24Y15.B1      net (fanout=1)        0.725   host/core0/core0/state_FSM_FFd17-In2
    SLICE_X24Y15.B       Tilo                  0.235   host/core0/core0/state_FSM_FFd7
                                                       host/core0/core0/state_FSM_FFd17-In3
    SLICE_X24Y15.C4      net (fanout=1)        0.371   host/core0/core0/state_FSM_FFd17-In3
    SLICE_X24Y15.CLK     Tas                   0.221   host/core0/core0/state_FSM_FFd7
                                                       host/core0/core0/state_FSM_FFd17-In4
                                                       host/core0/core0/state_FSM_FFd17
    -------------------------------------------------  ---------------------------
    Total                                      7.122ns (2.350ns logic, 4.772ns route)
                                                       (33.0% logic, 67.0% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd17
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X24Y15.CLK     net (fanout=557)      1.430   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.353ns (-4.752ns logic, 6.105ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd6 (SLICE_X25Y15.AX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     8.388ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<2> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd6 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      6.820ns (Levels of Logic = 2)
  Clock Path Delay:     1.353ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<2> to host/core0/core0/state_FSM_FFd6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB7.I                Tiopi                 1.557   hi_in<2>
                                                       hi_in<2>
                                                       hi_in_2_IBUF
                                                       ProtoComp215.IMUX.13
    SLICE_X25Y16.D1      net (fanout=2)        4.189   hi_in_2_IBUF
    SLICE_X25Y16.D       Tilo                  0.259   host/core0/core0/state_FSM_FFd14
                                                       host/core0/core0/state_FSM_FFd14-In11
    SLICE_X25Y15.AX      net (fanout=1)        0.701   host/core0/core0/state_FSM_FFd14-In1
    SLICE_X25Y15.CLK     Tdick                 0.114   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd6
    -------------------------------------------------  ---------------------------
    Total                                      6.820ns (1.930ns logic, 4.890ns route)
                                                       (28.3% logic, 71.7% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y15.CLK     net (fanout=557)      1.430   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.353ns (-4.752ns logic, 6.105ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd16 (SLICE_X24Y16.AX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     8.707ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<2> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd16 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      6.472ns (Levels of Logic = 2)
  Clock Path Delay:     1.324ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<2> to host/core0/core0/state_FSM_FFd16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB7.I                Tiopi                 1.557   hi_in<2>
                                                       hi_in<2>
                                                       hi_in_2_IBUF
                                                       ProtoComp215.IMUX.13
    SLICE_X25Y15.D5      net (fanout=2)        3.676   hi_in_2_IBUF
    SLICE_X25Y15.D       Tilo                  0.259   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd16-In11
    SLICE_X24Y16.AX      net (fanout=1)        0.866   host/core0/core0/state_FSM_FFd16-In1
    SLICE_X24Y16.CLK     Tdick                 0.114   host/core0/core0/state_FSM_FFd16
                                                       host/core0/core0/state_FSM_FFd16
    -------------------------------------------------  ---------------------------
    Total                                      6.472ns (1.930ns logic, 4.542ns route)
                                                       (29.8% logic, 70.2% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X24Y16.CLK     net (fanout=557)      1.401   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.324ns (-4.752ns logic, 6.076ns route)

--------------------------------------------------------------------------------

Hold Paths: COMP "hi_in<2>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"
        "RISING";
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd9 (SLICE_X25Y15.D5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      8.019ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<2> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd9 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      2.767ns (Levels of Logic = 2)
  Clock Path Delay:     1.173ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<2> to host/core0/core0/state_FSM_FFd9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB7.I                Tiopi                 0.763   hi_in<2>
                                                       hi_in<2>
                                                       hi_in_2_IBUF
                                                       ProtoComp215.IMUX.13
    SLICE_X25Y15.D5      net (fanout=2)        1.789   hi_in_2_IBUF
    SLICE_X25Y15.CLK     Tah         (-Th)    -0.215   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd16-In11
                                                       host/core0/core0/state_FSM_FFd9
    -------------------------------------------------  ---------------------------
    Total                                      2.767ns (0.978ns logic, 1.789ns route)
                                                       (35.3% logic, 64.7% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y15.CLK     net (fanout=557)      0.752   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.173ns (-1.826ns logic, 2.999ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd14 (SLICE_X25Y16.D1), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      8.356ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<2> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd14 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      3.075ns (Levels of Logic = 2)
  Clock Path Delay:     1.144ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<2> to host/core0/core0/state_FSM_FFd14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB7.I                Tiopi                 0.763   hi_in<2>
                                                       hi_in<2>
                                                       hi_in_2_IBUF
                                                       ProtoComp215.IMUX.13
    SLICE_X25Y16.D1      net (fanout=2)        2.097   hi_in_2_IBUF
    SLICE_X25Y16.CLK     Tah         (-Th)    -0.215   host/core0/core0/state_FSM_FFd14
                                                       host/core0/core0/state_FSM_FFd14-In11
                                                       host/core0/core0/state_FSM_FFd14
    -------------------------------------------------  ---------------------------
    Total                                      3.075ns (0.978ns logic, 2.097ns route)
                                                       (31.8% logic, 68.2% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y16.CLK     net (fanout=557)      0.723   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.144ns (-1.826ns logic, 2.970ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd16 (SLICE_X24Y16.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      8.446ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<2> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd16 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      3.165ns (Levels of Logic = 2)
  Clock Path Delay:     1.144ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<2> to host/core0/core0/state_FSM_FFd16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB7.I                Tiopi                 0.763   hi_in<2>
                                                       hi_in<2>
                                                       hi_in_2_IBUF
                                                       ProtoComp215.IMUX.13
    SLICE_X25Y15.D5      net (fanout=2)        1.789   hi_in_2_IBUF
    SLICE_X25Y15.D       Tilo                  0.156   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd16-In11
    SLICE_X24Y16.AX      net (fanout=1)        0.409   host/core0/core0/state_FSM_FFd16-In1
    SLICE_X24Y16.CLK     Tckdi       (-Th)    -0.048   host/core0/core0/state_FSM_FFd16
                                                       host/core0/core0/state_FSM_FFd16
    -------------------------------------------------  ---------------------------
    Total                                      3.165ns (0.967ns logic, 2.198ns route)
                                                       (30.6% logic, 69.4% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X24Y16.CLK     net (fanout=557)      0.723   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.144ns (-1.826ns logic, 2.970ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: COMP "hi_in<1>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE 
COMP "hi_in<0>"         "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   7.262ns.
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd17 (SLICE_X24Y15.C4), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     6.868ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<1> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd17 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      8.340ns (Levels of Logic = 4)
  Clock Path Delay:     1.353ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<1> to host/core0/core0/state_FSM_FFd17
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB20.I               Tiopi                 1.557   hi_in<1>
                                                       hi_in<1>
                                                       hi_in_1_IBUF
                                                       ProtoComp215.IMUX.12
    SLICE_X25Y15.D4      net (fanout=2)        4.894   hi_in_1_IBUF
    SLICE_X25Y15.DMUX    Tilo                  0.337   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd17-In2
    SLICE_X24Y15.B1      net (fanout=1)        0.725   host/core0/core0/state_FSM_FFd17-In2
    SLICE_X24Y15.B       Tilo                  0.235   host/core0/core0/state_FSM_FFd7
                                                       host/core0/core0/state_FSM_FFd17-In3
    SLICE_X24Y15.C4      net (fanout=1)        0.371   host/core0/core0/state_FSM_FFd17-In3
    SLICE_X24Y15.CLK     Tas                   0.221   host/core0/core0/state_FSM_FFd7
                                                       host/core0/core0/state_FSM_FFd17-In4
                                                       host/core0/core0/state_FSM_FFd17
    -------------------------------------------------  ---------------------------
    Total                                      8.340ns (2.350ns logic, 5.990ns route)
                                                       (28.2% logic, 71.8% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd17
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X24Y15.CLK     net (fanout=557)      1.430   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.353ns (-4.752ns logic, 6.105ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd16 (SLICE_X24Y16.AX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     7.489ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<1> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd16 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      7.690ns (Levels of Logic = 2)
  Clock Path Delay:     1.324ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<1> to host/core0/core0/state_FSM_FFd16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB20.I               Tiopi                 1.557   hi_in<1>
                                                       hi_in<1>
                                                       hi_in_1_IBUF
                                                       ProtoComp215.IMUX.12
    SLICE_X25Y15.D4      net (fanout=2)        4.894   hi_in_1_IBUF
    SLICE_X25Y15.D       Tilo                  0.259   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd16-In11
    SLICE_X24Y16.AX      net (fanout=1)        0.866   host/core0/core0/state_FSM_FFd16-In1
    SLICE_X24Y16.CLK     Tdick                 0.114   host/core0/core0/state_FSM_FFd16
                                                       host/core0/core0/state_FSM_FFd16
    -------------------------------------------------  ---------------------------
    Total                                      7.690ns (1.930ns logic, 5.760ns route)
                                                       (25.1% logic, 74.9% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X24Y16.CLK     net (fanout=557)      1.401   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.324ns (-4.752ns logic, 6.076ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd6 (SLICE_X25Y15.AX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     7.675ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_in<1> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd6 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          14.130ns
  Data Path Delay:      7.533ns (Levels of Logic = 2)
  Clock Path Delay:     1.353ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_in<1> to host/core0/core0/state_FSM_FFd6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB20.I               Tiopi                 1.557   hi_in<1>
                                                       hi_in<1>
                                                       hi_in_1_IBUF
                                                       ProtoComp215.IMUX.12
    SLICE_X25Y16.D4      net (fanout=2)        4.902   hi_in_1_IBUF
    SLICE_X25Y16.D       Tilo                  0.259   host/core0/core0/state_FSM_FFd14
                                                       host/core0/core0/state_FSM_FFd14-In11
    SLICE_X25Y15.AX      net (fanout=1)        0.701   host/core0/core0/state_FSM_FFd14-In1
    SLICE_X25Y15.CLK     Tdick                 0.114   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd6
    -------------------------------------------------  ---------------------------
    Total                                      7.533ns (1.930ns logic, 5.603ns route)
                                                       (25.6% logic, 74.4% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y15.CLK     net (fanout=557)      1.430   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.353ns (-4.752ns logic, 6.105ns route)

--------------------------------------------------------------------------------

Hold Paths: COMP "hi_in<1>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"
        "RISING";
--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd9 (SLICE_X25Y15.D4), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      8.867ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<1> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd9 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      3.615ns (Levels of Logic = 2)
  Clock Path Delay:     1.173ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<1> to host/core0/core0/state_FSM_FFd9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB20.I               Tiopi                 0.763   hi_in<1>
                                                       hi_in<1>
                                                       hi_in_1_IBUF
                                                       ProtoComp215.IMUX.12
    SLICE_X25Y15.D4      net (fanout=2)        2.637   hi_in_1_IBUF
    SLICE_X25Y15.CLK     Tah         (-Th)    -0.215   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd16-In11
                                                       host/core0/core0/state_FSM_FFd9
    -------------------------------------------------  ---------------------------
    Total                                      3.615ns (0.978ns logic, 2.637ns route)
                                                       (27.1% logic, 72.9% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y15.CLK     net (fanout=557)      0.752   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.173ns (-1.826ns logic, 2.999ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd14 (SLICE_X25Y16.D4), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      8.904ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<1> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd14 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      3.623ns (Levels of Logic = 2)
  Clock Path Delay:     1.144ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<1> to host/core0/core0/state_FSM_FFd14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB20.I               Tiopi                 0.763   hi_in<1>
                                                       hi_in<1>
                                                       hi_in_1_IBUF
                                                       ProtoComp215.IMUX.12
    SLICE_X25Y16.D4      net (fanout=2)        2.645   hi_in_1_IBUF
    SLICE_X25Y16.CLK     Tah         (-Th)    -0.215   host/core0/core0/state_FSM_FFd14
                                                       host/core0/core0/state_FSM_FFd14-In11
                                                       host/core0/core0/state_FSM_FFd14
    -------------------------------------------------  ---------------------------
    Total                                      3.623ns (0.978ns logic, 2.645ns route)
                                                       (27.0% logic, 73.0% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y16.CLK     net (fanout=557)      0.723   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.144ns (-1.826ns logic, 2.970ns route)

--------------------------------------------------------------------------------

Paths for end point host/core0/core0/state_FSM_FFd6 (SLICE_X25Y15.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      9.204ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_in<1> (PAD)
  Destination:          host/core0/core0/state_FSM_FFd6 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          6.700ns
  Data Path Delay:      3.952ns (Levels of Logic = 2)
  Clock Path Delay:     1.173ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_in<1> to host/core0/core0/state_FSM_FFd6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB20.I               Tiopi                 0.763   hi_in<1>
                                                       hi_in<1>
                                                       hi_in_1_IBUF
                                                       ProtoComp215.IMUX.12
    SLICE_X25Y16.D4      net (fanout=2)        2.645   hi_in_1_IBUF
    SLICE_X25Y16.D       Tilo                  0.156   host/core0/core0/state_FSM_FFd14
                                                       host/core0/core0/state_FSM_FFd14-In11
    SLICE_X25Y15.AX      net (fanout=1)        0.329   host/core0/core0/state_FSM_FFd14-In1
    SLICE_X25Y15.CLK     Tckdi       (-Th)    -0.059   host/core0/core0/state_FSM_FFd9
                                                       host/core0/core0/state_FSM_FFd6
    -------------------------------------------------  ---------------------------
    Total                                      3.952ns (0.978ns logic, 2.974ns route)
                                                       (24.7% logic, 75.3% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/core0/core0/state_FSM_FFd6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    SLICE_X25Y15.CLK     net (fanout=557)      0.752   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.173ns (-1.826ns logic, 2.999ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "okHostINOUT_grp" OFFSET = IN 9.83 ns VALID 9.83 ns 
BEFORE COMP         "hi_in<0>" "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 16 paths analyzed, 16 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   5.720ns.
--------------------------------------------------------------------------------

Paths for end point host/delays[5].fdrein0 (ILOGIC_X20Y0.DDLY), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     4.110ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_inout<5> (PAD)
  Destination:          host/delays[5].fdrein0 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          9.830ns
  Data Path Delay:      7.331ns (Levels of Logic = 3)
  Clock Path Delay:     1.886ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_inout<5> to host/delays[5].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V15.I                Tiopi                 1.557   hi_inout<5>
                                                       hi_inout<5>
                                                       host/delays[5].iobf0/IBUF
                                                       ProtoComp208.IMUX.5
    IODELAY_X20Y0.IDATAINnet (fanout=1)        0.153   host/iobf0_hi_datain<5>
    IODELAY_X20Y0.DATAOUTTioddo_IDATAIN        5.082   host/delays[5].iodelay_inst
                                                       host/delays[5].iodelay_inst
    ILOGIC_X20Y0.DDLY    net (fanout=1)        0.007   host/iodly0_datain<5>
    ILOGIC_X20Y0.CLK0    Tidockd               0.532   host/hi_datain<5>
                                                       ProtoComp286.D2OFFBYP_SRC.5
                                                       host/delays[5].fdrein0
    -------------------------------------------------  ---------------------------
    Total                                      7.331ns (7.171ns logic, 0.160ns route)
                                                       (97.8% logic, 2.2% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/delays[5].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    ILOGIC_X20Y0.CLK0    net (fanout=557)      1.963   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.886ns (-4.752ns logic, 6.638ns route)

--------------------------------------------------------------------------------

Paths for end point host/delays[15].fdrein0 (ILOGIC_X25Y1.DDLY), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     4.110ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_inout<15> (PAD)
  Destination:          host/delays[15].fdrein0 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          9.830ns
  Data Path Delay:      7.331ns (Levels of Logic = 3)
  Clock Path Delay:     1.886ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_inout<15> to host/delays[15].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AA20.I               Tiopi                 1.557   hi_inout<15>
                                                       hi_inout<15>
                                                       host/delays[15].iobf0/IBUF
                                                       ProtoComp208.IMUX.16
    IODELAY_X25Y1.IDATAINnet (fanout=1)        0.153   host/iobf0_hi_datain<15>
    IODELAY_X25Y1.DATAOUTTioddo_IDATAIN        5.082   host/delays[15].iodelay_inst
                                                       host/delays[15].iodelay_inst
    ILOGIC_X25Y1.DDLY    net (fanout=1)        0.007   host/iodly0_datain<15>
    ILOGIC_X25Y1.CLK0    Tidockd               0.532   host/hi_datain<15>
                                                       ProtoComp286.D2OFFBYP_SRC.15
                                                       host/delays[15].fdrein0
    -------------------------------------------------  ---------------------------
    Total                                      7.331ns (7.171ns logic, 0.160ns route)
                                                       (97.8% logic, 2.2% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/delays[15].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    ILOGIC_X25Y1.CLK0    net (fanout=557)      1.963   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.886ns (-4.752ns logic, 6.638ns route)

--------------------------------------------------------------------------------

Paths for end point host/delays[11].fdrein0 (ILOGIC_X7Y0.DDLY), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     4.131ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               hi_inout<11> (PAD)
  Destination:          host/delays[11].fdrein0 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          9.830ns
  Data Path Delay:      7.331ns (Levels of Logic = 3)
  Clock Path Delay:     1.907ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: hi_inout<11> to host/delays[11].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB6.I                Tiopi                 1.557   hi_inout<11>
                                                       hi_inout<11>
                                                       host/delays[11].iobf0/IBUF
                                                       ProtoComp208.IMUX.12
    IODELAY_X7Y0.IDATAIN net (fanout=1)        0.153   host/iobf0_hi_datain<11>
    IODELAY_X7Y0.DATAOUT Tioddo_IDATAIN        5.082   host/delays[11].iodelay_inst
                                                       host/delays[11].iodelay_inst
    ILOGIC_X7Y0.DDLY     net (fanout=1)        0.007   host/iodly0_datain<11>
    ILOGIC_X7Y0.CLK0     Tidockd               0.532   host/hi_datain<11>
                                                       ProtoComp286.D2OFFBYP_SRC.11
                                                       host/delays[11].fdrein0
    -------------------------------------------------  ---------------------------
    Total                                      7.331ns (7.171ns logic, 0.160ns route)
                                                       (97.8% logic, 2.2% route)

  Minimum Clock Path at Slow Process Corner: hi_in<0> to host/delays[11].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.344   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.541   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.179   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.070   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -6.472   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.064   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.197   host/clkout1_buf
                                                       host/clkout1_buf
    ILOGIC_X7Y0.CLK0     net (fanout=557)      1.984   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.907ns (-4.752ns logic, 6.659ns route)

--------------------------------------------------------------------------------

Hold Paths: TIMEGRP "okHostINOUT_grp" OFFSET = IN 9.83 ns VALID 9.83 ns BEFORE COMP
        "hi_in<0>" "RISING";
--------------------------------------------------------------------------------

Paths for end point host/delays[8].fdrein0 (ILOGIC_X8Y3.DDLY), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.470ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_inout<8> (PAD)
  Destination:          host/delays[8].fdrein0 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          0.000ns
  Data Path Delay:      2.175ns (Levels of Logic = 3)
  Clock Path Delay:     1.430ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_inout<8> to host/delays[8].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y7.I                 Tiopi                 0.763   hi_inout<8>
                                                       hi_inout<8>
                                                       host/delays[8].iobf0/IBUF
                                                       ProtoComp208.IMUX.8
    IODELAY_X8Y3.IDATAIN net (fanout=1)        0.093   host/iobf0_hi_datain<8>
    IODELAY_X8Y3.DATAOUT Tioddo_IDATAIN        1.178   host/delays[8].iodelay_inst
                                                       host/delays[8].iodelay_inst
    ILOGIC_X8Y3.DDLY     net (fanout=1)        0.005   host/iodly0_datain<8>
    ILOGIC_X8Y3.CLK0     Tiockdd     (-Th)    -0.136   host/hi_datain<8>
                                                       ProtoComp286.D2OFFBYP_SRC.8
                                                       host/delays[8].fdrein0
    -------------------------------------------------  ---------------------------
    Total                                      2.175ns (2.077ns logic, 0.098ns route)
                                                       (95.5% logic, 4.5% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/delays[8].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    ILOGIC_X8Y3.CLK0     net (fanout=557)      1.009   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.430ns (-1.826ns logic, 3.256ns route)

--------------------------------------------------------------------------------

Paths for end point host/delays[2].fdrein0 (ILOGIC_X14Y3.DDLY), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.490ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_inout<2> (PAD)
  Destination:          host/delays[2].fdrein0 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          0.000ns
  Data Path Delay:      2.175ns (Levels of Logic = 3)
  Clock Path Delay:     1.410ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_inout<2> to host/delays[2].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y13.I                Tiopi                 0.763   hi_inout<2>
                                                       hi_inout<2>
                                                       host/delays[2].iobf0/IBUF
                                                       ProtoComp208.IMUX.2
    IODELAY_X14Y3.IDATAINnet (fanout=1)        0.093   host/iobf0_hi_datain<2>
    IODELAY_X14Y3.DATAOUTTioddo_IDATAIN        1.178   host/delays[2].iodelay_inst
                                                       host/delays[2].iodelay_inst
    ILOGIC_X14Y3.DDLY    net (fanout=1)        0.005   host/iodly0_datain<2>
    ILOGIC_X14Y3.CLK0    Tiockdd     (-Th)    -0.136   host/hi_datain<2>
                                                       ProtoComp286.D2OFFBYP_SRC.2
                                                       host/delays[2].fdrein0
    -------------------------------------------------  ---------------------------
    Total                                      2.175ns (2.077ns logic, 0.098ns route)
                                                       (95.5% logic, 4.5% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/delays[2].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    ILOGIC_X14Y3.CLK0    net (fanout=557)      0.989   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.410ns (-1.826ns logic, 3.236ns route)

--------------------------------------------------------------------------------

Paths for end point host/delays[3].fdrein0 (ILOGIC_X20Y2.DDLY), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.490ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hi_inout<3> (PAD)
  Destination:          host/delays[3].fdrein0 (FF)
  Destination Clock:    ok1<24> rising at 0.000ns
  Requirement:          0.000ns
  Data Path Delay:      2.173ns (Levels of Logic = 3)
  Clock Path Delay:     1.408ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: hi_inout<3> to host/delays[3].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AB18.I               Tiopi                 0.763   hi_inout<3>
                                                       hi_inout<3>
                                                       host/delays[3].iobf0/IBUF
                                                       ProtoComp208.IMUX.3
    IODELAY_X20Y2.IDATAINnet (fanout=1)        0.091   host/iobf0_hi_datain<3>
    IODELAY_X20Y2.DATAOUTTioddo_IDATAIN        1.178   host/delays[3].iodelay_inst
                                                       host/delays[3].iodelay_inst
    ILOGIC_X20Y2.DDLY    net (fanout=1)        0.005   host/iodly0_datain<3>
    ILOGIC_X20Y2.CLK0    Tiockdd     (-Th)    -0.136   host/hi_datain<3>
                                                       ProtoComp286.D2OFFBYP_SRC.3
                                                       host/delays[3].fdrein0
    -------------------------------------------------  ---------------------------
    Total                                      2.173ns (2.077ns logic, 0.096ns route)
                                                       (95.6% logic, 4.4% route)

  Maximum Clock Path at Fast Process Corner: hi_in<0> to host/delays[3].fdrein0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.887   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.389   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.130   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.421   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.906   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.437   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.063   host/clkout1_buf
                                                       host/clkout1_buf
    ILOGIC_X20Y2.CLK0    net (fanout=557)      0.987   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.408ns (-1.826ns logic, 3.234ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "okHostINOUT_grp" OFFSET = OUT 11.63 ns AFTER COMP 
"hi_in<0>"         "RISING";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 32 paths analyzed, 16 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   6.779ns.
--------------------------------------------------------------------------------

Paths for end point hi_inout<8> (Y7.PAD), 2 paths
--------------------------------------------------------------------------------
Slack (slowest paths):  4.851ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               host/delays[8].fdreout0 (FF)
  Destination:          hi_inout<8> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Requirement:          11.630ns
  Data Path Delay:      4.240ns (Levels of Logic = 1)
  Clock Path Delay:     2.264ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: hi_in<0> to host/delays[8].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.557   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.933   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.232   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -7.467   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.207   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X8Y3.CLK0     net (fanout=557)      2.403   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      2.264ns (-5.511ns logic, 7.775ns route)

  Maximum Data Path at Slow Process Corner: host/delays[8].fdreout0 to hi_inout<8>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X8Y3.OQ       Tockq                 1.080   host/fdreout0_hi_dataout<8>
                                                       host/delays[8].fdreout0
    Y7.O                 net (fanout=1)        0.438   host/fdreout0_hi_dataout<8>
    Y7.PAD               Tioop                 2.722   hi_inout<8>
                                                       host/delays[8].iobf0/OBUFT
                                                       hi_inout<8>
    -------------------------------------------------  ---------------------------
    Total                                      4.240ns (3.802ns logic, 0.438ns route)
                                                       (89.7% logic, 10.3% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.232ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               host/delays[8].fdreout1 (FF)
  Destination:          hi_inout<8> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Requirement:          11.630ns
  Data Path Delay:      3.859ns (Levels of Logic = 1)
  Clock Path Delay:     2.264ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: hi_in<0> to host/delays[8].fdreout1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.557   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.933   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.232   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -7.467   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.207   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X8Y3.CLK0     net (fanout=557)      2.403   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      2.264ns (-5.511ns logic, 7.775ns route)

  Maximum Data Path at Slow Process Corner: host/delays[8].fdreout1 to hi_inout<8>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X8Y3.TQ       Tockq                 0.699   host/fdreout0_hi_dataout<8>
                                                       host/delays[8].fdreout1
    Y7.T                 net (fanout=1)        0.438   host/fdreout1_hi_drive<8>
    Y7.PAD               Tiotp                 2.722   hi_inout<8>
                                                       host/delays[8].iobf0/OBUFT
                                                       hi_inout<8>
    -------------------------------------------------  ---------------------------
    Total                                      3.859ns (3.421ns logic, 0.438ns route)
                                                       (88.6% logic, 11.4% route)

--------------------------------------------------------------------------------

Paths for end point hi_inout<2> (Y13.PAD), 2 paths
--------------------------------------------------------------------------------
Slack (slowest paths):  4.872ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               host/delays[2].fdreout0 (FF)
  Destination:          hi_inout<2> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Requirement:          11.630ns
  Data Path Delay:      4.240ns (Levels of Logic = 1)
  Clock Path Delay:     2.243ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: hi_in<0> to host/delays[2].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.557   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.933   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.232   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -7.467   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.207   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X14Y3.CLK0    net (fanout=557)      2.382   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      2.243ns (-5.511ns logic, 7.754ns route)

  Maximum Data Path at Slow Process Corner: host/delays[2].fdreout0 to hi_inout<2>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X14Y3.OQ      Tockq                 1.080   host/fdreout0_hi_dataout<2>
                                                       host/delays[2].fdreout0
    Y13.O                net (fanout=1)        0.438   host/fdreout0_hi_dataout<2>
    Y13.PAD              Tioop                 2.722   hi_inout<2>
                                                       host/delays[2].iobf0/OBUFT
                                                       hi_inout<2>
    -------------------------------------------------  ---------------------------
    Total                                      4.240ns (3.802ns logic, 0.438ns route)
                                                       (89.7% logic, 10.3% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.253ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               host/delays[2].fdreout1 (FF)
  Destination:          hi_inout<2> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Requirement:          11.630ns
  Data Path Delay:      3.859ns (Levels of Logic = 1)
  Clock Path Delay:     2.243ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: hi_in<0> to host/delays[2].fdreout1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.557   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.933   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.232   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -7.467   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.207   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X14Y3.CLK0    net (fanout=557)      2.382   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      2.243ns (-5.511ns logic, 7.754ns route)

  Maximum Data Path at Slow Process Corner: host/delays[2].fdreout1 to hi_inout<2>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X14Y3.TQ      Tockq                 0.699   host/fdreout0_hi_dataout<2>
                                                       host/delays[2].fdreout1
    Y13.T                net (fanout=1)        0.438   host/fdreout1_hi_drive<2>
    Y13.PAD              Tiotp                 2.722   hi_inout<2>
                                                       host/delays[2].iobf0/OBUFT
                                                       hi_inout<2>
    -------------------------------------------------  ---------------------------
    Total                                      3.859ns (3.421ns logic, 0.438ns route)
                                                       (88.6% logic, 11.4% route)

--------------------------------------------------------------------------------

Paths for end point hi_inout<3> (AB18.PAD), 2 paths
--------------------------------------------------------------------------------
Slack (slowest paths):  4.873ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               host/delays[3].fdreout0 (FF)
  Destination:          hi_inout<3> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Requirement:          11.630ns
  Data Path Delay:      4.240ns (Levels of Logic = 1)
  Clock Path Delay:     2.242ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: hi_in<0> to host/delays[3].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.557   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.933   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.232   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -7.467   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.207   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X20Y2.CLK0    net (fanout=557)      2.381   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      2.242ns (-5.511ns logic, 7.753ns route)

  Maximum Data Path at Slow Process Corner: host/delays[3].fdreout0 to hi_inout<3>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X20Y2.OQ      Tockq                 1.080   host/fdreout0_hi_dataout<3>
                                                       host/delays[3].fdreout0
    AB18.O               net (fanout=1)        0.438   host/fdreout0_hi_dataout<3>
    AB18.PAD             Tioop                 2.722   hi_inout<3>
                                                       host/delays[3].iobf0/OBUFT
                                                       hi_inout<3>
    -------------------------------------------------  ---------------------------
    Total                                      4.240ns (3.802ns logic, 0.438ns route)
                                                       (89.7% logic, 10.3% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.254ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               host/delays[3].fdreout1 (FF)
  Destination:          hi_inout<3> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Requirement:          11.630ns
  Data Path Delay:      3.859ns (Levels of Logic = 1)
  Clock Path Delay:     2.242ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: hi_in<0> to host/delays[3].fdreout1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 1.557   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        2.933   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.232   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -7.467   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        1.207   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X20Y2.CLK0    net (fanout=557)      2.381   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      2.242ns (-5.511ns logic, 7.753ns route)

  Maximum Data Path at Slow Process Corner: host/delays[3].fdreout1 to hi_inout<3>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X20Y2.TQ      Tockq                 0.699   host/fdreout0_hi_dataout<3>
                                                       host/delays[3].fdreout1
    AB18.T               net (fanout=1)        0.438   host/fdreout1_hi_drive<3>
    AB18.PAD             Tiotp                 2.722   hi_inout<3>
                                                       host/delays[3].iobf0/OBUFT
                                                       hi_inout<3>
    -------------------------------------------------  ---------------------------
    Total                                      3.859ns (3.421ns logic, 0.438ns route)
                                                       (88.6% logic, 11.4% route)

--------------------------------------------------------------------------------

Fastest Paths: TIMEGRP "okHostINOUT_grp" OFFSET = OUT 11.63 ns AFTER COMP "hi_in<0>"
        "RISING";
--------------------------------------------------------------------------------

Paths for end point hi_inout<15> (AA20.PAD), 2 paths
--------------------------------------------------------------------------------
Delay (fastest paths):  3.052ns (clock arrival + clock path + data path - uncertainty)
  Source:               host/delays[15].fdreout0 (FF)
  Destination:          hi_inout<15> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Data Path Delay:      2.000ns (Levels of Logic = 1)
  Clock Path Delay:     1.327ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: hi_in<0> to host/delays[15].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.763   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.327   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.372   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.643   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.394   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X25Y1.CLK0    net (fanout=557)      0.933   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.327ns (-1.699ns logic, 3.026ns route)

  Minimum Data Path at Fast Process Corner: host/delays[15].fdreout0 to hi_inout<15>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X25Y1.OQ      Tockq                 0.336   host/fdreout0_hi_dataout<15>
                                                       host/delays[15].fdreout0
    AA20.O               net (fanout=1)        0.268   host/fdreout0_hi_dataout<15>
    AA20.PAD             Tioop                 1.396   hi_inout<15>
                                                       host/delays[15].iobf0/OBUFT
                                                       hi_inout<15>
    -------------------------------------------------  ---------------------------
    Total                                      2.000ns (1.732ns logic, 0.268ns route)
                                                       (86.6% logic, 13.4% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  2.944ns (clock arrival + clock path + data path - uncertainty)
  Source:               host/delays[15].fdreout1 (FF)
  Destination:          hi_inout<15> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Data Path Delay:      1.892ns (Levels of Logic = 1)
  Clock Path Delay:     1.327ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: hi_in<0> to host/delays[15].fdreout1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.763   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.327   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.372   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.643   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.394   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X25Y1.CLK0    net (fanout=557)      0.933   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.327ns (-1.699ns logic, 3.026ns route)

  Minimum Data Path at Fast Process Corner: host/delays[15].fdreout1 to hi_inout<15>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X25Y1.TQ      Tockq                 0.228   host/fdreout0_hi_dataout<15>
                                                       host/delays[15].fdreout1
    AA20.T               net (fanout=1)        0.268   host/fdreout1_hi_drive<15>
    AA20.PAD             Tiotp                 1.396   hi_inout<15>
                                                       host/delays[15].iobf0/OBUFT
                                                       hi_inout<15>
    -------------------------------------------------  ---------------------------
    Total                                      1.892ns (1.624ns logic, 0.268ns route)
                                                       (85.8% logic, 14.2% route)

--------------------------------------------------------------------------------

Paths for end point hi_inout<5> (V15.PAD), 2 paths
--------------------------------------------------------------------------------
Delay (fastest paths):  3.053ns (clock arrival + clock path + data path - uncertainty)
  Source:               host/delays[5].fdreout0 (FF)
  Destination:          hi_inout<5> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Data Path Delay:      2.000ns (Levels of Logic = 1)
  Clock Path Delay:     1.328ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: hi_in<0> to host/delays[5].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.763   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.327   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.372   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.643   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.394   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X20Y0.CLK0    net (fanout=557)      0.934   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.328ns (-1.699ns logic, 3.027ns route)

  Minimum Data Path at Fast Process Corner: host/delays[5].fdreout0 to hi_inout<5>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X20Y0.OQ      Tockq                 0.336   host/fdreout0_hi_dataout<5>
                                                       host/delays[5].fdreout0
    V15.O                net (fanout=1)        0.268   host/fdreout0_hi_dataout<5>
    V15.PAD              Tioop                 1.396   hi_inout<5>
                                                       host/delays[5].iobf0/OBUFT
                                                       hi_inout<5>
    -------------------------------------------------  ---------------------------
    Total                                      2.000ns (1.732ns logic, 0.268ns route)
                                                       (86.6% logic, 13.4% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  2.945ns (clock arrival + clock path + data path - uncertainty)
  Source:               host/delays[5].fdreout1 (FF)
  Destination:          hi_inout<5> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Data Path Delay:      1.892ns (Levels of Logic = 1)
  Clock Path Delay:     1.328ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: hi_in<0> to host/delays[5].fdreout1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.763   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.327   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.372   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.643   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.394   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X20Y0.CLK0    net (fanout=557)      0.934   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.328ns (-1.699ns logic, 3.027ns route)

  Minimum Data Path at Fast Process Corner: host/delays[5].fdreout1 to hi_inout<5>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X20Y0.TQ      Tockq                 0.228   host/fdreout0_hi_dataout<5>
                                                       host/delays[5].fdreout1
    V15.T                net (fanout=1)        0.268   host/fdreout1_hi_drive<5>
    V15.PAD              Tiotp                 1.396   hi_inout<5>
                                                       host/delays[5].iobf0/OBUFT
                                                       hi_inout<5>
    -------------------------------------------------  ---------------------------
    Total                                      1.892ns (1.624ns logic, 0.268ns route)
                                                       (85.8% logic, 14.2% route)

--------------------------------------------------------------------------------

Paths for end point hi_inout<11> (AB6.PAD), 2 paths
--------------------------------------------------------------------------------
Delay (fastest paths):  3.074ns (clock arrival + clock path + data path - uncertainty)
  Source:               host/delays[11].fdreout0 (FF)
  Destination:          hi_inout<11> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Data Path Delay:      2.000ns (Levels of Logic = 1)
  Clock Path Delay:     1.349ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: hi_in<0> to host/delays[11].fdreout0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.763   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.327   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.372   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.643   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.394   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X7Y0.CLK0     net (fanout=557)      0.955   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.349ns (-1.699ns logic, 3.048ns route)

  Minimum Data Path at Fast Process Corner: host/delays[11].fdreout0 to hi_inout<11>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X7Y0.OQ       Tockq                 0.336   host/fdreout0_hi_dataout<11>
                                                       host/delays[11].fdreout0
    AB6.O                net (fanout=1)        0.268   host/fdreout0_hi_dataout<11>
    AB6.PAD              Tioop                 1.396   hi_inout<11>
                                                       host/delays[11].iobf0/OBUFT
                                                       hi_inout<11>
    -------------------------------------------------  ---------------------------
    Total                                      2.000ns (1.732ns logic, 0.268ns route)
                                                       (86.6% logic, 13.4% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  2.966ns (clock arrival + clock path + data path - uncertainty)
  Source:               host/delays[11].fdreout1 (FF)
  Destination:          hi_inout<11> (PAD)
  Source Clock:         ok1<24> rising at 0.000ns
  Data Path Delay:      1.892ns (Levels of Logic = 1)
  Clock Path Delay:     1.349ns (Levels of Logic = 4)
  Clock Uncertainty:    0.275ns

  Clock Uncertainty:          0.275ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.200ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: hi_in<0> to host/delays[11].fdreout1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y12.I                Tiopi                 0.763   hi_in<0>
                                                       hi_in<0>
                                                       hi_in_0_IBUFG
                                                       ProtoComp215.IMUX.11
    BUFIO2_X3Y1.I        net (fanout=4)        1.327   hi_in_0_IBUFG
    BUFIO2_X3Y1.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.372   host/hi_dcm_ML_NEW_DIVCLK
    DCM_X0Y1.CLK0        Tdmcko_CLK           -2.643   host/hi_dcm
                                                       host/hi_dcm
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.394   host/dcm_clk0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   host/clkout1_buf
                                                       host/clkout1_buf
    OLOGIC_X7Y0.CLK0     net (fanout=557)      0.955   ok1<24>
    -------------------------------------------------  ---------------------------
    Total                                      1.349ns (-1.699ns logic, 3.048ns route)

  Minimum Data Path at Fast Process Corner: host/delays[11].fdreout1 to hi_inout<11>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X7Y0.TQ       Tockq                 0.228   host/fdreout0_hi_dataout<11>
                                                       host/delays[11].fdreout1
    AB6.T                net (fanout=1)        0.268   host/fdreout1_hi_drive<11>
    AB6.PAD              Tiotp                 1.396   hi_inout<11>
                                                       host/delays[11].iobf0/OBUFT
                                                       hi_inout<11>
    -------------------------------------------------  ---------------------------
    Total                                      1.892ns (1.624ns logic, 0.268ns route)
                                                       (85.8% logic, 14.2% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_okHostClk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_okHostClk                   |     20.830ns|     16.000ns|     16.392ns|            0|            0|            3|        42956|
| TS_host_dcm_clk0              |     20.830ns|     16.392ns|          N/A|            0|            0|        42956|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_SYS_CLK3
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK3                    |     10.000ns|    410.251ns|   5483.500ns|           40|          126|        25369|     10923472|
| TS_SDRAM_FIFO_inst_memc3_infra|     12.800ns|      9.919ns|          N/A|            0|            0|        13623|            0|
| structure_inst_mcb_drp_clk_buf|             |             |             |             |             |             |             |
| g_in                          |             |             |             |             |             |             |             |
| TS_SDRAM_FIFO_inst_memc3_infra|      1.600ns|      1.599ns|          N/A|            0|            0|            0|            0|
| structure_inst_clk_2x_180     |             |             |             |             |             |             |             |
| TS_SDRAM_FIFO_inst_memc3_infra|      1.600ns|      1.599ns|          N/A|            0|            0|            0|            0|
| structure_inst_clk_2x_0       |             |             |             |             |             |             |             |
| TS_SDRAM_FIFO_inst_memc3_infra|      6.400ns|   3509.440ns|          N/A|            9|            0|         4315|            0|
| structure_inst_clk0_bufg_in   |             |             |             |             |             |             |             |
| TS_variable_freq_clk_generator|     11.905ns|     16.321ns|          N/A|          117|            0|     10905534|            0|
| _inst_clkout_i                |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

3 constraints not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock hi_in<0>
------------+------------+------------+------------+------------+------------------+--------+
            |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
------------+------------+------------+------------+------------+------------------+--------+
hi_in<1>    |    7.262(R)|      SLOW  |   -2.167(R)|      FAST  |ok1<24>           |   0.000|
hi_in<2>    |    6.044(R)|      SLOW  |   -1.319(R)|      FAST  |ok1<24>           |   0.000|
hi_in<3>    |    5.330(R)|      SLOW  |   -1.197(R)|      FAST  |ok1<24>           |   0.000|
hi_in<4>    |   10.257(R)|      SLOW  |   -1.329(R)|      FAST  |ok1<24>           |   0.000|
hi_in<5>    |   10.493(R)|      SLOW  |   -1.502(R)|      FAST  |ok1<24>           |   0.000|
hi_in<6>    |   10.653(R)|      SLOW  |   -1.661(R)|      FAST  |ok1<24>           |   0.000|
hi_in<7>    |   11.590(R)|      SLOW  |   -1.299(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<0> |    5.697(R)|      SLOW  |   -0.526(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<1> |    5.697(R)|      SLOW  |   -0.526(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<2> |    5.661(R)|      SLOW  |   -0.490(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<3> |    5.661(R)|      SLOW  |   -0.490(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<4> |    5.663(R)|      SLOW  |   -0.492(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<5> |    5.720(R)|      SLOW  |   -0.549(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<6> |    5.698(R)|      SLOW  |   -0.527(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<7> |    5.698(R)|      SLOW  |   -0.527(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<8> |    5.641(R)|      SLOW  |   -0.470(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<9> |    5.698(R)|      SLOW  |   -0.527(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<10>|    5.698(R)|      SLOW  |   -0.527(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<11>|    5.699(R)|      SLOW  |   -0.528(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<12>|    5.699(R)|      SLOW  |   -0.528(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<13>|    5.661(R)|      SLOW  |   -0.490(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<14>|    5.663(R)|      SLOW  |   -0.492(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<15>|    5.720(R)|      SLOW  |   -0.549(R)|      FAST  |ok1<24>           |   0.000|
------------+------------+------------+------------+------------+------------------+--------+

Clock hi_in<0> to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
------------+-----------------+------------+-----------------+------------+------------------+--------+
hi_inout<0> |         6.730(R)|      SLOW  |         2.968(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<1> |         6.730(R)|      SLOW  |         2.968(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<2> |         6.758(R)|      SLOW  |         2.996(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<3> |         6.757(R)|      SLOW  |         2.995(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<4> |         6.757(R)|      SLOW  |         2.995(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<5> |         6.707(R)|      SLOW  |         2.945(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<6> |         6.729(R)|      SLOW  |         2.967(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<7> |         6.729(R)|      SLOW  |         2.967(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<8> |         6.779(R)|      SLOW  |         3.017(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<9> |         6.729(R)|      SLOW  |         2.967(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<10>|         6.729(R)|      SLOW  |         2.967(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<11>|         6.728(R)|      SLOW  |         2.966(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<12>|         6.728(R)|      SLOW  |         2.966(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<13>|         6.756(R)|      SLOW  |         2.994(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<14>|         6.756(R)|      SLOW  |         2.994(R)|      FAST  |ok1<24>           |   0.000|
hi_inout<15>|         6.706(R)|      SLOW  |         2.944(R)|      FAST  |ok1<24>           |   0.000|
hi_out<0>   |         8.797(R)|      SLOW  |         4.326(R)|      FAST  |ok1<24>           |   0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock clk1_in
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk1_in        |   19.569|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock hi_in<0>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
hi_in<0>       |   16.392|         |         |         |
---------------+---------+---------+---------+---------+

COMP "hi_in<7>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"         "RISING";
Worst Case Data Window 10.291; Ideal Clock Offset To Actual Clock 3.530; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
hi_in<7>          |   11.590(R)|      SLOW  |   -1.299(R)|      FAST  |    1.740|    8.799|       -3.530|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      11.590|         -  |      -1.299|         -  |    1.740|    8.799|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

COMP "hi_in<6>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"         "RISING";
Worst Case Data Window 8.992; Ideal Clock Offset To Actual Clock 3.242; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
hi_in<6>          |   10.653(R)|      SLOW  |   -1.661(R)|      FAST  |    2.677|    9.161|       -3.242|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      10.653|         -  |      -1.661|         -  |    2.677|    9.161|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

COMP "hi_in<5>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"         "RISING";
Worst Case Data Window 8.991; Ideal Clock Offset To Actual Clock 3.083; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
hi_in<5>          |   10.493(R)|      SLOW  |   -1.502(R)|      FAST  |    2.837|    9.002|       -3.083|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      10.493|         -  |      -1.502|         -  |    2.837|    9.002|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

COMP "hi_in<4>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"         "RISING";
Worst Case Data Window 8.928; Ideal Clock Offset To Actual Clock 2.878; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
hi_in<4>          |   10.257(R)|      SLOW  |   -1.329(R)|      FAST  |    3.073|    8.829|       -2.878|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      10.257|         -  |      -1.329|         -  |    3.073|    8.829|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

COMP "hi_in<3>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"         "RISING";
Worst Case Data Window 4.133; Ideal Clock Offset To Actual Clock -0.452; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
hi_in<3>          |    5.330(R)|      SLOW  |   -1.197(R)|      FAST  |    8.800|    7.897|        0.452|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       5.330|         -  |      -1.197|         -  |    8.800|    7.897|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

COMP "hi_in<2>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"         "RISING";
Worst Case Data Window 4.725; Ideal Clock Offset To Actual Clock -0.034; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
hi_in<2>          |    6.044(R)|      SLOW  |   -1.319(R)|      FAST  |    8.086|    8.019|        0.034|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       6.044|         -  |      -1.319|         -  |    8.086|    8.019|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

COMP "hi_in<1>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE COMP "hi_in<0>"         "RISING";
Worst Case Data Window 5.095; Ideal Clock Offset To Actual Clock 1.000; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
hi_in<1>          |    7.262(R)|      SLOW  |   -2.167(R)|      FAST  |    6.868|    8.867|       -1.000|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       7.262|         -  |      -2.167|         -  |    6.868|    8.867|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "okHostINOUT_grp" OFFSET = IN 9.83 ns VALID 9.83 ns BEFORE COMP         "hi_in<0>" "RISING";
Worst Case Data Window 5.250; Ideal Clock Offset To Actual Clock -1.820; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
hi_inout<0>       |    5.697(R)|      SLOW  |   -0.526(R)|      FAST  |    4.133|    0.526|        1.804|
hi_inout<1>       |    5.697(R)|      SLOW  |   -0.526(R)|      FAST  |    4.133|    0.526|        1.804|
hi_inout<2>       |    5.661(R)|      SLOW  |   -0.490(R)|      FAST  |    4.169|    0.490|        1.839|
hi_inout<3>       |    5.661(R)|      SLOW  |   -0.490(R)|      FAST  |    4.169|    0.490|        1.839|
hi_inout<4>       |    5.663(R)|      SLOW  |   -0.492(R)|      FAST  |    4.167|    0.492|        1.838|
hi_inout<5>       |    5.720(R)|      SLOW  |   -0.549(R)|      FAST  |    4.110|    0.549|        1.781|
hi_inout<6>       |    5.698(R)|      SLOW  |   -0.527(R)|      FAST  |    4.132|    0.527|        1.802|
hi_inout<7>       |    5.698(R)|      SLOW  |   -0.527(R)|      FAST  |    4.132|    0.527|        1.802|
hi_inout<8>       |    5.641(R)|      SLOW  |   -0.470(R)|      FAST  |    4.189|    0.470|        1.860|
hi_inout<9>       |    5.698(R)|      SLOW  |   -0.527(R)|      FAST  |    4.132|    0.527|        1.802|
hi_inout<10>      |    5.698(R)|      SLOW  |   -0.527(R)|      FAST  |    4.132|    0.527|        1.802|
hi_inout<11>      |    5.699(R)|      SLOW  |   -0.528(R)|      FAST  |    4.131|    0.528|        1.802|
hi_inout<12>      |    5.699(R)|      SLOW  |   -0.528(R)|      FAST  |    4.131|    0.528|        1.802|
hi_inout<13>      |    5.661(R)|      SLOW  |   -0.490(R)|      FAST  |    4.169|    0.490|        1.839|
hi_inout<14>      |    5.663(R)|      SLOW  |   -0.492(R)|      FAST  |    4.167|    0.492|        1.838|
hi_inout<15>      |    5.720(R)|      SLOW  |   -0.549(R)|      FAST  |    4.110|    0.549|        1.781|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       5.720|         -  |      -0.470|         -  |    4.110|    0.470|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

COMP "hi_out<0>" OFFSET = OUT 11.93 ns AFTER COMP "hi_in<0>" "RISING";
Bus Skew: 0.000 ns; 
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
                                               |Max (slowest)|  Process   |Min (fastest)|  Process   |              |
PAD                                            | Delay (ns)  |   Corner   | Delay (ns)  |   Corner   |Edge Skew (ns)|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
hi_out<0>                                      |        8.797|      SLOW  |        4.326|      FAST  |         0.000|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+

TIMEGRP "okHostINOUT_grp" OFFSET = OUT 11.63 ns AFTER COMP "hi_in<0>"         "RISING";
Bus Skew: 0.073 ns; 
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
                                               |Max (slowest)|  Process   |Min (fastest)|  Process   |              |
PAD                                            | Delay (ns)  |   Corner   | Delay (ns)  |   Corner   |Edge Skew (ns)|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
hi_inout<0>                                    |        6.730|      SLOW  |        2.968|      FAST  |         0.024|
hi_inout<1>                                    |        6.730|      SLOW  |        2.968|      FAST  |         0.024|
hi_inout<2>                                    |        6.758|      SLOW  |        2.996|      FAST  |         0.052|
hi_inout<3>                                    |        6.757|      SLOW  |        2.995|      FAST  |         0.051|
hi_inout<4>                                    |        6.757|      SLOW  |        2.995|      FAST  |         0.051|
hi_inout<5>                                    |        6.707|      SLOW  |        2.945|      FAST  |         0.001|
hi_inout<6>                                    |        6.729|      SLOW  |        2.967|      FAST  |         0.023|
hi_inout<7>                                    |        6.729|      SLOW  |        2.967|      FAST  |         0.023|
hi_inout<8>                                    |        6.779|      SLOW  |        3.017|      FAST  |         0.073|
hi_inout<9>                                    |        6.729|      SLOW  |        2.967|      FAST  |         0.023|
hi_inout<10>                                   |        6.729|      SLOW  |        2.967|      FAST  |         0.023|
hi_inout<11>                                   |        6.728|      SLOW  |        2.966|      FAST  |         0.022|
hi_inout<12>                                   |        6.728|      SLOW  |        2.966|      FAST  |         0.022|
hi_inout<13>                                   |        6.756|      SLOW  |        2.994|      FAST  |         0.050|
hi_inout<14>                                   |        6.756|      SLOW  |        2.994|      FAST  |         0.050|
hi_inout<15>                                   |        6.706|      SLOW  |        2.944|      FAST  |         0.000|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+


Timing summary:
---------------

Timing errors: 166  Score: 728179  (Setup/Max: 728179, Hold: 0)

Constraints cover 10992859 paths, 0 nets, and 38144 connections

Design statistics:
   Minimum period: 3509.440ns{1}   (Maximum frequency:   0.285MHz)
   Minimum input required time before clock:  11.590ns
   Minimum output required time after clock:   8.797ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Tue Dec 16 02:33:31 2014 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 431 MB