PueoSURF constructor with TURFIO access method should raise exception if its RXCLK is not enabled or no SURF present

[barawn]

Trying to access a SURF on a TURFIO that does not have the corresponding RXCLK enabled will obviously fail (since the other side of the RACKbus is not clocked), and will just return timeouts (0xFFFFFFFF). But it isn't clear that this is what's going on:

>>> tio.status()
FPGA: TFIO v0.2.13 5/8/25 0x2ad40e4601a854
Crate Power Enable: 1
RACK 3.3V Enable: 1
Crate I2C Ready: 1
Local HSKBUS Override: 0
HSKBUS Crate Bridge Enable: 0
Housekeeping RX Byte Count: 0
SYSCLK: 124993536
GTPCLK: 125009920
RXCLK: 125009920
HSRXCLK: 250003456
CLK200: 199999488
>>> surf = PueoSURF((tio,0), 'TURFIO')
>>> surf.status()
FPGA: ÿÿÿÿ
ACLK: 4294967295
GTPCLK: 4294967295
RXCLK: 4294967295
CLK300: 4294967295
IFCLK: 4294967295
RACKCLK: 4294967295
>>> tio.enable_rxclk(True)
>>> surf = PueoSURF((tio,0), 'TURFIO')
>>> surf.status()
FPGA: SURF v0.1.1 5/7/25 boardrev B 0x142011848293c15
ACLK: 374996992
GTPCLK: 100024320
RXCLK: 124993536
CLK300: 300007424
IFCLK: 124993536
RACKCLK: 125009920

Instead we should check the enable_rxclk bits just like we check the Aurora lane and test the bridge with the TURFIO.