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.vitis_hls_log_all.xml
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.vitis_hls_log_all.xml
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<?xml version="1.0" encoding="UTF-8"?>
<vivadoHLSLog:LogRoot xmlns:vivadoHLSLog="www.xilinx.com/vivadoHLSLog">
<errorLogs>
<logs>
<synLog/>
<simLog/>
<mgLog/>
<packageLog/>
<csimLog/>
</logs>
</errorLogs>
<warningLogs>
<logs>
<synLog>
<logs message="WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:19.771+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_BREADY' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.911+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWUSER' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.880+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWREGION' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.848+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWQOS' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.833+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWPROT' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.802+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWCACHE' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.770+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWLOCK' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.755+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWBURST' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.723+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWSIZE' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.708+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWLEN' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.677+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWID' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.645+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWADDR' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.630+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataWrite/m_axi_gmem_AWVALID' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.598+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARUSER' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.255+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARREGION' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.223+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARQOS' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.208+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARPROT' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.177+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARCACHE' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.145+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARLOCK' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.130+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARBURST' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.114+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARSIZE' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.083+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARLEN' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.067+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARID' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.052+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARADDR' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.020+0100" type="Warning"/>
<logs message="WARNING: [RTGEN 206-101] Setting dangling out port 'runBench_Pipeline_dataRead/m_axi_gmem_ARVALID' to 0." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:18.005+0100" type="Warning"/>
<logs message="WARNING: [HLS 200-1450] Process runBench has both a successor and writes an output to its caller (see the GUI dataflow viewer). This may lead to lower throughput. Consider copying this output via a successor process.
Resolution: For help on HLS 200-1450 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.1;t=hls+guidance;d=200-1450.html" projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:16.333+0100" type="Warning"/>
<logs message="WARNING: [HLS 200-786] Detected dataflow-on-top in function 'ddrBenchmark' (MemBench/src/ddrbenchmark.cpp:44:1) with default interface mode 'ap_ctrl_hs'. Overlapped execution of successive kernel calls will not happen unless interface mode 'ap_ctrl_chain' is used (or 'ap_ctrl_none' for a purely data-driven design).
Resolution: For help on HLS 200-786 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.1;t=hls+guidance;d=200-786.html" projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:15.989+0100" type="Warning"/>
<logs message="WARNING: [HLS 200-805] An internal stream 'counterCmd' (MemBench/src/ddrbenchmark.cpp:58) with default size can result in deadlock. Please consider resizing the stream using the directive 'set_directive_stream' or the 'HLS stream' pragma." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:15.973+0100" type="Warning"/>
</synLog>
<simLog>
<logs message="WARNING: [HLS 200-616] This design uses AXI slave interface in dataflow mode, which can result in simulation dead-lock and/or mismatching results (due to AXI slave FIFO sizing)." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:50.555+0100" type="Warning"/>
<logs message="WARNING: [COSIM 212-384] This design has internal non-blocking FIFO/Stream accesses, which may result in mismatches or simulation hanging." projectName="MemBench" solutionName="ddrbench_sol" date="2023-03-13T14:23:35.768+0100" type="Warning"/>
</simLog>
<mgLog/>
<packageLog/>
<csimLog/>
</logs>
</warningLogs>
</vivadoHLSLog:LogRoot>