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vivado_1672.backup.jou
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vivado_1672.backup.jou
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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Fri Jul 24 14:35:00 2020
# Process ID: 1672
# Current directory: D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent5836 D:\MSc_DSE\AUTUMN_TERM\Digital Design\Lab\Group project\Copy of Mem_subsyst_ full_interg\Mem_subsyst_ full_interg\Mem_subsyst_ full_interg.xpr
# Log file: D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/vivado.log
# Journal file: D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.xpr}
update_compile_order -fileset sources_1
synth_design -rtl -name rtl_1
add_files -norecurse -scan_for_includes {{D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bits.vhd} {D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd}}
import_files -norecurse {{D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bits.vhd} {D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd}}
update_compile_order -fileset sources_1
import_files
update_files -from_files {{D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd}} -to_files {{D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd}} -filesets [get_filesets *]