Incorrect comments on v_i/ready_o port in bsg_one_fifo

[muwyse]

The comments on the v_i/ready_o ports of bsg_one_fifo (

basejump_stl/bsg_dataflow/bsg_one_fifo.v

Lines 25 to 27 in 7a05961

	, output ready_o // early
	, input [width_p-1:0] data_i // late
	, input v_i // late

) incorrectly imply that the interface is ready->valid when in reality the module implements ready&valid.

Adjusting the comments on the data_i and v_i ports to reflect this is a first step. Comments on both should be // early Renaming signals for clarity to v_i, ready_and_o would be ideal in the long term.

[dpetrisko]

basejump_stl/bsg_dataflow/bsg_one_fifo.v

Line 50 in 7a05961

// although technically it is okay to just look at v_o

Also, this comment should read v_i, not v_o

[muwyse]

Also, this comment should read v_i, not v_o

However, if we only look at v_i, the interface becomes ready->valid since new data would be captured when the producer raises v_i, regardless of the state of ready_o (i.e., existing data will be cached if the producer does not consider ready_o before raising v_i)

[dpetrisko]

https://github.com/bespoke-silicon-group/basejump_stl/blob/master/bsg_dataflow/bsg_fifo_1r1w_small.v#L25

Yep, we would need to add this parameter to change it