A utility to help read simulation waveform of RISCV SOC

[jiinlai]

The Caravel SOC verification has two parts, one is the Verilog test bench; another is riscv code. The riscv code is compiled into hex file and loaded into instruction memory. When running the simulation the riscv fetched instructions and execute them to validate the design. When we use waveform tool (gtkwave) to observe the waveform of the system operation, it is very difficult to associate the part of the waveform and the related code. Here we propose a utility "riscv-tracer". It helps us to read the waveform and understand the system operation much easier.
Attached is a preliminary specification.
riscv-tracer.pdf

[kevinjantw]

https://github.com/bol-edu/caravel-soc/tree/cpu-trace