A flexible framework for analyzing and transforming netlists <https://en.wikipedia.org/wiki/Netlist>_. Built to fill an important gap in FPGA research and reliability. Currently available as a pure Python package.
- Website and Documentation: https://byuccl.github.io/spydrnet-tmr/
Released under the BSD 3-Clause License (see :ref:LICENSE)::
Copyright (C) 2021, Brigham Young University All rights reserved.