From d49a395a2afb2e23c481c3ecff1fa80aae9d81fe Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Wed, 19 Oct 2022 10:35:34 -0700 Subject: [PATCH 1/7] Fix 4MB ublaze axi_slave_wishbone offset and range --- .../hdl_sources/microblaze_wb/microblaze_wb.tcl | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl index 229dbc977a..16f0f951fc 100644 --- a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl +++ b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl @@ -295,7 +295,7 @@ proc create_root_design { parentCell } { # Create ports set ACK_I [ create_bd_port -dir I ACK_I ] - set ADR_O [ create_bd_port -dir O -from 19 -to 0 ADR_O ] + set ADR_O [ create_bd_port -dir O -from 21 -to 0 ADR_O ] set CYC_O [ create_bd_port -dir O CYC_O ] set Clk [ create_bd_port -dir I -type clk -freq_hz 100000000 Clk ] set DAT_I [ create_bd_port -dir I -from 31 -to 0 DAT_I ] @@ -428,7 +428,7 @@ proc create_root_design { parentCell } { # Create address segments assign_bd_address -offset 0x40200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_hwicap_0/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0x44A00000 -range 0x00100000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_slave_wishbone_classic_master_0/S_AXI/reg0] -force + assign_bd_address -offset 0x44C00000 -range 0x00400000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_slave_wishbone_classic_master_0/S_AXI/reg0] -force assign_bd_address -offset 0x41A00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timebase_wdt_0/S_AXI/Reg] -force assign_bd_address -offset 0x41C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force assign_bd_address -offset 0x40600000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] -force @@ -439,7 +439,7 @@ proc create_root_design { parentCell } { # Restore current instance current_bd_instance $oldCurInst - + validate_bd_design save_bd_design } # End of create_root_design() @@ -450,7 +450,3 @@ proc create_root_design { parentCell } { ################################################################## create_root_design "" - - -common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." - From 628030975654bed3edd5aacfda7357a47cc99ac3 Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Wed, 19 Oct 2022 12:53:22 -0700 Subject: [PATCH 2/7] Add back vaidation comment, The call to vaildate design didn't work --- jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl index 16f0f951fc..e3c8f75184 100644 --- a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl +++ b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl @@ -439,7 +439,7 @@ proc create_root_design { parentCell } { # Restore current instance current_bd_instance $oldCurInst - validate_bd_design + save_bd_design } # End of create_root_design() @@ -450,3 +450,6 @@ proc create_root_design { parentCell } { ################################################################## create_root_design "" + + +common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." From 61bf720e607cc1961299881fcb577874074d5a64 Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Thu, 20 Oct 2022 12:12:17 -0700 Subject: [PATCH 3/7] Add back SPI and hardware monitoring to ublaze tcl --- .../microblaze_wb/microblaze_wb.tcl | 45 ++++++++++++++++--- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl index e3c8f75184..34bff5a12c 100644 --- a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl +++ b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl @@ -321,8 +321,24 @@ proc create_root_design { parentCell } { CONFIG.C_OPERATION {1} \ ] $axi_hwicap_0 + # Create instance: axi_quad_spi_0, and set properties + set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ] + set_property -dict [ list \ + CONFIG.C_SCK_RATIO {2} \ + CONFIG.C_SHARED_STARTUP {0} \ + CONFIG.C_SPI_MEMORY {2} \ + CONFIG.C_SPI_MODE {2} \ + CONFIG.C_TYPE_OF_AXI4_INTERFACE {0} \ + CONFIG.C_USE_STARTUP {1} \ + CONFIG.C_USE_STARTUP_INT {1} \ + CONFIG.C_XIP_MODE {0} \ + ] $axi_quad_spi_0 + # Create instance: axi_slave_wishbone_classic_master_0, and set properties set axi_slave_wishbone_classic_master_0 [ create_bd_cell -type ip -vlnv peralex.com:user:axi_slave_wishbone_classic_master:1.0 axi_slave_wishbone_classic_master_0 ] + set_property -dict [ list \ + CONFIG.C_S_AXI_ADDR_WIDTH {22} \ + ] $axi_slave_wishbone_classic_master_0 # Create instance: axi_timebase_wdt_0, and set properties set axi_timebase_wdt_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timebase_wdt:3.0 axi_timebase_wdt_0 ] @@ -381,19 +397,35 @@ proc create_root_design { parentCell } { CONFIG.C_AUX_RST_WIDTH {1} \ ] $rst_Clk_100M + # Create instance: xadc_wiz_0, and set properties + set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ] + set_property -dict [ list \ + CONFIG.CHANNEL_ENABLE_VP_VN {false} \ + CONFIG.ENABLE_RESET {false} \ + CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \ + CONFIG.INTERFACE_SELECTION {Enable_AXI} \ + CONFIG.SEQUENCER_MODE {Off} \ + CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \ + CONFIG.TIMING_MODE {Continuous} \ + CONFIG.XADC_STARUP_SELECTION {single_channel} \ + ] $xadc_wiz_0 + # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] set_property -dict [ list \ - CONFIG.NUM_PORTS {4} \ + CONFIG.NUM_PORTS {6} \ ] $xlconcat_0 # Create interface connections + connect_bd_intf_net -intf_net axi_quad_spi_0_SPI_0 [get_bd_intf_ports spi_rtl] [get_bd_intf_pins axi_quad_spi_0/SPI_0] connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports UART] [get_bd_intf_pins axi_uartlite_0/UART] connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_timebase_wdt_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_slave_wishbone_classic_master_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M05_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins microblaze_0_axi_periph/M05_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M06_AXI [get_bd_intf_pins microblaze_0_axi_periph/M06_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite] connect_bd_intf_net -intf_net microblaze_0_axi_periph_M07_AXI [get_bd_intf_pins axi_hwicap_0/S_AXI_LITE] [get_bd_intf_pins microblaze_0_axi_periph/M07_AXI] connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] @@ -405,7 +437,9 @@ proc create_root_design { parentCell } { connect_bd_net -net ACK_I_1 [get_bd_ports ACK_I] [get_bd_pins axi_slave_wishbone_classic_master_0/ACK_I] connect_bd_net -net DAT_I_1 [get_bd_ports DAT_I] [get_bd_pins axi_slave_wishbone_classic_master_0/DAT_I] connect_bd_net -net Reset_1 [get_bd_ports Reset] [get_bd_pins rst_Clk_100M/ext_reset_in] - connect_bd_net -net axi_hwicap_0_ip2intc_irpt [get_bd_pins axi_hwicap_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net axi_hwicap_0_ip2intc_irpt [get_bd_pins axi_hwicap_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In4] + connect_bd_net -net axi_quad_spi_0_eos [get_bd_pins axi_hwicap_0/eos_in] [get_bd_pins axi_quad_spi_0/eos] + connect_bd_net -net axi_quad_spi_0_ip2intc_irpt [get_bd_pins axi_quad_spi_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In2] connect_bd_net -net axi_slave_wishbone_classic_master_0_ADR_O [get_bd_ports ADR_O] [get_bd_pins axi_slave_wishbone_classic_master_0/ADR_O] connect_bd_net -net axi_slave_wishbone_classic_master_0_CYC_O [get_bd_ports CYC_O] [get_bd_pins axi_slave_wishbone_classic_master_0/CYC_O] connect_bd_net -net axi_slave_wishbone_classic_master_0_DAT_O [get_bd_ports DAT_O] [get_bd_pins axi_slave_wishbone_classic_master_0/DAT_O] @@ -417,13 +451,14 @@ proc create_root_design { parentCell } { connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins xlconcat_0/In1] connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In0] connect_bd_net -net dcm_locked_1 [get_bd_ports dcm_locked] [get_bd_pins rst_Clk_100M/dcm_locked] - connect_bd_net -net ext_intr_1 [get_bd_ports ext_intr] [get_bd_pins xlconcat_0/In3] + connect_bd_net -net ext_intr_1 [get_bd_ports ext_intr] [get_bd_pins xlconcat_0/In5] connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_Clk_100M/mb_debug_sys_rst] - connect_bd_net -net microblaze_0_Clk [get_bd_ports Clk] [get_bd_pins axi_hwicap_0/icap_clk] [get_bd_pins axi_hwicap_0/s_axi_aclk] [get_bd_pins axi_slave_wishbone_classic_master_0/S_AXI_ACLK] [get_bd_pins axi_timebase_wdt_0/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/M06_ACLK] [get_bd_pins microblaze_0_axi_periph/M07_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_Clk_100M/slowest_sync_clk] + connect_bd_net -net microblaze_0_Clk [get_bd_ports Clk] [get_bd_pins axi_hwicap_0/icap_clk] [get_bd_pins axi_hwicap_0/s_axi_aclk] [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins axi_slave_wishbone_classic_master_0/S_AXI_ACLK] [get_bd_pins axi_timebase_wdt_0/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/M06_ACLK] [get_bd_pins microblaze_0_axi_periph/M07_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_Clk_100M/slowest_sync_clk] [get_bd_pins xadc_wiz_0/s_axi_aclk] connect_bd_net -net rst_Clk_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_Clk_100M/bus_struct_reset] connect_bd_net -net rst_Clk_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_Clk_100M/interconnect_aresetn] connect_bd_net -net rst_Clk_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_axi_intc/processor_rst] [get_bd_pins rst_Clk_100M/mb_reset] - connect_bd_net -net rst_Clk_100M_peripheral_aresetn [get_bd_pins axi_hwicap_0/s_axi_aresetn] [get_bd_pins axi_slave_wishbone_classic_master_0/S_AXI_ARESETN] [get_bd_pins axi_timebase_wdt_0/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/M06_ARESETN] [get_bd_pins microblaze_0_axi_periph/M07_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_Clk_100M/peripheral_aresetn] + connect_bd_net -net rst_Clk_100M_peripheral_aresetn [get_bd_pins axi_hwicap_0/s_axi_aresetn] [get_bd_pins axi_quad_spi_0/s_axi_aresetn] [get_bd_pins axi_slave_wishbone_classic_master_0/S_AXI_ARESETN] [get_bd_pins axi_timebase_wdt_0/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/M06_ARESETN] [get_bd_pins microblaze_0_axi_periph/M07_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_Clk_100M/peripheral_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn] + connect_bd_net -net xadc_wiz_0_ip2intc_irpt [get_bd_pins xadc_wiz_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In3] connect_bd_net -net xlconcat_0_dout [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins xlconcat_0/dout] # Create address segments From 0912781502e1458b9d13cdba91ae08efcf22c7f1 Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Thu, 20 Oct 2022 12:28:17 -0700 Subject: [PATCH 4/7] Add missing IPs --- jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl index 34bff5a12c..db1690aeb3 100644 --- a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl +++ b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl @@ -124,6 +124,7 @@ set bCheckIPs 1 if { $bCheckIPs == 1 } { set list_check_ips "\ xilinx.com:ip:axi_hwicap:3.0\ +xilinx.com:ip:axi_quad_spi:3.2\ peralex.com:user:axi_slave_wishbone_classic_master:1.0\ xilinx.com:ip:axi_timebase_wdt:3.0\ xilinx.com:ip:axi_timer:2.0\ @@ -132,6 +133,7 @@ xilinx.com:ip:mdm:3.2\ xilinx.com:ip:microblaze:11.0\ xilinx.com:ip:axi_intc:4.1\ xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:xadc_wiz:3.3\ xilinx.com:ip:xlconcat:2.1\ xilinx.com:ip:lmb_bram_if_cntlr:4.0\ xilinx.com:ip:lmb_v10:3.0\ From 95fe498428ac3c9767b3e253f6948d67288da6c5 Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Thu, 20 Oct 2022 12:35:06 -0700 Subject: [PATCH 5/7] Create the SPI interface port --- jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl index db1690aeb3..42671daf29 100644 --- a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl +++ b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl @@ -293,7 +293,7 @@ proc create_root_design { parentCell } { # Create interface ports set UART [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART ] - + set spi_rtl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi_rtl ] # Create ports set ACK_I [ create_bd_port -dir I ACK_I ] From 75ba4a430f4a679fca565dada1b085aef38e790c Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Fri, 21 Oct 2022 10:20:36 -0700 Subject: [PATCH 6/7] Add missing SPI and xadc_wiz address space mapping --- jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl index 42671daf29..d102a1e7e4 100644 --- a/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl +++ b/jasper_library/hdl_sources/microblaze_wb/microblaze_wb.tcl @@ -472,7 +472,8 @@ proc create_root_design { parentCell } { assign_bd_address -offset 0x00000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] -force assign_bd_address -offset 0x00000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] -force assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_axi_intc/S_AXI/Reg] -force - + assign_bd_address -offset 0x44A00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_quad_spi_0/AXI_LITE/Reg] -force + assign_bd_address -offset 0x44A10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] -force # Restore current instance current_bd_instance $oldCurInst From 8174e7802d54af9da2018aec42d57923acb9b9de Mon Sep 17 00:00:00 2001 From: Kiran Shila Date: Mon, 24 Oct 2022 09:56:00 -0700 Subject: [PATCH 7/7] Include SPI by default --- jasper_library/yellow_blocks/microblaze.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/jasper_library/yellow_blocks/microblaze.py b/jasper_library/yellow_blocks/microblaze.py index 164fdbff95..f6388ced77 100644 --- a/jasper_library/yellow_blocks/microblaze.py +++ b/jasper_library/yellow_blocks/microblaze.py @@ -16,7 +16,7 @@ def factory(blk, plat, hdl_root=None): return microblaze_k7(blk, plat, hdl_root) def initialize(self): - self.include_spi_ports = False + self.include_spi_ports = True if self.platform.name in ['snap2']: if self.platform.version == 1: self.memfile= 'executable_no_xadc.mem'