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Makefile
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XILINXCADROOT = /opt/cad/Xilinx/10.1/ISE
VINCDIR= \
-I../rtl/wb_conbus \
-I../rtl/lm32 \
-I../rtl/wb_ddr
SYN_SRC=
SIM_SRC= \
system_tb.v \
../sim/sram/sram16.v \
../sim/unisims/BUFG.v \
../sim/unisims/DCM.v
SRC= \
../system.v \
../rtl/lac/lac.v \
../rtl/lac/uart.v \
../rtl/lac/dp_ram.v \
../rtl/lm32/lm32_cpu.v \
../rtl/lm32/lm32_instruction_unit.v \
../rtl/lm32/lm32_decoder.v \
../rtl/lm32/lm32_simtrace.v \
../rtl/lm32/lm32_load_store_unit.v \
../rtl/lm32/lm32_adder.v \
../rtl/lm32/lm32_addsub.v \
../rtl/lm32/lm32_logic_op.v \
../rtl/lm32/lm32_shifter.v \
../rtl/lm32/lm32_multiplier.v \
../rtl/lm32/lm32_mc_arithmetic.v \
../rtl/lm32/lm32_interrupt.v \
../rtl/lm32/lm32_ram.v \
../rtl/wb_bram/wb_bram.v \
../rtl/wb_uart/wb_uart.v \
../rtl/wb_everloop/wb_everloop.v \
../rtl/wb_everloop/everloop.v \
../rtl/wb_everloop/everloop_bram.v \
../rtl/wb_SK6812RGBW/wb_SK6812RGBW.v \
../rtl/wb_SK6812RGBW/SK6812RGBW.v \
../rtl/wb_SK6812RGBW/ram.v \
../rtl/wb_timer/wb_timer.v \
../rtl/wb_gpio/wb_gpio.v \
../rtl/wb_spi/wb_spi.v \
../rtl/wb_memory/wb_control_top.v \
../rtl/wb_memory/control_led.v \
../rtl/wb_memory/ram_using_file.v \
../rtl/wb_conbus/conbus.v \
../rtl/wb_conbus/conbus_arb.v \
../rtl/wb_i2c/i2c_master_wb.v \
../rtl/wb_i2c/i2c_master.v \
../rtl/wb_fuente/wb_fuente.v \
../rtl/wb_fuente/ROM_fuente.v
IP=192.168.2.1
#############################################################################
# Synthesis constants
SYNCLEAN=system.bgn system.drc system.mrp system.ngd system.pcf
SYNCLEAN+=system.bld system.lso system.ncd system.ngm system.srp
SYNCLEAN+=system.bit system_signalbrowser.* system-routed_pad.tx
SYNCLEAN+=system.map system_summary.xml timing.twr
SYNCLEAN+=system-routed* system_usage* system.ngc param.opt netlist.lst
SYNCLEAN+=xst system.prj *ngr *xrpt _xmsgs xlnx_auto_0_xdb *html *log *xwbt
USAGE_DEPTH=0
SMARTGUIDE=
#############################################################################
# Simulation constants
SIMCLEAN=system_tb.vvp system_tb.vcd verilog.log system_tb.vvp.list simulation
CVER=cver
GTKWAVE=gtkwave
IVERILOG=iverilog
VVP=vvp
#############################################################################
#
sim: system_tb.vcd
syn: system.bit
view: system_tb.view
#############################################################################
# Ikarus verilog simulation
system_tb.vvp:
rm -rf simulation && mkdir simulation
cp system_tb.v system_conf.v simulation && cd simulation && rm -f $@.list
for i in $(SRC); do echo $$i >> simulation/$@.list; done
for i in $(SIM_SRC); do echo $$i >> simulation/$@.list; done
cd simulation && $(IVERILOG) -o $@ $(VINCDIR) -c $@.list -s $(@:.vvp=)
postsim: system.ngc
cd build && netgen -sim -ofmt verilog system.ngc
cd build && iverilog -Wall \
-y $(XILINXCADROOT)/verilog/src/unisims \
-y $(XILINXCADROOT)/verilog/src/XilinxCoreLib \
-y ../ \
system.v ../system_tb.v -o system.bin
cd build && vvp system.bin
%.vcd: %.vvp
cd simulation && $(VVP) $<
#############################################################################
# ISE Synthesis
system.prj:
rm -rf build && mkdir build
@rm -f $@
for i in $(SRC); do echo verilog work $$i >> build/$@; done
for i in $(SRC_HDL); do echo VHDL work $$i >> build/$@; done
system.ngc: system.prj
cd build && xst -ifn ../system.xst
system.ngd: system.ngc system.ucf
cd build && ngdbuild -uc ../system.ucf system.ngc
system.ncd: system.ngd
cd build && map $(SMARTGUIDE) system.ngd
system-routed.ncd: system.ncd
cd build && par $(SMARTGUIDE) -ol high -w system.ncd system-routed.ncd
system.bit: system-routed.ncd
cd build && bitgen -w system-routed.ncd system.bit
@mv -f build/system.bit $@
system.mcs: system.bit
cd build && promgen -u 0 system
system-routed.xdl: system-routed.ncd
cd build && xdl -ncd2xdl system-routed.ncd system-routed.xdl
system-routed.twr: system-routed.ncd
cd build && trce -v 10 system-routed.ncd system.pcf
timing: system-routed.twr
usage: system-routed.xdl
xdlanalyze.pl system-routed.xdl $(USAGE_DEPTH)
upload:
scp system.bit pi@$(IP):/home/pi
ssh pi@$(IP) sudo xc3sprog -c matrix_pi /home/pi/system.bit -p 1
####################################################################
# final targets
%.view: %.vcd
cd simulation && $(GTKWAVE) $< $<.save
clean:
rm -Rf build $(SYNCLEAN) $(SIMCLEAN)
.PHONY: clean view