diff --git a/events/chips-2023-fall-event/index.html b/events/chips-2023-fall-event/index.html index 18c0b339d..aa81d9eb5 100644 --- a/events/chips-2023-fall-event/index.html +++ b/events/chips-2023-fall-event/index.html @@ -17,21 +17,21 @@ development. Hosted by Google in …"> +Register and view schedule."> +Register and view schedule."> - + +Register and view schedule."> @@ -134,7 +134,8 @@

CHIPS Technology Update - November 2023

Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro, Open Compute Project, and others. This event is free to attend, however, registration is required.

-

Details here.

+

Register and view +schedule.

diff --git a/events/chips_ocp_2023/index.html b/events/chips_ocp_2023/index.html index 208b99c43..1f188669f 100644 --- a/events/chips_ocp_2023/index.html +++ b/events/chips_ocp_2023/index.html @@ -12,10 +12,10 @@ -CHIPS Alliance at the Open Compute Projecct Global Summit | CHIPS Alliance +CHIPS Alliance at the Open Compute Project Global Summit | CHIPS Alliance - + @@ -23,7 +23,7 @@ - + @@ -31,7 +31,7 @@ - + @@ -112,7 +112,7 @@
-

CHIPS Alliance at the Open Compute Projecct Global Summit

+

CHIPS Alliance at the Open Compute Project Global Summit

diff --git a/events/index.html b/events/index.html index cddb5438e..dd54a46a5 100644 --- a/events/index.html +++ b/events/index.html @@ -126,35 +126,36 @@

Upcoming Events

-CHIPS Alliance at the RISC-V North American Summit +CHIPS Technology Update - November 2023

-November 7, 2023 +November 9, 2023
-

Please join us at the RISC-V North American Summit November 7 - 8

-

Be sure to come visit us at the CHIPS Alliance booth at the event.

-

Details here:

+

Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative +development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro, Open Compute +Project, and others. This event is free to attend, however, registration is required.

+

Register and view +schedule.

-CHIPS Technology Update - November 2023 +RISC-V Summit North America 2023

-November 9, 2023 +November 7, 2023
-

Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative -development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro, Open Compute -Project, and others. This event is free to attend, however, registration is required.

-

Details here.

+

Please join us at the RISC-V North American Summit November 7 - 8

+

Be sure to come visit us at the CHIPS Alliance booth at the event.

+

Details here:

Past Events

-CHIPS Alliance at the Open Compute Projecct Global Summit +CHIPS Alliance at the Open Compute Project Global Summit

October 17, 2023 diff --git a/events/index.xml b/events/index.xml index ae906ea50..b989e0b14 100644 --- a/events/index.xml +++ b/events/index.xml @@ -1,7 +1,7 @@ Events on CHIPS Alliancehttps://chipsalliance.org/events/Recent content in Events on CHIPS AllianceHugo -- gohugo.ioen-usThu, 09 Nov 2023 00:00:00 +0000CHIPS Technology Update - November 2023https://chipsalliance.org/events/chips-2023-fall-event/Thu, 09 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/chips-2023-fall-event/Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro, Open Compute Project, and others. This event is free to attend, however, registration is required. -Details here.CHIPS Alliance at the RISC-V North American Summithttps://chipsalliance.org/events/riscv_na_2023/Tue, 07 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/riscv_na_2023/Please join us at the RISC-V North American Summit November 7 - 8 +Register and view schedule.RISC-V Summit North America 2023https://chipsalliance.org/events/riscv_na_2023/Tue, 07 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/riscv_na_2023/Please join us at the RISC-V North American Summit November 7 - 8 Be sure to come visit us at the CHIPS Alliance booth at the event. -Details here:CHIPS Alliance at the Open Compute Projecct Global Summithttps://chipsalliance.org/events/chips_ocp_2023/Tue, 17 Oct 2023 00:00:00 +0000https://chipsalliance.org/events/chips_ocp_2023/Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project. +Details here:CHIPS Alliance at the Open Compute Project Global Summithttps://chipsalliance.org/events/chips_ocp_2023/Tue, 17 Oct 2023 00:00:00 +0000https://chipsalliance.org/events/chips_ocp_2023/Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project. Be sure to come visit us at booth C37 hosted by the Linux Foundation at the event. Details hereCHIPS Alliance Summer Workshop 2023https://chipsalliance.org/events/chips-biannual-technology-update-2022_13_07/Thu, 13 Jul 2023 00:00:00 +0000https://chipsalliance.org/events/chips-biannual-technology-update-2022_13_07/Check out the presentations below, and watch the replay here Caliptra & VeeR continuous integration ecosystem – Michael Gielda, Antmicro (slides) Caliptra: Validating firmware against multiple hardware models in CI - Kor Nielsen, Google OmniXtend: coherent scaleout over commodity fabrics - Jaco Hoffman, Westen Digital (slides) CHISEL 3 and Beyond - Jack Koenig, SiFive (slides) Single Source library for digital design and virtual prototyping - Mikhail Moiseev, Intel (slides) Building Confidence in Open IC Design using OpenFASOC - Mehdi Saligane, University of Michigan (slides) Watch the ReplayCHIPS Alliance Fall Workshop 2022https://chipsalliance.org/events/chips-biannual-technology-update-2022-2/Thu, 15 Dec 2022 00:00:00 +0000https://chipsalliance.org/events/chips-biannual-technology-update-2022-2/Check out the presentations below, and watch the replay here diff --git a/events/riscv_na_2023/index.html b/events/riscv_na_2023/index.html index 5a3bfc412..67fc45ea7 100644 --- a/events/riscv_na_2023/index.html +++ b/events/riscv_na_2023/index.html @@ -12,12 +12,12 @@ -CHIPS Alliance at the RISC-V North American Summit | CHIPS Alliance +RISC-V Summit North America 2023 | CHIPS Alliance - + @@ -25,7 +25,7 @@ - + @@ -33,7 +33,7 @@ - + @@ -114,7 +114,7 @@
-

CHIPS Alliance at the RISC-V North American Summit

+

RISC-V Summit North America 2023

@@ -138,7 +138,7 @@

CHIPS Alliance at the RISC-V North American Summit

Please join us at the RISC-V North American Summit November 7 - 8

Be sure to come visit us at the CHIPS Alliance booth at the event.

-

Details here:

+

Details here:

diff --git a/index.xml b/index.xml index fdc078b8d..3c9567f7d 100644 --- a/index.xml +++ b/index.xml @@ -1,7 +1,7 @@ CHIPS Alliancehttps://chipsalliance.org/Recent content on CHIPS AllianceHugo -- gohugo.ioen-usThu, 09 Nov 2023 00:00:00 +0000CHIPS Technology Update - November 2023https://chipsalliance.org/events/chips-2023-fall-event/Thu, 09 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/chips-2023-fall-event/Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro, Open Compute Project, and others. This event is free to attend, however, registration is required. -Details here.CHIPS Alliance at the RISC-V North American Summithttps://chipsalliance.org/events/riscv_na_2023/Tue, 07 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/riscv_na_2023/Please join us at the RISC-V North American Summit November 7 - 8 +Register and view schedule.RISC-V Summit North America 2023https://chipsalliance.org/events/riscv_na_2023/Tue, 07 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/riscv_na_2023/Please join us at the RISC-V North American Summit November 7 - 8 Be sure to come visit us at the CHIPS Alliance booth at the event. -Details here:CHIPS Alliance at the Open Compute Projecct Global Summithttps://chipsalliance.org/events/chips_ocp_2023/Tue, 17 Oct 2023 00:00:00 +0000https://chipsalliance.org/events/chips_ocp_2023/Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project. +Details here:CHIPS Alliance at the Open Compute Project Global Summithttps://chipsalliance.org/events/chips_ocp_2023/Tue, 17 Oct 2023 00:00:00 +0000https://chipsalliance.org/events/chips_ocp_2023/Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project. Be sure to come visit us at booth C37 hosted by the Linux Foundation at the event. Details hereVerilator Model Generation Performance Improvements and Initial Multithreaded Verilation Supporthttps://chipsalliance.org/news/verilator-model-generation-performance-improvements-and-initial-multithreaded-verilation-support/Fri, 29 Sep 2023 00:00:00 +0000https://chipsalliance.org/news/verilator-model-generation-performance-improvements-and-initial-multithreaded-verilation-support/Verilator can boast the status of one of the most widely used free and open source digital design tools for ASIC and FPGA development. To stay on top of the ever-increasing complexity of ASIC and FPGA devices, as users and contributors, Antmicro, a CHIPS Alliance member and part of the Tools Workgroup, has been actively working on improving the tool and its ecosystem, including adding co-simulation capabilities with Renode, adding support for SystemVerilog UVM testbenches to Verilator, or improving scalability for very large designs.Progress in open source SystemVerilog / UVM support in Verilatorhttps://chipsalliance.org/news/progress-in-open-source-systemverilog-uvm-support-in-verilator/Fri, 21 Jul 2023 00:00:00 +0000https://chipsalliance.org/news/progress-in-open-source-systemverilog-uvm-support-in-verilator/Verilator is a shining example of a widely-accepted open source tool which provides state-of-the-art results in the ASIC design space. It is commonly used for simulation and testing, but originally, due to the lack of capability to run event-driven simulations, Verilator wasn’t even considered capable of handling UVM (Universal Verification Methodology) testbenches implemented in SystemVerilog which require scheduling and other features notably absent from the tool. For some time now, Antmicro, together with Western Digital, Google and others in the CHIPS Alliance, has been working on enabling fully open source support for SystemVerilog UVM testbenches in Verilator.CHIPS Alliance Summer Workshop 2023https://chipsalliance.org/events/chips-biannual-technology-update-2022_13_07/Thu, 13 Jul 2023 00:00:00 +0000https://chipsalliance.org/events/chips-biannual-technology-update-2022_13_07/Check out the presentations below, and watch the replay here Caliptra & VeeR continuous integration ecosystem – Michael Gielda, Antmicro (slides) Caliptra: Validating firmware against multiple hardware models in CI - Kor Nielsen, Google OmniXtend: coherent scaleout over commodity fabrics - Jaco Hoffman, Westen Digital (slides) CHISEL 3 and Beyond - Jack Koenig, SiFive (slides) Single Source library for digital design and virtual prototyping - Mikhail Moiseev, Intel (slides) Building Confidence in Open IC Design using OpenFASOC - Mehdi Saligane, University of Michigan (slides) Watch the ReplayOpen source and CI-driven RTL testing and verification for Caliptra’s RISC-V VeeR corehttps://chipsalliance.org/news/open-source-rtl-ci-testing-and-verification-for-caliptra-veer/Tue, 04 Jul 2023 00:00:00 +0000https://chipsalliance.org/news/open-source-rtl-ci-testing-and-verification-for-caliptra-veer/As part of CHIPS Alliance’s mission to enable a software-driven approach to silicon, working with Google and other CHIPS members, Antmicro has been developing and improving a growing number of open source tools to enable effective, CI-driven silicon development. @@ -89,6 +89,6 @@ THe CHIPS Alliance is hosted by The Linux Foundation, a 501(c)6 non-profit.Joinhttps://chipsalliance.org/join/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/join/The CHIPS Alliance is an organization which works collaboratively to develop high quality, open source hardware designs relevant to silicon devices and FPGAs. By sharing openly resources and ideas, we hope to lower the cost of hardware development. As a collection of open source projects, anyone is welcome to participate in the technical development process. The Technical Steering Committee is governed by a technical charter. The CHIPS Alliance also welcomes corporate members.Membershttps://chipsalliance.org/about/members/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/about/members/When an organization joins the CHIPS Alliance, they are making a tangible commitment to the success and sustainability of open source projects which help to achieve these goals. The CHIPS Alliance recognizes the critical supporting role of these organizations, and thanks them for their ongoing support of our project communities. -CHIPS Alliance Members Become a Member Platinum Members Gold Members Silver Members Auditor Members Associate MembersProjectshttps://chipsalliance.org/projects/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/projects/Graduated Projects Caliptra The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust Repositories: caliptra caliptra-rtl caliptra-sw caliptra-ureg caliptra-dpe Issue Tracker Website Contact: Andres Lagar-Cavilla (GitHub) FPGA Interchange format FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.Rocket Workgrouphttps://chipsalliance.org/workgroups/rocket/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/rocket/The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.Tools Workgrouphttps://chipsalliance.org/workgroups/tools/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/tools/The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.Who We Arehttps://chipsalliance.org/about/who-we-are/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/about/who-we-are/The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification. +CHIPS Alliance Members Become a Member Platinum Members Gold Members Silver Members Auditor Members Associate MembersProjectshttps://chipsalliance.org/projects/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/projects/Graduated Projects Caliptra The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust Repositories: caliptra caliptra-rtl caliptra-sw caliptra-ureg caliptra-dpe Issue Tracker Website Contact: Andres Lagar-Cavilla (GitHub) F4PGA Free and open source toolchain for FPGA devices Repositories: f4pga Issue Tracker Website Contact: Tomasz Michalak (GitHub) FPGA Interchange format FPGA Interchange is a Vendor agnostic FPGA devices and designs description.Rocket Workgrouphttps://chipsalliance.org/workgroups/rocket/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/rocket/The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.Tools Workgrouphttps://chipsalliance.org/workgroups/tools/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/tools/The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.Who We Arehttps://chipsalliance.org/about/who-we-are/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/about/who-we-are/The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification. The scope of the Project includes hardware and software design and development under an open source (Apache v2) license: Verified IP blocks (compute cores, accelerators etc) Verified SoC designs (based on RISC-V and other open source cores) Open source software development tools for ASIC development High value IP including analog peripherals, mixed signal blocks and compute acceleration Exploration of new design flows such as Python-based design verification. \ No newline at end of file diff --git a/projects/index.html b/projects/index.html index 4588d598d..9ad6307e2 100644 --- a/projects/index.html +++ b/projects/index.html @@ -155,41 +155,41 @@

Caliptra

- -Placeholder project logo + +F4PGA
-

FPGA Interchange format

-

FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.

+

F4PGA

+

Free and open source toolchain for FPGA devices

- -F4PGA + +Placeholder project logo
-

F4PGA

-

Free and open source toolchain for FPGA devices

+

FPGA Interchange format

+

FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.