From 7749d677d48c1560a80e4281ce7eb7566873d445 Mon Sep 17 00:00:00 2001 From: bensternthal Date: Wed, 20 Mar 2024 20:45:10 +0000 Subject: [PATCH] deploy: 6e55ced2a12742d29e0c7f5759dda5daca4704b0 --- events/google-summer-of-code-2024/index.html | 237 +++++++++++++++++++ events/index.html | 14 ++ events/index.xml | 2 +- index.xml | 4 +- projects/index.html | 190 +++++++-------- sitemap.xml | 2 +- 6 files changed, 350 insertions(+), 99 deletions(-) create mode 100644 events/google-summer-of-code-2024/index.html diff --git a/events/google-summer-of-code-2024/index.html b/events/google-summer-of-code-2024/index.html new file mode 100644 index 000000000..24a193b3a --- /dev/null +++ b/events/google-summer-of-code-2024/index.html @@ -0,0 +1,237 @@ + + + + + + + + + + + + + + +Google Summer of Code 2024 | CHIPS Alliance + + + + + + + + + + + + + + + + + + + + +
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Google Summer of Code 2024

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As in previous years, CHIPS Alliance returns as a mentor organization for Google Summer of Code 2024. +Become a contributor and join us in our mission to push forward open source hardware, ASIC and FPGA design. +Explore our list of project ideas and submit by April 2: +https://github.com/chipsalliance/ideas/blob/main/gsoc-2024-ideas.md

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Details here:

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+Google Summer of Code 2024 +

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+April 2, 2024 +
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As in previous years, CHIPS Alliance returns as a mentor organization for Google Summer of Code 2024. +Become a contributor and join us in our mission to push forward open source hardware, ASIC and FPGA design. +Explore our list of project ideas and submit by April 2: +https://github.com/chipsalliance/ideas/blob/main/gsoc-2024-ideas.md

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Past Events

diff --git a/events/index.xml b/events/index.xml index 008a1df90..0a87ddcda 100644 --- a/events/index.xml +++ b/events/index.xml @@ -1,6 +1,6 @@ Events on CHIPS Alliancehttps://chipsalliance.org/events/Recent content in Events on CHIPS AllianceHugo -- gohugo.ioen-usMon, 15 Apr 2024 00:00:00 +0000Open Hardware and Software: Accelerating Beyond Moore’s Law and Enabling the Next Wave of Innovationhttps://chipsalliance.org/events/chips-2024-ossna-mini-summit/Mon, 15 Apr 2024 00:00:00 +0000https://chipsalliance.org/events/chips-2024-ossna-mini-summit/Want to learn more about open source hardware and software? Come see us at the Linux Foundation Open Source Summit April 15-18 in Seattle. We will have a mini-summit on Linux Foundation open hardware efforts on April 15 featuring talks from CHIPS Alliance, OpenPower, and RISC-V. -Details here:CHIPS Technology Update - November 2023https://chipsalliance.org/events/chips-2023-fall-event/Thu, 09 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/chips-2023-fall-event/Check out the presentations below, and watch the replay here +Details here:Google Summer of Code 2024https://chipsalliance.org/events/google-summer-of-code-2024/Tue, 02 Apr 2024 00:00:00 +0000https://chipsalliance.org/events/google-summer-of-code-2024/As in previous years, CHIPS Alliance returns as a mentor organization for Google Summer of Code 2024. Become a contributor and join us in our mission to push forward open source hardware, ASIC and FPGA design. Explore our list of project ideas and submit by April 2: https://github.com/chipsalliance/ideas/blob/main/gsoc-2024-ideas.mdCHIPS Technology Update - November 2023https://chipsalliance.org/events/chips-2023-fall-event/Thu, 09 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/chips-2023-fall-event/Check out the presentations below, and watch the replay here Project Open Se Cura – Kenny Vassigh, Bangfei Pan, Cindy Liu, Kai Yick, Google, Michael Gielda, Antmicro, Brian Murray, Verisilicon (slides) Caliptra Workgroup Update - Andres Lagar-Cavilla, Google (slides) Enabling UVM testbenches in Verilator - Michael Gielda, Karol Gugala, Antmicro (slides) FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development - Olof Kindgren, Qamcom (slides) CHIPYard: An Open Source RISC-V Design Frameowrk - Sagar Karandikar, U.RISC-V Summit North America 2023https://chipsalliance.org/events/riscv_na_2023/Tue, 07 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/riscv_na_2023/Please join us at the RISC-V North American Summit November 7 - 8 Be sure to come visit us at the CHIPS Alliance booth at the event. Details here:CHIPS Alliance at the Open Compute Project Global Summithttps://chipsalliance.org/events/chips_ocp_2023/Tue, 17 Oct 2023 00:00:00 +0000https://chipsalliance.org/events/chips_ocp_2023/Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project. diff --git a/index.xml b/index.xml index ba3d31807..c9396ffde 100644 --- a/index.xml +++ b/index.xml @@ -1,6 +1,6 @@ CHIPS Alliancehttps://chipsalliance.org/Recent content on CHIPS AllianceHugo -- gohugo.ioen-usMon, 15 Apr 2024 00:00:00 +0000Open Hardware and Software: Accelerating Beyond Moore’s Law and Enabling the Next Wave of Innovationhttps://chipsalliance.org/events/chips-2024-ossna-mini-summit/Mon, 15 Apr 2024 00:00:00 +0000https://chipsalliance.org/events/chips-2024-ossna-mini-summit/Want to learn more about open source hardware and software? Come see us at the Linux Foundation Open Source Summit April 15-18 in Seattle. We will have a mini-summit on Linux Foundation open hardware efforts on April 15 featuring talks from CHIPS Alliance, OpenPower, and RISC-V. -Details here:Analyze Verilator processes and ASTs with the astsee suitehttps://chipsalliance.org/news/analyze-verilator-processes/Mon, 18 Mar 2024 00:00:00 +0000https://chipsalliance.org/news/analyze-verilator-processes/Among other things, Antmicro’s work towards improving the vertical integration potential of customers designing ASIC solutions often sees them enhance one of the flagship open source projects in this space, Verilator which complements - and in fact is often used alongside - Antmicro’s own functional simulation framework, Renode. Besides contributing bug fixes and other quality-of-life improvements into Verilator, Antmicro also develops new functionalities that expand its use cases towards e.g. UVM verification and continuously improve overall performance.Versatile SO-DIMM (LP)DDR5 Rowhammer testing platformhttps://chipsalliance.org/news/versatile-rowhammer-testing-platform/Mon, 11 Mar 2024 00:00:00 +0000https://chipsalliance.org/news/versatile-rowhammer-testing-platform/Ten years after the first disclosure of the initial Rowhammer security exploit, new DRAM vulnerabilities continue to be discovered, and developing new and efficient mitigation techniques requires a deep understanding of the problem considering the complexity of modern DRAM. To safeguard its Data Center and edge device use cases, Google has been using Antmicro’s advanced R&D capabilities to develop an open source FPGA-based memory testing suite and family of open hardware platforms, expanding beyond the capabilities of pure-software vulnerability testing and mitigation approaches.CHIPS Technology Update - November 2023https://chipsalliance.org/events/chips-2023-fall-event/Thu, 09 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/chips-2023-fall-event/Check out the presentations below, and watch the replay here +Details here:Google Summer of Code 2024https://chipsalliance.org/events/google-summer-of-code-2024/Tue, 02 Apr 2024 00:00:00 +0000https://chipsalliance.org/events/google-summer-of-code-2024/As in previous years, CHIPS Alliance returns as a mentor organization for Google Summer of Code 2024. Become a contributor and join us in our mission to push forward open source hardware, ASIC and FPGA design. Explore our list of project ideas and submit by April 2: https://github.com/chipsalliance/ideas/blob/main/gsoc-2024-ideas.mdAnalyze Verilator processes and ASTs with the astsee suitehttps://chipsalliance.org/news/analyze-verilator-processes/Mon, 18 Mar 2024 00:00:00 +0000https://chipsalliance.org/news/analyze-verilator-processes/Among other things, Antmicro’s work towards improving the vertical integration potential of customers designing ASIC solutions often sees them enhance one of the flagship open source projects in this space, Verilator which complements - and in fact is often used alongside - Antmicro’s own functional simulation framework, Renode. Besides contributing bug fixes and other quality-of-life improvements into Verilator, Antmicro also develops new functionalities that expand its use cases towards e.g. UVM verification and continuously improve overall performance.Versatile SO-DIMM (LP)DDR5 Rowhammer testing platformhttps://chipsalliance.org/news/versatile-rowhammer-testing-platform/Mon, 11 Mar 2024 00:00:00 +0000https://chipsalliance.org/news/versatile-rowhammer-testing-platform/Ten years after the first disclosure of the initial Rowhammer security exploit, new DRAM vulnerabilities continue to be discovered, and developing new and efficient mitigation techniques requires a deep understanding of the problem considering the complexity of modern DRAM. To safeguard its Data Center and edge device use cases, Google has been using Antmicro’s advanced R&D capabilities to develop an open source FPGA-based memory testing suite and family of open hardware platforms, expanding beyond the capabilities of pure-software vulnerability testing and mitigation approaches.CHIPS Technology Update - November 2023https://chipsalliance.org/events/chips-2023-fall-event/Thu, 09 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/chips-2023-fall-event/Check out the presentations below, and watch the replay here Project Open Se Cura – Kenny Vassigh, Bangfei Pan, Cindy Liu, Kai Yick, Google, Michael Gielda, Antmicro, Brian Murray, Verisilicon (slides) Caliptra Workgroup Update - Andres Lagar-Cavilla, Google (slides) Enabling UVM testbenches in Verilator - Michael Gielda, Karol Gugala, Antmicro (slides) FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development - Olof Kindgren, Qamcom (slides) CHIPYard: An Open Source RISC-V Design Frameowrk - Sagar Karandikar, U.Initial Open Source Support for UVM Testbenches in Verilatorhttps://chipsalliance.org/news/initial-open-source-support-for-uvm-testbenches-in-verilator/Wed, 08 Nov 2023 00:00:00 +0000https://chipsalliance.org/news/initial-open-source-support-for-uvm-testbenches-in-verilator/Leading the efforts of the Tools Workgroup in CHIPS Alliance, across a variety of customer projects, as well as its own R&D, Antmicro is actively looking for and capturing the productivity enhancements that can be achieved in ASIC design using open source. Developing and using open source-enhanced workflows is one thing, but in order for the general shift towards open source to happen, open source support for tooling and methodologies that are already prevalent across the chipmaking industry is necessary.RISC-V Summit North America 2023https://chipsalliance.org/events/riscv_na_2023/Tue, 07 Nov 2023 00:00:00 +0000https://chipsalliance.org/events/riscv_na_2023/Please join us at the RISC-V North American Summit November 7 - 8 Be sure to come visit us at the CHIPS Alliance booth at the event. Details here:CHIPS Alliance at the Open Compute Project Global Summithttps://chipsalliance.org/events/chips_ocp_2023/Tue, 17 Oct 2023 00:00:00 +0000https://chipsalliance.org/events/chips_ocp_2023/Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project. @@ -91,6 +91,6 @@ THe CHIPS Alliance is hosted by The Linux Foundation, a 501(c)6 non-profit.Interconnect Workgrouphttps://chipsalliance.org/workgroups/interconnect/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/interconnect/The Interconnect workgroup researches open networking protocols to facilitate direct coherency messaging between components such as processor caches, memory controllers, and various accelerators in RISC-V cores. The interconnections provided by this group play a crucial role in SoCs, chiplets, and various hardware designs. We offer design guidelines for interconnects and manage open-source interconnect IP based on these guidelines. Interconnect WG supports the advancement of the open-source hardware ecosystem.Joinhttps://chipsalliance.org/join/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/join/The CHIPS Alliance is an organization which works collaboratively to develop high quality, open source hardware designs relevant to silicon devices and FPGAs. By sharing openly resources and ideas, we hope to lower the cost of hardware development. As a collection of open source projects, anyone is welcome to participate in the technical development process. The Technical Steering Committee is governed by a technical charter. The CHIPS Alliance also welcomes corporate members.Membershttps://chipsalliance.org/about/members/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/about/members/When an organization joins the CHIPS Alliance, they are making a tangible commitment to the success and sustainability of open source projects which help to achieve these goals. The CHIPS Alliance recognizes the critical supporting role of these organizations, and thanks them for their ongoing support of our project communities. -CHIPS Alliance Members Become a Member Platinum Members Gold Members Silver Members Auditor Members Associate MembersProjectshttps://chipsalliance.org/projects/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/projects/Graduated Projects Caliptra The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust Repositories: caliptra caliptra-rtl caliptra-sw caliptra-ureg caliptra-dpe Issue Tracker Website Contact: Andres Lagar-Cavilla (GitHub) F4PGA Free and open source toolchain for FPGA devices Repositories: f4pga Issue Tracker Website Contact: Tomasz Michalak (GitHub) FPGA Interchange format FPGA Interchange is a Vendor agnostic FPGA devices and designs description.Rocket Workgrouphttps://chipsalliance.org/workgroups/rocket/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/rocket/The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.Tools Workgrouphttps://chipsalliance.org/workgroups/tools/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/tools/The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.Who We Arehttps://chipsalliance.org/about/who-we-are/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/about/who-we-are/The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification. +CHIPS Alliance Members Become a Member Platinum Members Gold Members Silver Members Auditor Members Associate MembersProjectshttps://chipsalliance.org/projects/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/projects/Graduated Projects FPGA tool perf Framework for automatic FPGA toolchains benchmarking Repositories: fpga-tool-perf actions Issue Tracker Website Contact: Tomasz Gorochowik (GitHub) OmniXtend Cache coherence framework for RISC-V based on TileLink Repositories: omnixtend OmnixtendEndpoint OmniXtend_RemoteAgent_RISC-V Issue Tracker Website Contact: Jaco Hofmann (GitHub) Intel Compiler for SystemC Open source SystemC to SystemVerilog translation tool and SingleSource library.Rocket Workgrouphttps://chipsalliance.org/workgroups/rocket/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/rocket/The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.Tools Workgrouphttps://chipsalliance.org/workgroups/tools/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/workgroups/tools/The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.Who We Arehttps://chipsalliance.org/about/who-we-are/Mon, 01 Jan 0001 00:00:00 +0000https://chipsalliance.org/about/who-we-are/The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification. The scope of the Project includes hardware and software design and development under an open source (Apache v2) license: Verified IP blocks (compute cores, accelerators etc) Verified SoC designs (based on RISC-V and other open source cores) Open source software development tools for ASIC development High value IP including analog peripherals, mixed signal blocks and compute acceleration Exploration of new design flows such as Python-based design verification. \ No newline at end of file diff --git a/projects/index.html b/projects/index.html index 1a60d9e9e..2575d4775 100644 --- a/projects/index.html +++ b/projects/index.html @@ -131,189 +131,209 @@

Graduated Projects

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Caliptra

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The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust

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FPGA tool perf

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Framework for automatic FPGA toolchains benchmarking

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F4PGA

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Free and open source toolchain for FPGA devices

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OmniXtend

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Cache coherence framework for RISC-V based on TileLink

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FPGA Interchange format

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FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.

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Intel Compiler for SystemC

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Open source SystemC to SystemVerilog translation tool and SingleSource library.

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FPGA tool perf

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Framework for automatic FPGA toolchains benchmarking

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Verible

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Parse SystemVerilog (IEEE 1800-2017) with a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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Intel Compiler for SystemC

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Open source SystemC to SystemVerilog translation tool and SingleSource library.

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RISCV-DV

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RISCV-DV is an open source verification tool for RISC-V processors. RISCV-DV is a SystemVerilog based random RISC-V instruction generator that checks the execution against an industry standard ISS for correction and compliance.

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OmniXtend

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Cache coherence framework for RISC-V based on TileLink

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OpenFASOC

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Fully Open Source Automated Analog Block Generation built on top of OpenROAD, Magic, Netgen, Klayout and Ngspice

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OpenFASOC

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Fully Open Source Automated Analog Block Generation built on top of OpenROAD, Magic, Netgen, Klayout and Ngspice

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RocketChip

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The SoC generator instantiates the RISC-V Rocket Core and relevant component.

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RISCV-DV

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RISCV-DV is an open source verification tool for RISC-V processors. RISCV-DV is a SystemVerilog based random RISC-V instruction generator that checks the execution against an industry standard ISS for correction and compliance.

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Caliptra

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The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust

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F4PGA

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Free and open source toolchain for FPGA devices

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RocketChip

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The SoC generator instantiates the RISC-V Rocket Core and relevant component.

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FPGA Interchange format

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FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.

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SV tests

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Verible

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Parse SystemVerilog (IEEE 1800-2017) with a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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Sandbox Projects

diff --git a/sitemap.xml b/sitemap.xml index dd7a2bdfe..35d5353ce 100644 --- a/sitemap.xml +++ b/sitemap.xml @@ -1 +1 @@ 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