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+Blog
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+September 29, 2023
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+Mailing Address
+CHIPS Alliance
+1 Letterman Drive, Building D, Suite D4700
+San Francisco, CA 94129
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+The CHIPS Alliance is always interested in hearing from our community, supporters, users of our projects, and anyone else interested in using our projects.
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+CHIPS Alliance
+1 Letterman Drive, Building D, Suite D4700
+San Francisco, CA 94129
+Learn more about CHIPS Alliance!
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+Members are never obligated to contribute to code or specification projects in CHIPS Alliance, nor are they obligated to participate in the development process in any way. Members and non-members alike must sign a CHIPS Alliance CLA (distinct from membership) before contributing to code or specification projects.
+Our specification projects leverage the OWFa 0.9 (Necessary Claims) license, as described in the CHIPS directed fund charter which is included in the project’s membership agreement. Prospective members will want to review the IP policy set forth in the charter with their own legal counsel, in order to understand how the implementation of OWFa may relate to their specific situation. Please note also that CHIPS utilizes a notice and voting period in connection with specification releases, and provides a mechanism for members to opt out of further commitments under OWFa at any time by following the procedures outlined in the IP policy.
+Our CLAs can be found in the TSC repository.
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+The CHIPS Alliance is a directed fund of The Linux Foundation, a 501(c)(6) non-profit organization. Following best practices in the industry, we maintain a clear and consistent separation of responsibilities between technical and non-technical governance decisions. The CHIPS Alliance operates under its Charter.
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+In addition to the top-level structure of The CHIPS Alliance, each hosted open source project has its own process, structure, and community. While the Technical Steering Community (TSC) sets high-level technical policy, projects have a great deal of flexibility in day-to-day operations.
+The General Manager works with the Governing Board, our members, and our projects to ensure the CHIPS Alliance is a healthy, sustainable, and neutral home for open source technical collaborations.
+Rob Mains is a 38 year industry veteran, former engineering vice president of Oracle and Sun Microsystems distinguished engineer, where he lead an organization of over 200 software researchers and developers. Prior to this, Rob was a principal engineer at Magma Design Automation, and originally a senior engineer at IBM involved in numerous technical areas for the development of IBM Power and S/390 systems.
+Rob has in depth experience in software development, electronic design automation, IT management, semiconductor technology, microprocessor circuit design, and chip construction methodology. In his career, he has had the privilege of working in multi-company collaborations, understanding the dynamics of multiple players, and working towards win-win solutions for all. He is the holder of 13 U.S. patents.
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+The Governing Board sets overall policy through our participation agreement and technical charter, which describes the membership requirements and responsibilities of participants.
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+Berkeley
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+VeriSilicon
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+Infineon
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+Futerwei
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+Intel
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+Governing Board Chair
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+Antmicro
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+SiFive
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+AMD
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+AMI US Holdings Inc
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+Microsoft
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+ISCAS
+The Technical Steering Committee, or TSC, is responsible for the technical oversight of the CHIPS Alliance. The TSC is responsible for implementing technical policy and procedures within the scope and direction of the policies set by the Governing Board, such as defining and maintaining neutral consensus on the technical vision for CHIPS Alliance projects, shepherding projects through their technical lifecycle, and identifying, recruiting, and engaging prospective projects.
+The TSC operates openly and transparently, and consists of elected representatives from each CHIPS Alliance workgroup. TSC meetings are open to all, and both members and non-members may earn the right to participate in all TSC governance processes.
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+Chair
+The Outreach Committee is responsible for organizing the external presence of the CHIPS Alliance.
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+The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks. CHIPS Alliance is open to all organizations who are interested in collaborating on open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.
+Hosted Projects
+Established in
+Workgroups
+Member Organizations
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+Browser the CHIPS Alliance mailing lists and join groups you are interested in.
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+The mission of the CHIPS Alliance is to develop high-quality, open source hardware designs relevant to silicon devices and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks.
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+When an organization joins the CHIPS Alliance, they are making a tangible commitment to the success and sustainability of open source projects which help to achieve these goals. The CHIPS Alliance recognizes the critical supporting role of these organizations, and thanks them for their ongoing support of our project communities.
++ Become a Member +
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+The CHIPS Alliance is an organization which develops and hosts high quality, open source hardware code (IP cores), interconnect IP (phy and logical protocols), and open source software development tools for design, verification, and more. We seek to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development.
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+The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification.
+The scope of the Project includes hardware and software design and development under an open source (Apache v2) license:
+We also welcome organizations and institutions who wish to participate in the CHIPS Alliance governance process by becoming members. If you have questions, please reach out to membership@chipsalliance.org.
+The CHIPS Alliance is hosted by The Linux Foundation, a 501(c)6 non-profit organization.
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+Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative +development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro, Open Compute +Project, and others. This event is free to attend, however, registration is required.
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+Check out the presentations below:
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+Check out the presentations below, and watch the replay here
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+Check out the presentations below, and watch the replay here
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+Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project.
+Be sure to come visit us at booth C37 hosted by the Linux Foundation at the event.
+Details here
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+
+Check out the presentations below, and watch the replay here
+
+Join CHIPS Alliance workshops and meetings.
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+Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative +development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro, Open Compute +Project, and others. This event is free to attend, however, registration is required.
+ +Please join us at the RISC-V North American Summit November 7 - 8
+Be sure to come visit us at the CHIPS Alliance booth at the event.
+Details here:
+Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project.
+Be sure to come visit us at booth C37 hosted by the Linux Foundation at the event.
+Details here
+Check out the presentations below, and watch the replay here
+Check out the presentations below, and watch the replay here
+Check out the presentations below:
+Check out the presentations below, and watch the replay here
+Check out the presentations below, and watch the replay here
+
+
+Please join us at the RISC-V North American Summit November 7 - 8
+Be sure to come visit us at the CHIPS Alliance booth at the event.
+Details here:
+
+
+Check out the presentations below, and watch the replay here
+
+The CHIPS Alliance develops high-quality, open source hardware designs and open source hardware design tools relevant to silicon devices and FPGAs.
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+By creating an open and collaborative environment, the CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, complex IP blocks, tools and workflows.
+The CHIPS Alliance is open to all organizations who are interested in collaborating on open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.
+THe CHIPS Alliance is hosted by The Linux Foundation, a 501(c)6 non-profit.
+Read on to learn more about participation in the CHIPS Alliance, and join us as we develop open source hardware designs and tools!
+The CHIPS Alliance works in the open and welcomes all participants in our open source community. Here are the first things you should do to get involved.
+We recommend you join our mailing lists, as they are our primary means of communication. The CHIPS Alliance uses groups.io for our mailing lists. If you aren’t familiar with the process of joining groups, we have a tutorial on how to find and join our lists.
+Go to the Workgroups page for details, with mailing lists and meeting times.
+In addition to the lists which are open to everyone, we have some special-purpose mailing lists for members and individual participants in the CHIPS Alliance. If you work for a CHIPS Alliance member, or have completed the individual participant registration form, please visit these lists and apply for membership.
+Follow us on our social channels: Twitter, LinkedIn.
+Join our Slack. You can get an invite here.
+We publish our workgroup and meeting calendar (ical). Please email mailto:operations@chipsalliance.org to request new events on the calendar, or to be added to an existing invite.
+The CHIPS Alliance is home to multiple open source projects, which operate under the leadership of the Technical Steering Committee (TSC). These projects develop high quality open source hardware code (IP cores), interconnect IP (phy and logical protocols), and open source software development tools for design, verification, and more.
+Our projects represent a diverse range of technologies and implementations, and are organized into workgroups. Each of these workgroups are represented through membership in the TSC, our primary technical governing body.
+Participation in the development and decision-making process is open to anybody in the technical community. We strongly encourage developers to engage with our projects directly on a technical level.
+The TSC is governed by the CHIPS Alliance Technical Charter. The Charter provides the TSC a great deal of latitude to organize itself and its processes in such a way that benefits our technical communities.
+The TSC is comprised of technical representatives from CHIPS Alliance projects and workgroups, and led by a chairperson. All members of the technical community are welcome to subscribe to the TSC mailing list, and can participate in TSC meetings.
+The CHIPS Alliance is a member-supported organization. Our members provide 100% of the financial support for our activities. Among other things, this enables us to provide operational, marketing, and legal support for our hosted projects, enables logisitical support for the ongoing operations of the Alliance, and allows us to host technical workshops to advance the state of the art of open hardware design.
+We have a number of additional lists and committees for members. Here are a few more things you should do.
+Please contact operations@chipsalliance.org for any questions or issues related to membership.
+The CHIPS Alliance is managed by a Governing Board, comprised of member representatives, the TSC chair, and the Marketing Committee chair.
+Although the Governing Board delegates day-to-day technical governance to the TSC, it is responsible for setting the high-level policies which govern our projects. For example, the Governing Board works in close coordination with the Legal Committee to manage the Participation Agreement and the Technical Charter (including the IP Policy).
+In addition, the Governing Board is responsible for managing the organization’s budget.
+The Governing Board meets bi-weekly.
+The Marketing Committee is responsible for coordinating outreach activities and for responding to inbound requests. All CHIPS Alliance members are welcome to participate on Marketing Committee meetings and activities.
+Please send an email to operations@chipsalliance.org to be added to the mailing list and calendar invitation.
+The CHIPS Alliance Legal Committee is responsible for coordinating legal activity, including document and policy reviews. The Legal Committee makes recommendations to the Governing Board on such matters. All CHIPS Alliance members are welcome to designate a member of their in-house legal counsel to participate on this committee.
+Please send an email to operations@chipsalliance.org to be added to the mailing list and calendar invitation.
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+CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development.
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+The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks. CHIPS Alliance is open to all organizations who are interested in collaborating on open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.
+Hosted Projects
+Established in
+Workgroups
+Member Organizations
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+Browser the CHIPS Alliance mailing lists and join groups you are interested in.
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++ Become a Member +
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+Join the CHIPS Alliance and harness the tremendous amount of collaborative energy in open source hardware development.
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+The CHIPS Alliance is an organization which works collaboratively to develop high quality, open source hardware designs relevant to silicon devices and FPGAs. By sharing openly resources and ideas, we hope to lower the cost of hardware development.
+As a collection of open source projects, anyone is welcome to participate in the technical development process. The Technical Steering Committee is governed by a technical charter.
+The CHIPS Alliance also welcomes corporate members. By participating as a corporate member, your organization provides vital funding for the infrastructure and activities that support our open and collaborative development process.
+To join the CHIPS Alliance as a corporate member, please complete the participation agreement below. Please note that Linux Foundation membership is required to join the CHIPS Alliance.
+You may preview these documents before signing:
+If you have any questions, please email membership@chipsalliance.org!
++ Join Us +
+Please note that non-profit and academic institutions may join the Linux Foundation and the CHIPS Alliance as Associate members at no cost. Please contact us for more information.
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+CHIPS Alliance is excited by the Antmicro announcement of the extensible, open, Rowhammer testing framework for DDR5. Read a detailed description of their work here: https://antmicro.com/blog/2022/08/extending-the-open-source-rowhammer-testing-framework-to-ddr5/
+Here are some graphics of the work:
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+CHIPS Alliance was founded in March 2019 to design high-quality, open source hardware register transfer level (RTL) and develop open source hardware and software design tools. By creating an open and collaborative environment, companies and organizations can develop innovative, cost effective hardware designs optimized for the requirements of today’s silicon devices and FPGAs.
+CHIPS Alliance was incorporated by four organizations which wanted to make open source silicon a reality. Esperanto, Google, SiFive and Western Digital were the founding members. Now that one year has passed since the organization’s founding, it is fitting to look back at our progress so far. We are pleased to present this annual report detailing the many things we have accomplished collectively in this fast growing organization.
+Comments and feedback are welcome at info@chipsalliance.org.
+“The growth behind CHIPS Alliance has been incredible. We are laying the foundation for open source hardware development to become accessible to a wider number of companies, universities and individuals.”
+– Zvonimir Bandic, Governing Board Chair, CHIPS Alliance, and Senior Director, Western Digital
CHIPS Alliance is a barrier free, open organization focused on developing open source hardware RTL and open source hardware and software development tools. The organization desires to lower the cost of chip development through collaboration, leveraging the diverse expertise and broad experience of its members. CHIPS Alliance encourages contributions and shared investments by providing vendor-neutral promotional events, documentation, tools and support for a variety of projects in our workgroups.
+The following workgroups are part of CHIPS Alliance:
+In March 2019, CHIPS Alliance was formed as a project under the Linux Foundation. The four founding members – Esperanto, Google, SiFive and Western Digital – set the aspirations for the group. CHIPS Alliance can be viewed as an extension of the mission started by organizations such as RISC-V International. RISC-V defines an open instruction set architecture (ISA) specification which paved the way for a plethora of open cores and CPU implementations, but does not instruct how to make the physical hardware and other building blocks needed to create practical open silicon. This is where CHIPS Alliance begins. Using open standards such as RISC-V, CHIPS Alliance is working to collaboratively build robust and industry-proven cores, peripherals and SoCs.
+Early on it became clear that lowering the barriers and cost of development would require collaboration among many parties to develop relevant open source design tools. CHIPS Alliance stepped up to the task. Today the organization focuses on both open source hardware RTL designs and open source software and hardware design tool development. CHIPS Alliance is a barrier free, open organization promoting open silicon.
+CHIPS Alliance has grown to nineteen members over the past year. The organization now boasts some of the world’s leading semiconductor manufacturers including Intel, Samsung, Futurewei and Alibaba. Software tools, IP and services companies in the organization include Antmicro, Codasip, Imperas and Qamcom. Several notable universities and open source projects are also part of CHIPS Alliance, including the leading open simulator tool Verilator, UC Berkeley, IIT Madras, Yale University, OpenRoad, Munich University of Applied Sciences and UC San Diego. The complete membership list can be found at https://chipsalliance.org/.
+To aid new members and those who are interested in knowing more about CHIPS Alliance, we have created a Getting Started Guide. We encourage everyone to join our main mailing list, follow us on social media channels Twitter and LinkedIn, and engage in our technical community, which is not limited to members. If you see a particular workgroup you want to get involved in, you can join that specific mailing list and attend their meetings.
+After the formation of CHIPS Alliance, we began holding events to share what the organization is about and to highlight progress of various work groups. Listed chronologically:
+The members of CHIPS Alliance join for a variety of reasons. Some organizations join to grow their business. Companies that fall into this group normally offer an open source solution, along with selling support and additional services to interested companies. As an example, Codasip has an open SweRV package that anyone can access, a Pro version with commercial EDA tools, and customization and verification services available upon request.
+Many organizations join CHIPS Alliance to accelerate development of a RTL IP/SoC or software tool. For example, Verilator and Chisel are software development tools that have benefited from their organizations joining. See slide 4 of the Verilator, Accelerated presentation to see how CHIPS Alliance has benefited the Verilator ecosystem.
+Another reason companies join CHIPS Alliance is to accelerate adoption of IP or software. One such IP is AIB which was brought into CHIPS Alliance by Intel. AIB is a chiplet interconnect and is being adopted by a number of companies. Recently DARPA presented on the benefits of AIB and how chiplets can accelerate SoC development.
+While CHIPS Alliance had a number of in-person events planned for 2020, many of these events have been delayed or postponed due to COVID-19. In the meantime, the CHIPS Alliance will be hosting several online events and meetups. Sign up for our announcements list to be kept up-to-date on our events.
+The CHIPS Alliance has seen additional interest from a number of companies, organizations and nonprofits in joining our ecosystem, so we will continue to focus on growing our membership. As development accelerates and more output is generated, we anticipate this will foster even more interest in CHIPS Alliance and its open source solutions.
+Lastly, we are actively recruiting a full time executive director and hope to have this individual on board by mid-2020.
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+CHIPS Alliance was founded in March 2019 to design high-quality, open source hardware register transfer level (RTL) and develop open source hardware and software design tools. By creating an open and collaborative environment, companies and organizations can develop innovative, cost effective hardware designs optimized for the requirements of today’s silicon devices and FPGAs.
+CHIPS Alliance was incorporated by four organizations which wanted to make open source silicon a reality. Esperanto, Google, SiFive and Western Digital were the founding members. Now almost two years later, it is fitting to look back at our progress. We are pleased to present this annual report detailing the many things we have accomplished collectively in this fast growing organization.
+Comments and feedback are welcome at info@chipsalliance.org.
+++“The growth behind CHIPS Alliance has been incredible. We are laying the foundation for open source hardware development to become accessible to a wider number of companies, universities and individuals.”
+– Zvonimir Bandic, Governing Board Chair, CHIPS Alliance, and Senior Director, Western Digital
+
CHIPS Alliance is a barrier free, open organization focused on developing open source hardware RTL and open source hardware and software development tools. The organization desires to lower the cost of chip development through collaboration, leveraging the diverse expertise and broad experience of its members. CHIPS Alliance encourages contributions and shared investments by providing vendor-neutral promotional events, documentation, tools and support for a variety of projects in our workgroups.
+Rob Mains serves as General Manager of the CHIPS Alliance. Rob joined the organization in January 2021, bringing more than 38 years of industry experience to the role. To learn more about Rob, please visit here.
+The following workgroups are part of CHIPS Alliance:
+The organization is also working on setting up an Open Source Analog Design/Generators Working Group.
+In March 2019, CHIPS Alliance was formed as a project under the Linux Foundation. The four founding members – Esperanto, Google, SiFive and Western Digital – set the aspirations for the group. CHIPS Alliance can be viewed as an extension of the mission started by organizations such as RISC-V International. RISC-V defines an open instruction set architecture (ISA) specification which paved the way for a plethora of open cores and CPU implementations, but does not instruct how to make the physical hardware and other building blocks needed to create practical open silicon. This is where CHIPS Alliance begins. Using open standards such as RISC-V, CHIPS Alliance is working to collaboratively build robust and industry-proven cores, peripherals and SoCs.
+Early on it became clear that lowering the barriers and cost of development would require collaboration among many parties to develop relevant open source design tools. CHIPS Alliance stepped up to the task. Today the organization focuses on both open source hardware RTL designs and open source software and hardware design tool development. CHIPS Alliance is a barrier free, open organization promoting open silicon.
+CHIPS Alliance has grown to more than 25 members over the past year. The organization now boasts some of the world’s leading semiconductor manufacturers including Intel, Samsung, Futurewei and Alibaba. Software tools, IP and services companies in the organization include Antmicro, Codasip, Imperas, Qamcom and Verisilicon. Several notable universities and open source projects are also part of CHIPS Alliance such as UC Berkeley, IIT Madras, Yale University, OpenRoad, Munich University of Applied Sciences and UC San Diego. The complete membership list can be found at https://chipsalliance.org/about/members/
+To aid new members and those who are interested in knowing more about CHIPS Alliance, we have created a Getting Started Guide. We encourage everyone to join our main mailing list, follow us on social media channels Twitter and LinkedIn, and engage in our technical community, which is not limited to members. If you see a particular workgroup you want to get involved in, you can join that specific mailing list and attend their meetings.
+CHIPS Alliance hosted a number of events over the past year, pivoting to virtual workshops and Meetups due to the pandemic. Below please find more information about the events CHIPS Alliance and its members participated in:
+The members of CHIPS Alliance join for a variety of reasons. Some organizations join to grow their business. Companies that fall into this group normally offer an open source solution, along with selling support and additional services to interested companies. As an example, Codasip has an open SweRV package that anyone can access, a Pro version with commercial EDA tools, and customization and verification services available upon request.
+Many organizations join CHIPS Alliance to accelerate development of a RTL IP/SoC or software tool. For example, the software tool Verilator and the hardware compiler framework Chisel have benefited from their organizations joining. See slide 4 of the Verilator, Accelerated presentation to see how CHIPS Alliance has benefited the Verilator ecosystem.
+Another reason companies join CHIPS Alliance is to accelerate adoption of IP or software. One such IP is AIB which was brought into CHIPS Alliance by Intel. AIB is a chiplet interconnect and is being adopted by a number of companies. DARPA presented on the benefits of AIB and how chiplets can accelerate SoC development.
+Don’t miss the CHIPS Alliance Spring Workshop on March 30! Learn more and register for free. Sign up for our announcements list to be kept up-to-date on our events. The CHIPS Alliance has seen additional interest from a number of companies, organizations and nonprofits in joining our ecosystem, so we will continue to focus on growing our membership. As development accelerates and more output is generated, we anticipate this will foster even more interest in CHIPS Alliance and its open source solutions.
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+AIB reduces design barriers, costs, and leverages generators to ease development of chiplet-based designs
+SAN FRANCISCO, July 16, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that it has released the Advanced Interface Bus (AIB) version 2.0 draft specification on GitHub. The AIB standard is an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package. AIB is ideal for designing SoCs, FPGAs, SerDes chiplets, high-performance ADC/DAC chiplets, optical networking chiplets and more.
+AIB 2.0 has more than six times the edge bandwidth density of AIB 1.0 through increases in the per-wire line rate and the number of IOs per channel. Additionally, with smaller microbumps AIB 2.0 can use as little as half of the current microbump array area. AIB makes it easier for designers to connect chiplets so companies can mix foundries, process nodes, IP sources, etc. for more flexibility in designing highly-integrated semiconductor devices.
+“The AIB 2.0 draft standard continues the CHIPS Alliance’s efforts to provide comprehensive design resources to simplify hardware design and reduce development costs,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “As companies increasingly rely on chiplets to keep up with the latest computing requirements and workloads for different applications, AIB will make it easier to integrate silicon IP with other chiplets into a single device to deliver new levels of functionality and optimization.”
+The CHIPS Alliance and its members are working together to help foster the growth of an industry ecosystem which engenders more device innovation via heterogeneous integration. With broader adoption and support for AIB-enabled chiplets, developers can go beyond the limits of traditional monolithic semiconductor manufacturing to leverage the ideal process node for each function in their design while lowering development costs. The AIB specification is already in use by leading semiconductor companies, and has also been adopted by DARPA’s Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program.
+To further reduce the design effort of producing block variants and porting custom blocks to a new process, Blue Cheetah Analog Design, Inc. has developed agile, process portable, and parameterizable generators for the AIB die-to-die interface. Blue Cheetah’s AIB PHY Generator enables the rapid generation of sign-off ready AIB custom blocks (i.e. netlist, GDS, LEF, LIB, and behavioral models) across a multitude of process design kits (PDKs).
+“Reducing barriers to entry in developing custom silicon will be critical for the growth, adoption, and success of the chiplet movement,” said Dr. Krishna Settaluri, CEO, Blue Cheetah Analog Design. “By producing custom blocks at push-button speed, Blue Cheetah’s generators drastically reduce time-to-market and engineering effort required to produce tape-out ready IP. We are excited to offer this capability and look forward to enabling companies to thrive in the chiplet ecosystem.”
+Dr. Settaluri of Blue Cheetah and David Kehlet of Intel® Corporation will be discussing the AIB PHY generator and AIB 2.0 draft specification at DAC 2020, which is being held virtually this year. The session, called “Tutorial 10 Part 1: Chiplet Integration: Tools, Methodology, Requirement, Infrastructure,” will take place on Monday, July 20 at 1:30 p.m. PT. To learn more about the talk, please visit here.
+To read the AIB specification, please visit: https://github.com/chipsalliance/AIB-specification.
+To check out the AIB PHY Generator, please visit: https://github.com/chipsalliance/aib-phy-generator.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
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+The company also tops MLPerf Tiny v0.7 Benchmark with its IOT processor
+Hangzhou, China, April 20, 2022 – Alibaba Cloud, the digital technologies and intelligence backbone of Alibaba Group, announced it has made further progress in porting basic Android functions onto the RISC-V instruction-set architecture (ISA). This proves the feasibility of using RISC-V based Android devices in scenarios ranging from multimedia to signal processing, device interconnection, and artificial intelligence.
+Last year, the company reported it had successfully ported basic functions like chrome browsing in Android 10. Since the initial porting trial, further effort has been invested to rebase previous engineering on Android 12 to enable third-party vendor modules to facilitate new functions, including audio and video playback, WiFi and Bluetooth, as well as camera operation.
+To better facilitate these new functions, Alibaba Cloud has also enabled more system enhancement features such as core tool sets, third-party libraries and SoC board support package on RISC-V, further improving the robustness of the RISC-V ecosystem when running on the Android software stack.
+In addition, Alibaba Cloud successfully trialed the TensorFlow Lite models on RISC-V, supporting AI functions like image and audio classification and Optical Character Recognition (OCR), a development that helps accelerate the incorporation of RISC-V into smart devices.
+“The support of Android12, vendor modules and the AI framework on RISC-V based devices is another major milestone that we have achieved,” said Jianyi Meng, Senior Director at Alibaba. “We look forward to further contributing to the RISC-V community with our advanced technology and resources, and encouraging more innovation in the community together with global developers.”
+Meng added Alibaba Cloud will open the source codes of related technologies in the near future.
+Alibaba Cloud Tops MLPerf Tiny v0.7 Benchmark
+Earlier this month, Alibaba Cloud’s Xuantie C906 processor attained firsts in the most recent findings from MLPerf Tiny v0.7, an AI benchmark focusing on IOT devices. The Xuantie C906’s performance excelled in all four core categories – visual wake words, image classifications, keyword spotting, and anomaly detection. The Xuantie C906 is Alibaba’s custom-built processor based on the RISC-V instruction-set architecture.
+Xuantie C906’s remarkable performance marks a milestone that showcases the potential of the RISC-V framework in achieving tailored AI functions with extremely low computing power.
+The breakthrough performance in the AIoT area is driven by Alibaba Cloud’s innovation across hardware and software layers. Alibaba Cloud has improved the computing efficiency by using SinianML, a model optimiser, the Heterogeneous Honey Badger (HHB), the neural network model deployment toolset designed for the RISC-V architecture, and CSI-NN2, the optimised neural network operator library. In addition, Alibaba’s software stack, along with the hardware toolset and library, has optimised AI operators and further improved the performance of the AI inference model, resulting in the Xuantie C906’sexceptional performance.
+Alibaba Cloud’s RISC-V based processors have already been deployed widely across a range of applications including smart home appliances, automotive environments and edge computing. Last year, Alibaba Cloud opened the source code of its XuanTie IP Core series, enabling developers to access the codes on Github and the Open Chip Community in order to build prototype chips of their own, which can be customised for IoT applications such as networking, gateway and edge servers.
+Launched by the open engineering consortium MLCommons, MLPerf™ Tiny benchmark measures how quickly a trained neural network can process new data for the lowest power devices and smallest form factors. MLPerf Tiny v0.7 is the organisation’s second inference benchmark suite that targets machine learning use cases on embedded devices.
+“AI for IoT is a highly competitive arena where customisation at every level is critical to achieve new breakthrough results at very low power” said Calista Redmond, CEO of RISC-V International. “Alibaba continues to build RISC-V industry leadership in parallel with their dedication and contribution to the global RISC-V community.”
+“The flexibility of the RISC-V’s framework gives it an advantage in meeting the customisation demands of clients in the AIoT field. We will continue to drive innovation among the thriving RISC-V community, and assist global developers to build their own RISC-V-based chips in a much more cost-effective way,” said Meng.
+
+
+This post was originally published at Antmicro.
+We are excited to announce the ARVSOM – Antmicro’s fully open source, RISC-V-based system-on-module featuring the StarFive 71×0 SoC. Using the RISC-V architecture, which Antmicro has been heavily involved in since the early days as a Founding Member of RISC-V International, the SoM is going to enable unprecedented openness, reusability and functionality across different verticals.
+We are excited to announce the ARVSOM – Antmicro’s fully open source, RISC-V-based system-on-module featuring the StarFive 71×0 SoC. Using the RISC-V architecture, which Antmicro has been heavily involved in since the early days as a Founding Member of RISC-V International, the SoM is going to enable unprecedented openness, reusability and functionality across different verticals.
+
Since its conception, Antmicro has been enabling its customers to tap into the technological freedom that is inherent in open source. We’ve been developing cutting-edge industrial and edge AI systems using vendor-neutral and customizable solutions as well as actively developing and contributing to the tooling ecosystem, improving processes and unlocking even more system design options – often in alignment with our efforts driving RISC-V International and CHIPS Alliance. Targeted at a range of different use cases and enabling unmatched flexibility, ARVSOM is the latest product and example of Antmicro’s expertise in creating practical and easily modifiable technologies using open source.
+Sitting at the heart of ARVSOM is the StarFive 71×0 system-on-chip – the first Linux-capable RISC-V SoC that is intended for mainstream, general-purpose edge applications and is expected to be used in millions of devices to be built on the open source RISC-V ISA. The SoC is also used in the BeagleV StarLight development platform (GitHub repo) which has just been shipped to beta users, including Antmicro, who will be verifying its robustness and reliability in real life use cases, while the development community focuses on further expanding the RISC-V software support. The SoC features a dual core U74 CPU from our partner and RISC-V pioneer SiFive, two AI accelerators: the open source NVDLA and SiFive’s Neural Network Engine, 1 MIPI DSI and 2 MIPI CSI interfaces, HDMI, Gigabit Ethernet, dual ISP, USB 3.0, while the production version of the SoC to be released later in the year will also have PCI Express.
+The SoM will be compatible with our server-oriented Scalenode platform, released earlier this month, originally designed as a baseboard for the Raspberry Pi 4 Compute Module. Used together, Scalenode and ARVSOM will enable building easily scalable and flexible infrastructures consisting of clusters of small RISC-V-based compute units, with as many as 18 Scalenode boards fitting in a 1U rack. ARVSOM will also work with other Raspberry Pi CM 4 baseboards, opening the door to a host of solutions and custom devices to be built with it right away.
+
You can already start software development with our ARVSOM and the BeagleV StarLight SBC thanks to support in Renode, our open source simulation framework. The two have joined an array of platforms and sensors that can be simulated in our open source framework for system development and testing. You can freely co-develop hardware and software in Renode’s virtual environment, with the code behaving exactly the way it would on real hardware. Renode can also be used throughout the development lifecycle to enable continuous testing and integration, as well as prototyping new solutions based on RISC-V, as it features extensive support of this open source ISA. You can read more about the latest updates in Renode in the version 1.12 announcement blog note.
+Our SoM is in development and will be gradually unveiled throughout the year with the increasing StarFive 71×0 SoC availability.
+ARVSOM can be customized and integrated into your project. We have been helping our customers embrace the groundbreaking RISC-V architecture and enable them to reap the benefits of having an advanced system based on vendor-neutral, future-proof and robust technologies. Get in touch with us at contact@antmicro.com if you need a modern product that you have full control over.
+
+
+This post was originally published at Antmicro.
+With the recent advances in open source ASIC development tools such as Verible, it has become easier to automate tasks and boost developer productivity. The Verible linter is a static code analysis tool that has been helping us and our collaborators to spot and fix stylistic errors and bugs in SystemVerilog code.
+As part of our work within the newly established CHIPS Alliance SystemVerilog subgroup, Antmicro has made further steps to facilitate SystemVerilog workflows with Verible, by providing an easy to use Verible Linter GitHub Action. Combined with another open source tool called Reviewdog, the action allows you to easily perform automatic code style checks and code review.
+
Using it is as easy as adding a few lines to a workflow in the .github/workflows directory. For basic usage, just add the action with a github_token parameter to your current workflow:
- uses: chipsalliance/verible-linter-action@main
+with:
+github_token: ${{ secrets.GITHUB_TOKEN }}
+For a more tailor-made setup, it is easy to configure the action by:
+--conf-file option of the linter,With this straightforward solution, any GitHub-hosted open-source or private project can inform commiters about the issues detected in their code, as you can see in the picture below. Of course, creating similar setups in private installations and other repository systems is also possible, and Antmicro offers the services to develop the necessary tooling, integrations and provide support and guidance.
+
The action uses a GitHub Token assigned to every workflow run individually. There’s no need to create personal access tokens, and you can use it in any repository, no matter if it uses a public, private, or enterprise plan.
+Developers can discuss each problem separately, by creating responses to the comments made by the GitHub Actions bot. Marking a conversation as resolved will let others know that the issue has already been taken care of.
+If, instead of automatic code review, you wish to have a log with all the issues, you can omit the github_token parameter. You can see the setup in action on the Ibex RISC-V Core used by the OpenTitan project below:
+
Software developers have been using such automated solutions to facilitate cross-team and cross-company collaboration, taking away the daily pains of coordinating between large teams while improving the ability to detect faults early. Instant, targeted feedback helps both the committers and the reviewers.
+Working together with Google and other CHIPS Alliance members we are making the benefits of automated, software-driven development in distributed environments and the cloud available to hardware developers. A wide range of applications for the Verible linter action can be devised, from faster pull requests reviews, to isolating erroneous portions of code.
+We’re working on adding this action to the Ibex repository. The next step will be preparing a GitHub Action with the Verible formatter, which will allow to not only find problems but automatically suggest changes.
+
+
+Come learn about open source hardware and CHIPS Alliance at next week’s 59th Design Automation Conference in San Francisco. We will be at kiosk 2344 in the RISC-V pavilion. You can also here out talk at 12:30 Monday in the Open Source Central Theatre (booth 2338). We are also in a DAC Pavilion Panel: Is Democratization of Chip Design Already Happening? at 2:30 on Monday. Look forward to an exciting day in SF!
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+SAN FRANCISCO, Nov. 7, 2019 — CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced the creation of Interconnects, Rocket and Chisel workgroups. In addition, a November verification workshop in Munich and a Chisel conference in January will be held giving engineers an opportunity to learn about open source development efforts in CHIPS Alliance. Lastly, the CHIPS Alliance toolchain and cores workgroups have made contributions to open source development tools.
+CHIPS Alliance is the project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code and software development tools relevant to the design of open source CPUs, RISC-V-based SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.
+The Open Source Design Verification Workshop in Munich is being held on November 14th and 15th. CHIPS Alliance is hosting the third Chisel Community Conference to be held on January 29-30th in Milpitas, CA. Chisel is a hardware-construction language, hosted in Scala, and is used in both academia and industry to generate RTL for digital hardware. The Chisel community is joining CHIPS Alliance to further accelerate the development of open source hardware and software. Call for papers is open now.
+CHIPS Alliance has also formed three new workgroups, Interconnects, Rocket and Chisel. The Interconnects group will further develop OmniXtendTM and TileLink. These groups will begin work imminently to make key contributions to open development tools and hardware. Go to www.chipsalliance.org to learn more or join a workgroup. In addition, the Cores and Toolchain workgroups have completed the following milestones
+“The rest of the developer team and I are very excited for Chisel to move to its new home in CHIPS Alliance. Now with open-source industry backing, Chisel is primed to continue growing its user base, adding new features, and stabilizing its infrastructure and ecosystem for industry applications.” – Adam Izraelevitz, PhD candidate at UC Berkeley and a lead developer of the Chisel ecosystem.
+“We want to personally thank Olof Kindgren, Wilson Snyder and Stefan Wallentowitz for their key contribution to open source software development. These extraordinary individuals were vital to achieving these milestones. We look forward to further participation in CHIPS Alliance to facilitate the adoption of open architectures,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital.
+“Antmicro firmly believes in CHIPS Alliance’s vision of fully open tools and workflows as a foundation of an open ecosystem.”, said Michael Gielda, Chair of Marketing, CHIPS Alliance, VP Business Development at Antmicro, “Our work with open source simulation and verification, as well as production-grade SystemVerilog support in open source tooling relies on a collaborative environment where common milestones can be achieved faster.”
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
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+Industry veteran to lead open hardware consortium democratizing silicon innovation
+SAN FRANCISCO, Feb. 8, 2021 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced the appointment of Rob Mains as the organization’s new executive director.
+Rob has over 35 years of experience in software engineering and development, with 25 years of experience as an EDA software architect focused on microprocessor design and advanced process node technologies. He most recently served as a technology advisor at Spillbox, and prior to that worked in leadership and senior engineering roles at Qualcomm, Sun Microsystems (staying on at Oracle after the acquisition) and IBM. Throughout his career, Rob has worked closely with hardware developers to play a hands-on role in helping to devise innovative solutions for a wide range of applications.
+“Rob is an ideal fit for the CHIPS Alliance with his strong leadership experience and deep understanding of the silicon industry,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “As the CHIPS Alliance runs full steam ahead with its growing membership, impressive technical milestones and other activities, we look forward to having Rob on board to continue this strong momentum.”
+“As more companies are looking to open source solutions to help eliminate design barriers, reduce costs and speed up development time, the CHIPS Alliance will play a critical role in advancing open hardware for the benefit of everyone,” said Mains. “I look forward to working closely with CHIPS Alliance members to continue the organization’s goals, while also focusing on growing the membership base.”
+Today the CHIPS Alliance has more than 25 members collaborating to accelerate the creation and deployment of open system-on-chips (SoCs), peripherals and software development tools for a wide range of applications. To learn more, check out the CHIPS Alliance 2020 Annual Report: https://chipsalliance.org/chips-alliance-2020-annual-report/.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
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+Imperas and Metrics joining CHIPS Alliance to help drive the verification of RISC-V Open ISA implementations
+SAN FRANCISCO – June 18, 2019 – CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Imperas and Metrics are joining the organization and the Verification Working Group. Imperas is an independent provider of processor simulation technology and tools for virtual platforms and +analysis tools for multicore SoC software development. Metrics leads the cloud-based solutions for SoC designers with hardware simulation for both design management flexibility and on-demand capacity. The CHIPS Alliance welcomes Imperas and Metrics among its current members Antmicro, Esperanto Technologies, Google, SiFive, Western Digital.
+CHIPS Alliance is a project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications. The CHIPS Alliance project hosts and curates high-quality open source Register Transfer Level (RTL) code relevant to the design of open source CPUs, RISC-V- based SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.
+Imperas provides reference processor models for verification of processors and SoC’s and will be contributing to the CHIPS Alliance working group on verification. Planned contributions will include enhanced interfaces and design flow methodologies to the riscvOVPsim ISS (Instruction Set Simulator) for RISC-V processor IP verification and compliance. riscvOVPsim is free and available for download on GitHub as part of the latest RISC-V compliance test suite and framework, available on GitHub at https://github.com/riscv/riscv-compliance
+Metrics is the first cloud platform for ASIC and complex FPGA design verification. The company provides design teams with on-demand simulation resources, a modern continuous integration workflow, a pricing by-the-minute business model and unique development flexibility. Metrics develops innovative products powered by a cross-functional team that includes simulation technologists, IC design verification experts, and modern cloud software developers.
+“Within the RISC-V community and ecosystem Imperas has made many contributions to customer and community projects and also released a free RISC-V reference simulator on GitHub, while Metrics has pioneered a cloud-based approach that enables infinite hardware simulation capacity that changes the nature of semiconductor verification use models,” said +Zvonimir Bandic, senior director of next-generation platforms architecture at Western Digital and Chairman, CHIPS Alliance. “With Imperas joining CHIPS Alliance we welcome their contributions within the verification task group to help the industry wide efforts to ensure quality IP is available to all adopters of RISC-V. Metrics’ contributions to verification +infrastructure will provide a modern approach to RISC-V cores, peripherals, and complex IP block development.”
+“Imperas is pleased to join the CHIPS Alliance and support the continuing efforts to improve verification for all RISC-V implementers and SoC designers,” said Simon Davidmann, CEO of Imperas Software. “Open ISA’s are enabling new approaches and innovations in processor architectures that will require broad community support to address the verification challenges of next generation domain specific optimized devices.”
+“Metrics was founded with an open platform philosophy that has allowed the company to form many valuable relationships that drive next-generation verification approaches,” said Doug Letcher, CEO, Metrics. “In joining CHIPS Alliance, we are excited to help and support industry wide collaborations for verification that are essential for the next generation +of devices.”
+“CHIPS Alliance has seen a tremendous wave of interest and support since it was first announced just a few months ago,” said Ted Marena, Interim Director CHIPS Alliance. “We are pleased to welcome Imperas and Metrics as its latest members and both will be in attendance at the inaugural workshop on June 19, 2019 at Google at 111 W. Java Drive, Sunnyvale, Calif.”
+The CHIPS Alliance community includes technology developers and contributors supported by a Board of Directors and a Technical Steering Committee. Its initial plans focus on establishing a curation process aimed at providing the FPGA and chip community access to high-quality, enterprise grade hardware.
+Imperas is revolutionizing the development of embedded software and systems and is the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of +processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.
+Metrics, headquartered in Ottawa, Ontario, Canada, is the first true cloud-based platform for ASIC and complex FPGA Design Verification. The Metrics Platform provides an infinitely scalable design verification workflow together with advanced simulation technology, which reduces infrastructure waste and enables better engineering efficiency. https://metrics.ca/
+Founded in 2000, the Linux Foundation is supported by more than 1,000 members and is the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Linux Foundation’s projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation’s +methodology focuses on leveraging best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, please visit us at linuxfoundation.org.
+
+
+Please join us on December 15 at 8:30 am PT either in person at Google or virtually for a CHIPS technology update featuring many exciting speakers. Details and registration are here: https://events.linuxfoundation.org/chips-biannual-technology-update/
+
+
+All About Circuits recently featured an interview with Ted Marena, Yunsup Lee, Amir Salek, and Zvonimir Bandic, discussing the formation of the CHIPS Alliance, its relationship to the RISC-V Foundation, the CHIPS Alliance’s open development model, and initial open source contributions.
+ +
+
+New workgroup draws support from industry leaders as the open FPGA toolchain matures
+SAN FRANCISCO, Feb. 18, 2022 – CHIPS Alliance, the leading consortium advancing common and open source hardware for interfaces, processors and systems, today established the FOSS Flow For FPGA (F4PGA) Workgroup to drive open source tooling, IP and research efforts for FPGAs.
+FPGA vendors such as Xilinx (now part of AMD) and QuickLogic, industrial FPGA users and contributors such as Google and Antmicro, as well as universities including Brigham Young University, University of Pennsylvania, Princeton University and University of Toronto, can now officially collaborate under the umbrella of the newly launched F4PGA Workgroup.
+“FPGAs are essential for a wide variety of low-latency compute use cases, from telecoms to space applications and beyond. This new F4PGA toolchain will enable a software-driven approach to building FPGA gateware, making code integration easier than ever,” said Rob Mains, General Manager at CHIPS Alliance. “Under the umbrella of the CHIPS Alliance, this workgroup will help unite current FPGA efforts so academia and industry leaders can collaborate on accelerating open FPGA innovation.”
+The initial F4PGA projects are focused around the free and open source FPGA toolchain formerly known as SymbiFlow, as well as the FPGA Interchange Format, which is designed to enable interoperability between open and closed source FPGA toolchains. CHIPS Alliance’s newest member Xilinx, now part of AMD, collaborated with Google and Antmicro to develop the Interchange Format definition and related tools to provide a development standard for the entire FPGA industry. The FPGA Interchange Format allows developers to quickly and easily move from one tool to another, lowering the barriers to entry for the entire supply chain – from FPGA vendors to academics and FPGA users.
+In addition to the work around the FPGA Interchange Format, several CHIPS Alliance members have collaborated on the FPGA tool perf framework. This open FPGA tooling project provides a comprehensive end-to-end FPGA synthesis flow and FPGA performance profiling framework, allowing developers to analyze FPGA designs by looking at metrics such as clock frequency, resource utilization and runtime.
+CHIPS Alliance members have also worked on the development of the FPGA Assembly (FASM) format. The FPGA Assembly (FASM) format is a textual format specifying which FPGA feature should be enabled or disabled; the textual nature of FASM makes it easy to analyze and experiment with in different designs.
+Industry support for open FPGA tools has continued to rise with QuickLogic becoming the first company to fully embrace the open source FPGA toolchain in 2020, and now with Xilinx’ participation in the FPGA Interchange project. The strong support for the F4PGA Workgroup promises to help further accelerate industry adoption across geographies and increase confidence in open source FPGA tooling as a viable option for all types of designs.
+To learn more about the F4PGA Workgroup, please visit: https://chipsalliance.org/workgroups/.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The primary focus is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
+
+SAN FRANCISCO, Oct. 15, 2019 /PRNewswire/ — CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Codasip GmbH and Munich University of Applied Science have joined the CHIPS Alliance. In addition, on November 14–15, CHIPS Alliance will be joining the university for a workshop on open source design verification.
+CHIPS Alliance is a project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code relevant to the design of open source CPUs, RISC-V-based SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.
+Codasip is a leading supplier of configurable RISC-V® embedded processor IP. Codasip provides a portfolio of various RISC-V implementations along with a suite of processor developers tools to allow for rapid core customization, and will contribute to working groups on verification platforms and open cores.
+“Codasip has years of processor development experience and has shown its dedication to open platforms by its contributions to open source compiler and compliance projects. We welcome their participation in the CHIPS Alliance to facilitate the adoption of open architectures,” said Zvonimir Bandić, senior director of next-generation platforms architecture at Western Digital and Chairman, CHIPS Alliance.
+“Codasip is excited to join the CHIPS Alliance and support the community in its efforts to ease the path of adoption of RISC-V processors in leading-edge SOC applications,” said Karel Masařík, CEO of Codasip. “The CHIPS Alliance is the logical next step in providing chip designers more choices when it comes to processor architectures.”
+Munich University of Applied Sciences aims to secure an outstanding position as a university of applied sciences. It recognizes the future demands of society and industry, and is changing with a critical yet open vision for current issues, such as the ongoing digitalization of all areas of life. The university focuses on continuous improvement of quality and on constant development in research, teaching, and continuing education.
+“We strongly believe in open source silicon and design flows,” said Stefan Wallentowitz, professor for computer architecture at MUAS. “We look forward to improving open source verification tools together with innovative companies in that field.”
+In cooperation with Munich University of Applied Science, the CHIPS Alliance is conducting an open source design verification workshop in Munich. The workshop invites contributions from industry, academia and hobbyists as talks or tutorials. Registration is open now for the November 14–15 event.
+Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Munich, Germany, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. For more information about our products and services, visit www.codasip.com.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+Chris Jones, VP of Marketing
+E-mail: jones@codasip.com
+
+SAN FRANCISCO – May 7, 2019 – CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced it is holding its inaugural workshop on June 19, 2019 at Google at 111 W. Java Drive, Sunnyvale, Calif.
+Project details, strategy and roadmaps will be presented by member companies, and attendees will have an opportunity to propose Register Transfer Level (RTL) projects and development flow ideas. The workshop will focus on open source hardware, software tools, RTL development, design verification tools and related topics. The agenda and registration details are available at https://events.linuxfoundation.org/events/chips-alliance-workshop-2019
+“This workshop at Google will kick off CHIPS Alliance hardware RTL development. The organization will discuss the planned projects, what is needed for accelerated open source hardware and key software tools. Attendees will see the potential of CHIPS Alliance and the vision for what we will deliver,” said Dr. Zvonimir Bandic, Western Digital and Chairman of the CHIPS Alliance Foundation.
+“Workshop attendees will learn more about our organization and the open source hardware, verification flows/tools and software we will be developing. Attendees will also have an opportunity to suggest projects and meet with CHIPS Alliance members and the Board of Directors. We look forward to answering questions, discussing ideas and sharing the aspirations of the group,” said Dr. Richard Ho, Google and Board member of the CHIPS Alliance Foundation.
+CHIPS Alliance members include Antmicro, Esperanto Technologies, Google, SiFive and Western Digital. The Alliance is a collaborative forum designed to accelerate the creation and deployment of more efficient and flexible CPUs, SoCs and complex peripherals for FPGAs and custom silicon. It is supported by a Board of Directors and a Technical Steering Committee.
+Founded in 2000, the Linux Foundation is supported by more than 1,000 members and is the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Linux Foundation’s projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation’s methodology focuses on leveraging best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, please visit us at linuxfoundation.org.
+
+
+CHIPS Alliance continues to grow with more than 25 companies collaborating on open source hardware and software technologies
+SAN FRANCISCO, Feb. 11, 2021 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today welcomed Antmicro and VeriSilicon to the company’s Platinum membership level. Antmicro, one of the initial members of the CHIPS Alliance, has upgraded to the Platinum membership level to reflect its deepening involvement in the organization. VeriSilicon is new to the CHIPS Alliance, although the company is heavily involved in open source activities.
+“Over the past few years, Antmicro has continued to become more involved in the CHIPS Alliance, helping to steer the technical deliverables and strategic direction of this important organization,” said Michael Gielda, VP Business Development at Antmicro. “We’re deeply committed to furthering the goals of the CHIPS Alliance to realize the vision of open source RTL designs and tooling for silicon and FPGAs.”
+In addition to his role at Antmicro, Gielda is Chair of Outreach at the CHIPS Alliance, helping to drive the marketing, educational and community activities of the organization. Antmicro provides development and commercial support services for open source IP, systems and tools, actively participating in a number of other open source projects and initiatives including RISC-V International, OpenPOWER Foundation, Renode and Zephyr Project. Antmicro is also propelling many of CHIPS Alliance efforts like open source SystemVerilog support and FPGA & ASIC tooling.
+Said Wayne Dai, President and CEO at VeriSilicon: “We have been impressed by the momentum the CHIPS Alliance community has generated over the past two years, and we look forward to helping to drive its next phase of growth and development by joining as a Platinum member.”
+In 2018, VeriSilicon was instrumental in establishing the China RISC-V Industry Consortium (CRVIC), which has more than 120 members today. VeriSilicon is also a member of RISC-V International, and is eager to expand its open source efforts by joining the CHIPS Alliance. With the company’s strong growth over the past two decades, the company recently celebrated a new milestone with its entry to the Sci-Tech Innovation Board (STAR Market) of the Shanghai Stock Exchange in China.
+“The addition of Antmicro and VeriSilicon to our Platinum membership level demonstrates the growing commitment we’re seeing from companies across the silicon ecosystem,” said Rob Mains, Executive Director at CHIPS Alliance. “As we continue to expand our membership base, we remain laser focused on targeting other parts of ASICs beyond the CPU core, open sourcing the tools needed to work with ASICs, and providing real, battle-proven reference implementations and project infrastructure.”
+As Platinum members, Antmicro and VeriSilicon are entitled to appoint a representative to the Governing Board and any Committee. Additionally, a representative of each Platinum member company is eligible to be elected Chair and/or Vice Chair of the Technical Steering Committee (the “TSC”). Furthermore, Platinum members get ten complimentary registrations for CHIPS Alliance workshops and events during the year of membership, along with each company’s logo prominently displayed in CHIPS Alliance online and print materials.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
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+Mentor to present at the virtual CHIPS Alliance Workshop on Sept. 17
+SAN FRANCISCO, Aug. 18, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Mentor, a Siemens business, has joined as its newest member. The CHIPS Alliance has a roster of more than 20 members collaborating to accelerate the creation and deployment of open system-on-chips (SoCs), peripherals and software tools for a wide range of applications.
+“Mentor has a long history of supporting open standards to enable companies to design and verify their solutions,” said Badru Agarwala, general manager of Digital Design and Implementation Solutions at Mentor. “High level synthesis plays an important role in the design of accelerators, and in fostering an open and collaborative hardware development ecosystem. We look forward to contributing to the CHIPS Alliance’s efforts to reduce design barriers for the benefit of the entire silicon ecosystem.”
+Mentor is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. The company recently collaborated with another CHIPS Alliance member, Imperas Software, to extend the hardware design verification of RISC-V cores with industrial quality coverage methodologies. Mentor’s high level synthesis (HLS) tool, Catapult, enables hardware designers to use C++ or SystemC to describe functional intent and move up to a more productive abstraction level.
+“Over the past year we’ve focused on expanding our membership base and achieving new technical milestones as we work to make open source silicon a reality for mobile, computing, consumer electronics and Internet of Things applications,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “We’re pleased to welcome Mentor to this dynamic, collaborative community driving the new era of hardware innovation.”
+Mentor will be presenting at the CHIPS Alliance Workshop, being held virtually on Thursday, Sept. 17. Mentor’s Anoop Saha will be presenting the session “Open ML Accelerator.”
+To see the full CHIPS Alliance Workshop schedule and register for the event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.
+To learn more about CHIPS Alliance’s work, please check out the 2020 Annual Report: https://chipsalliance.org/chips-alliance-2020-annual-report/.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+Note: A list of relevant Siemens trademarks can be found here.
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+SAN FRANCISCO, December 13, 2022 – CHIPS Alliance, a Linux Foundation project and leading consortium advancing common and open hardware for interfaces, processors and systems, announced that Caliptra, the open source root of trust project founded by technology leaders AMD, Google, Microsoft and NVIDIA, has joined CHIPS Alliance to enable an open, collaborative community-driven approach to hardware security.
+Caliptra is a new specification for an open source silicon root of trust (RoT) designed to meet the enhanced security requirements of modern edge and confidential computing workloads. CHIPS Alliance will oversee the open source implementation of register-transfer level (RTL) code for Caliptra that can be synthesized into current SoC designs, along with the verification suite and firmware. As part of this architecture, the open source RISC-V core hosted by the CHIPS Alliance and now relaunched as VeeR, is embedded within the Caliptra Root of Trust macro. VeeR is a true open source RISC-V core family with full RTL and verification bench all under Apache 2.0 license ready for anyone to use.
+Having joined CHIPS Alliance, Caliptra will form its governance under the CHIPS Alliance Technical Steering Committee in accordance with the project’s charter, while the Caliptra hardware specification is hosted in the Open Compute Project, in a collaboration that will further tighten the bond between the CHIPS Alliance and the OCP. .
+“By pushing for introducing transparency into hardware security, Caliptra’s aim coincides with that of CHIPS Alliance”, said Rob Mains, General Manager at CHIPS Alliance. “CHIPS is actively encouraging collaboration with industry, universities and individuals to build a strong open source hardware ecosystem, comprised of IP, design, EDA, and PDK’s. Caliptra is a strong addition to the overall endeavors of CHIPS, and helps further the goals of CHIPS.”
+CHIPS Alliance is proud to announce that, in addition to Google and AMD which were already members related to other open source initiatives they are pursuing with CHIPS Alliance, Microsoft and NVIDIA have now also joined as Platinum and Silver members, respectively.
+“Google is delighted to have Caliptra join the CHIPS Alliance and see it host the open source project, including RTL and firmware,” said Partha Ranganathan, Vice President and Technical Fellow, Google. “Furthermore, we are proud to welcome AMD, Nvidia and Microsoft as members of CHIPS Alliance and work together to drive further open source collaboration and raise the security bar in the broader Cloud industry.”
+Ensuring the security of our data centers and electronic devices is critical to all of us in the industry. Having a collaborative platform to bring the best minds to complex security problems and addressing real world threats is of paramount importance. The work done within CHIPS is all under an Apache 2.0 license, which encourages collaboration and usage of the intellectual property hosted by CHIPS.
+CHIPS Alliance welcomes all to join and participate in its different workgroups that covers a broad range of silicon design topics including: implementation, verification, process design kits, electronic design automation, and FPGAs to name a few. Please visit the CHIPS website at:
+https://chipsalliance.org/join for more information.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The primary focus is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+At the core of the Open Compute Project (OCP) Community are hyperscale data center operators and industry players, joined by telecom, colocation providers and enterprise IT users, working with vendors to develop and commercialize open innovations that, when embedded in product are deployed from the cloud to the edge. The OCP Foundation is responsible for fostering, serving and seeding the OCP Community to develop new open solutions that can meet the market and shape the future. In shaping the future, OCP will continue to invest in strategic initiatives that prepare the IT ecosystem for major changes, such as AI & ML, optics, sustainable data center solutions, advanced power management and cooling techniques, composable silicon and sustainability. Learn more at www.opencompute.org.
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+It’s been just over a year since the CHIPS Alliance was founded with the mission of making open source hardware development more accessible to companies, universities and individuals. We’re working to bring the dynamics of the hugely successful open source software development model into ASIC design, building on the groundwork set by the RISC-V community. Progress over the past year is detailed in our Annual Report.
+CHIPS Alliance is focused on expanding on this open hardware vision by:
+With these three pillars guiding our efforts, we believe that the CHIPS Alliance will enable truly open hardware to flourish for the first time. The CHIPS Alliance has already made incredible progress so far. We have achieved a number of important technical milestones, including announcing newly enhanced SweRV Cores – EH2 and EL2 – and releasing the Advanced Interface Bus (AIB) specification and reference implementations by one of the CHIPS Alliance’s newest members, Intel. These technical accomplishments are making it easier for engineers to design innovative embedded applications for the latest computing requirements.
+We’re also excited by the significant community interest in the work we’re doing. Hundreds of people from around the world have attended CHIPS Alliance events over the past year, both in-person and online, and our working groups are running full steam ahead. Check out our Annual Report to learn more about the CHIPS Alliance’s news and activities, and stay up to date by following us on Twitter and LinkedIn.
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+This post was originally published at Antmicro.
+Antmicro’s open source work spans all parts of the computing stack, from software and AI, to PCBs, FPGAs and, most recently, custom silicon. We connect those areas with an overarching vision of open source tooling and methodology, and a software-driven approach that allows us to move fast and build future-centric solutions. Our partners and customers, many of whom work with us also in the context of organizations such as CHIPS Alliance and RISC-V, share our approach to developing open systems. We were recently very happy to be invited to give a talk at the “Production grade, open RISC-V SweRV Core Solutions in CHIPS Alliance” meetup organized by Western Digital where we presented our systems approach on the example of the open source tools ecosystem that targets their SweRV cores and which we are helping to develop.
+SweRV is a family of production-grade RISC-V implementations originally developed by Western Digital, who have announced they are going to transition 2 billion cores in their products to RISC-V, showing they are fully committed to this open processor architecture. SweRV comes in three variants: the original EH1 and the recently released EH2 and EL2.
+EH2 is the world’s first dual-threaded commercial, embedded RISC-V core designed for IoT and AI systems, boasting as much as 6.3 CoreMark/MHz in dual-threaded mode, at 1.2 GHz in 16nm. EL2, on the other hand, is a tiny, low-power but high-performance RISC-V core (with just 0.023 mm2 in 16nm, it runs at up to 600 MHz and 3.6 CoreMark/MHz) targeting applications such as state-machine sequencers and waveform generators. The best thing about them is that anybody can use and extend them for free, with more high performance cores being planned in the future.
+But a CPU is as good as the tooling around it and Western Digital knows it. That is why the entire SweRV family was handed over to CHIPS Alliance, which now aims to facilitate using the cores in practical scenarios by maintaining the dynamic ecosystem of relevant tools. Many of the necessary building blocks are already in place, while others are still being developed with active participation of Antmicro, the FOSSi community and others. In this article you will see examples of how you can work with SweRV in simulation, on an FPGA and in an ASIC context.
+To get started very quickly with no hardware whatsoever, you can simulate any of the SweRV cores in Verilator – one of the most successful and widely used open source projects in the EDA space, which we use extensively. Simply, go to the relevant core’s GitHub space in the CHIPS Alliance organization (e.g. https://github.com/chipsalliance/Cores-SweRV for EH1) and simulate the RTL (which is written in SystemVerilog).
+Verilator simulates the RTL with high performance by compiling to an optimized model and running it, outperforming many proprietary alternatives. What is more, it is developing very fast thanks to the work of its maintainer – Wilson Snyder, the FOSSI community and CHIPS Alliance. Antmicro specifically has been working together with Western Digital and Google on adding support for SystemVerilog / Universal Verification Methodology to enable Verilator’s design verification for real-world use cases (see Looking into the future below).
+If you want to get working on something more tangible, you might want to run SweRV on an FPGA – in a portable, vendor-neutral manner, of course.
+To simplify interfacing with various toolchains, simulators and other tools you might need depending on the platform you want to target, you can use Edalize – a Python utility that allows you to seamlessly work with different kinds of EDA tools, both for FPGA and ASIC design. It helps you to maintain consistent workflows and pinpoint whether a specific bug is tool-related or pertains to your code. We’ve been adding quite a lot of new functionalities into Edalize recently, while using it heavily as a default way to interface with various tools out there in our work e.g. sv-tests (again, see Looking into the future for more on that topic).
+Edalize will help you use your SweRV-based design on the FPGA/board of your choice without having to care about remembering and maintaining specific configurations and runtime flags.
+Another great tool from the same author is FuseSoC, a Python-based package manager and a set of build tools for HDL code. It enables you to reuse your FPGA IP across many designs and, of course, it supports SweRV cores well. Apart from making it simple to reuse existing cores, it allows you to easily create compile-time or run-time configurations, port designs to new targets, set up configurable Continuous Integration as well as let other projects use your code. FuseSoC is also used by the SweRVolf SoC.
+Thanks to integrations with other open source tools like Google’s Verible linter/formatter, that we’re also helping to develop, FuseSoC can be used to lint and format System Verilog – we have recently written an article about this.
+A core alone, however, is not enough to get any practical work done. If you want to build a System-on-Chip, you should definitely look at LiteX – a SoC generator that allows you to put SweRV in an actual use case. LiteX is an IP library and a SoC builder that is portable between various FPGAs and can turn SweRV into a full blown system. It has a number of IPs and other building blocks such as Ethernet, RAM, UART, SATA, etc. which you can configure to work with different kinds of CPUs. It has initial SweRV support which enables the user to quickly build plug & play SoC systems with SweRV. Antmicro is heavily involved in work to build a robust ecosystem around it. LiteX can run the Zephyr RTOS – which is also supported on SweRV – and, with a suitable CPU, it can run Linux as well. The LiteX SoC ecosystem can also be used together with another tooling project we heavily contribute to, SymbiFlow – the open source FPGA flow.
+If you want to use SweRV to build a full production system and leverage the flexibility to customize that comes with the RISC-V and open tooling, you will most likely need to experiment with the architecture and co-develop hardware and software. This is where Renode can be of immense use thanks to its architectural exploration, simulation, testing and debug capabilities for complex systems: entire SoCs, boards and systems of boards. All you need to do is download Renode and put together a few configuration files – it even comes with many demos and pre-compiled examples for various platforms. Renode provides initial support for SweRV EH1 (with more to come) as well as extensive support of LiteX, which will let you quickly build and simulate entire open source SoCs. On top of that, Renode enables hardware/software co-simulation with Verilator for building your custom IP and testing its HDL as-is, while keeping the rest of the system simulated in Renode to save development time.
+Assuming SweRV fits your use case, you may eventually want to build and verify a production-grade ASIC which includes one of those CPUs. As part of the CHIPS working groups focused on cores and tools, the developers of SweRV in collaboration with Google, Antmicro and others are building an entirely open source design verification ecosystem around the cores family, including projects such as riscv-dv and Whisper ISS. The former is an entire SV/UVM flow based on an instruction generator for RISC-V processor verification, which allows you to perform various tests on SweRV-based designs. It features a number of test suites dedicated to different functionalities. It runs ISS and RTL simulators in tandem and compares the results. Whisper ISS is a tool used for verification of SweRV implementations, which can be run in an interactive mode, allowing the user to single step RISC-V code and inspect/modify the RISC-V registers or system memory, or it can be run in lock-step, e.g. with Verilator.
+There is ongoing work from CHIPS Alliance and the broader open source community to rapidly transform the ASIC-development workflows to fully embrace open source. One such effort is sv-tests, a System Verilog test suite designed to stress-test different kinds of designs in SystemVerilog against various open source tools, showing a results table indicating detailed coverage. SweRV, being written in SystemVerilog, is of course one of the suite’s test targets.
+The SV test suite informs some of our ongoing open source work for ASIC tooling, one of the goals of which is to enable open source development and verification of System Verilog designs. An interesting tool to look at in this space is Surelog – a full-blown SystemVerilog parser developed in collaboration between Google and Antmicro oriented at simulation and UVM. We are working to plug it as the System Verilog front-end into various open source tools using a framework called UHDM (Universal Hardware Data Model), which will enable code reuse between various tools with similar needs.
+With the recent release of the world’s first open PDK, that we are proud to have been participating in, and the progress being made in the OpenROAD project, which aims at a fully open flow for chip design and other areas, it looks like the future in which a SweRV based SoC can be designed, verified and manufactured using open tools is not that far off.
+Apart from being an expanding, production-grade family of cores, SweRV taps into a very good and dynamic ecosystem of tools that we are helping to build. CHIPS Alliance is aiming to revolutionize the way developers work with ASICs and FPGAs by enabling a software-driven approach to silicon, which perfectly aligns with Antmicro’s strategy and long-term objectives. With extensive experience in RISC-V-powered open source work, we offer high-quality services that our customers can use to build on top of SweRV using these new collaborative methodologies and tools. Reach out to Antmicro at contact@antmicro.com to find out how the company can assist you with your next RISC-V-centered project.
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+This post was originally published at Antmicro.
+UVM is a verification methodology traditionally used in chip design which has historically been missing from the open source landscape of verification-focused tooling. While new, open source approaches to verification have emerged that include the excellent Python-based Cocotb (that we also use and support) maintained by FOSSi Foundation, not everyone can easily adopt it, especially in long-running projects and existing codebases that use a different verification approach. Leading the efforts towards comprehensive UVM / SystemVerilog support in open source tools, we have been gradually completing milestones, getting closer to what will essentially be a modular, collaboration-driven chips design methodology/workflow. Some examples of our activity in this space include enabling open source synthesis and simulation of the Ibex CPU in Verilator/Yosys via UHDM/Surelog, and the most recent joint project with Western Digital in which we have developed dynamic scheduling in Verilator.
+The work is a part of a wider, long-term effort that, besides Western Digital, has involved other fellow CHIPS Alliance members such as Google, to develop UVM / SystemVerilog support in open source tools. To get closer to this goal, this time we have introduced an improvement to Verilator – an open source tool that is great at doing what it was originally designed to do, that is simulating synthesizable code, but hasn’t been enabling its users to convert non-synthesizable code and run fully fledged testbenches written in Verilog/SystemVerilog. The biggest challenge to opening that possibility turned out to be Verilator’s original scheduler running everything sequentially, which in general is not a bad approach but can get you only so far without actually executing the code in parallel.
+
To run proper UVM testbenches in Verilator, we had to be able to properly handle language constructs specifically designed for use in simulation. Those features include delay statements, forks, wait statements and events. To achieve all of this, we needed to add a proof-of-concept dynamic scheduler to Verilator.
+Instead of grouping code blocks of the same type as the original scheduler does, the dynamic scheduler separates the code into many runnable blocks and then creates and spawns a process for each of them (when they are due to be executed). To deal with it we created a new process, which translates to a new high level thread for each initial block, always block, forever block, each block in the fork statement etc. This allows us to pause the execution of one block and continue the execution of other blocks. Blocks can be paused when they encounter simulation control statements like:
+wait (rdy == 1); or wait (event_name.triggered))@event_name;)#10;)join, join_any – join_none is also supported, however it is not used to control the execution per se)All of the statements listed above are not supported in Verilator’s original scheduler, so to be able to dynamically control the execution of those already dynamically spawned sub-processes, a way to react to changes in signal/events states needed to be implemented. We did it by wrapping the primitive types used for storing signal values in objects using higher abstraction levels, which now allows us to attach other processes to monitor values of specific signals and execute an arbitrary callback when a signal changes. Note that this is a mechanism used internally to implement the flow control statements and is not visible to the user writing Verilog code.
+One additional thing that had to be re-written and adapted to the dynamic scheduler was the way non-blocking assignments are handled.
+With a scheduler that is aware of the simulation time and other flow control statements, the same approach originally used by Verilator could not be applied anymore. A way to properly schedule assignments, and execute them in the proper moment was a crucial step in getting all of this to work.
+Note that the features described above are the ones that are immediately visible to users of Verilator with the dynamic scheduler. This is however only the tip of the iceberg when it comes to the amount of internal changes needed to be done in Verilator.
+To present the usage of all the new Verilator features we have created a public GitHub repository with a number of example designs and GitHub Actions-based CI simulating them.
+The examples range from single feature examples to more complex scenarios simulating a system with two UARTs sending data between each other.
+The UART testbench example uses all the newly added features. It spawns a thread for every simulated UART block and each thread feeds the UART IP that is being tested with the predefined data (the “hello world” string in our example).
+The UART block reads the data from an AXI stream interface, serializes it and sends it over the TX line.
+The received data is available on the output AXI Stream bus.
+Each testbench thread introduces a random delay between consecutive data chunk transmission.
+The threads are synchronized using SystemVerilog events – e.g. once the data is fed into the UART block over the AXI stream interface, a thread is triggering an event informing the other part of the thread that the data is being transmitted by the IP. +Once transmission is done, another event is triggered informing the first thread that the IP is ready for a new data chunk.
+Once all the test data is transferred between both tested UART instances, the threads are joined and data correctness is validated.
+This ongoing project is a big step towards UVM support in open tools as it not only removes a number of limitations in this area but also opens the door to future developments – which include a number of SystemVerilog features oriented towards verification which were earlier out of scope since open source UVM verification wasn’t on the horizon. Together with the effort to support SystemVerilog in Verilator using UHDM which is part of another ongoing project, in CHIPS Alliance we continue to work towards enabling open source design verification for everyone, which will revolutionize the way chips are built.
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+Efabless to give a talk on the OpenROAD project at the CHIPS Alliance Workshop on Sept. 17
+SAN FRANCISCO, Sept. 15, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today welcomed Efabless, a crowdsourcing design platform for custom silicon, as its latest member. Efabless is already an active participant in several open source initiatives that the CHIPS Alliance is involved in, including the OpenROAD project and the Open Source Shuttle Program.
+“The mission of the CHIPS Alliance to democratize silicon design nicely aligns with our focus on changing how chip design is done forever. Our platform is essentially an ecosystem-in-a-box that’s instantly accessible to designers anywhere to create and deliver new chip solutions faster than traditional approaches,” said Mohamed Kassem, co-founder and CTO at Efabless. “Through the CHIPS Alliance and other open source initiatives, we’re working to make it easier for design teams of all sizes to define, develop, collaborate and monetize their work.”
+At the CHIPS Alliance Workshop on Thursday, Sept. 17, Kassem and Andrew Kahng of OpenROAD and UCSD will be presenting the session “OpenROAD open RTL-to-GDS update.” The talk will discuss the OpenROAD autonomous and fully open flow for chip design.
+“We’ve been impressed with Efabless’ strong commitment to accelerating open source chip innovation,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “We look forward to working closely with Efabless and our other members to continue to lower the cost of developing IP and tools for hardware development.”
+Efabless is collaborating with SkyWater Technology Foundry and CHIPS Alliance members Google and Antmicro on an open source SkyWater PDK (Process Design Kit) for the 130 nm CMOS process technology. Efabless will make the design for this PDK simple and affordable by integrating resources on its cloud-based design platform including: an open source based end-to-end ASIC design flow – openLANE based on OpenROAD, Yosys and Magic; the open source striVe family of full ASIC reference designs; and a marketplace for monetizing chip and IP designs. This project will help lower the cost of entry for chip manufacturing, making chip design more accessible for everyone.
+Additionally, Efabless is managing the Open Source Shuttle Program sponsored by Google. This program will provide free of cost chip manufacturing runs for open source designs. The first run is scheduled for November 2020, and another will take place in early 2021.
+To check out the schedule for the CHIPS Alliance Workshop and register for this free event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
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+Efabless, a community chip creation platform, today announced the launch of its new chipIgnite program to bring chip design and fabrication to the masses and a collaboration with SkyWater Technology for the first node supported in the program. The chipIgnite program expands upon the SKY130-based open source chip manufacturing program sponsored by Google and supports private commercial designs that include non-open source IP. This initiative represents another step forward in the industry to broaden access to chip design by giving people the ability to more easily create and fabricate chips.
+The first shuttle in the chipIgnite program will support fabrication of student projects as part of the EE272B course in the Electrical Engineering department at Stanford University for senior undergraduate and graduate students.
+The new program also has industry support from organizations including QuickLogic and the CHIPS Alliance.
+“CHIPS Alliance is a major champion of open source hardware design and associated design automation tools. I am excited to see the chipIgnite program offered by Efabless to include many different collaborative IP developers to prove new ideas. The platform alleviates the barriers to entry into chip design and allows for ready exploration of many concepts,” said Rob Mains, general manager of CHIPS Alliance.
+Read the full announcement at Efabless: https://info.efabless.com/press-release-efabless-launches-chipignite-with-skywater-to-bring-chip-creation-to-the-masses/
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+CHIPS Alliance is pleased to see the announcement by Antmicro for its development and contribution to the open source hardware community to provide a easy to use plug-in for any version of Yosys to allow import of System Verilog based designs. This development is made possible by the underlying utilization of the Unified Hardware Data Model (UHDM), a key open source data representation upon which EDA applications can be built. Details can be seen here from Antmicro: https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/
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+One of the most recent projects developed within the workgroup is the unified f4pga CLI tool. In the broader context of our continuous efforts to make the FPGA space more unified and flexible, creating the f4pga CLI tool was a logical next step – it allowed us to wrap the underlying tools into a single CLI, making the F4PGA toolchain a more complete flow. The currently supported architectures are AMD’s (former Xilinx) 7 Series, Lattice’s iCE40 and QuickLogic’s EOS S3. Details are here.
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+This post was originally published at Antmicro.
+Continuous Integration and smart lifecycle management are key for high-tech product development, which is often a complex and multi-faceted process that requires automation to be efficient and failure-proof. At Antmicro, we’ve been creating various open source cloud and hybrid cloud solutions for our customers, helping them to encapsulate the complexity of their software stack. Lots of those projects cross the hardware/software boundary and involve a mix of open source and proprietary code, which means that fine-grained control of the CI setups are needed to make them work.
+To provide the level of flexibility that we and our customers require, we often find ourselves working extensively on the underlying CI infrastructure, building open source solutions that can scale between organizations and teams. One such project involved creating a custom, local GitHub Actions runner, with containerized builds, support for Google’s Build Event Server and workload measurement and analytics; in collaboration with Google we then also enabled running an identical setup with the extra capabilities in Google Cloud.
+
GitHub is the world’s largest open source code sharing space, home to many of our open source projects such as Renode, the open source FPGA toolchain SymbiFlow or our open source ASIC development-focused SystemVerilog work. GitHub Actions – used by millions of developers worldwide – is a natural choice for those projects as the go-to CI flow. However, by default it provides compute resources – in the CI world traditionally called runners – with a specific hardware configuration which does not always fit the needs of the workloads that we deal with.
+Especially in our work that involves ASIC and FPGA development flows – working towards enabling fully open source chip and IP design in our broader work in collaboration with our customers and fellow CHIPS Alliance members such as Google, Western Digital and QuickLogic, we find ourselves needing hybrid setups which would allow us to keep the code as well as the CI definitions public while being able to rely on internal infrastructure to do the heavy lifting. Long-running builds involving tools like VtR or OpenROAD that use lots of memory and CPU power, can greatly benefit from the flexibility that comes with the use of custom, self-hosted runners, and this solution also gives you a high degree of freedom in terms of integrating your runner with external hardware or tools that can’t be shared publicly. The latter is especially helpful in some of our other open source projects for things like benchmarking RISC-V, OpenPOWER and other cores or tracking the QoR for your FPGA designs. The Quality of Results and flexible Continuous Integration elements are extremely important for custom engineering projects we embark on, which typically integrate a variety of open source components together – fortunately the very nature of open source that constitute the predominant part of the tools we use makes such work much easier.
+Our internal and our customers’ needs have called for the ability to integrate on-premise runners into our GitHub CI flows, which can be done using the GitHub runner project. For many of our projects, we provide flexible development infrastructure based on open source that allows us to better collaborate around shared code and to do that, we need to be able to scale compute resources between the private and public cloud. To enable feature parity with some of internal infrastructure, we also extended the self-hosted runners with some extra features.
+Firstly, the custom runners developed as part of the project can be used with our distant-bes framework to push results in the Build Event Server format to custom results viewers transparently to the CI run itself. You can see an example of how this works in the symbiflow-examples repository. Secondly, we modified the runner so that instead of running the CI script on bare metal, it spawns virtual machines and performs the run steps inside them, collects results, and kills the machine, without changing the state of the host system’s kernel. This also allows us to gather performance metrics to see what the real utilization of the runner’s resources is – and we push those results in the form of graphs to our BES server.
+
Lastly, based on the needs of several of our collaborative open source projects with Google, we pursued yet another goal, namely, instantiating our self-hosted runners in Google Cloud, which enables our CI to spin powerful servers up and down on demand. This mix of robust internal infrastructure and always-available, scalable on-demand Google Cloud resources is very useful for heavy workloads run by multiple organizations. In the world of collaborative development in forums like the CHIPS Alliance and RISC-V International, this is no longer a nice-to-have, but a necessity.
+
+
+This post was originally published by Olof Kindgren
+
2020 was a year with a lot of bad news and so it feels slightly strange to cheerfully write about a very specific topic in the light of this. But there will always be good and bad things happening in the world. So let’s keep fighting the bad things and for now take look at what happened last year within the amazing world of open source silicon. I will start by mentioning the most significant, but by no means the only, milestones for the FOSSi movement as a whole and then take a more personal look at the work where I have been directly involved.
+The biggest story within free and open source silicon this year has undoubtly been the openMPW project involving Google, SkyWater Foundries and eFabless together with a number of other collaborators.
+Ever since I got involved in open source silicon ten years ago, building a fully open source ASIC has been one of those big milestones. While we have had FOSSi IP cores taped out on chips for at least 20 years and parts of the flow being managed by open source tools, it has always seemed to be too much work and requiring filling in too many gaps to have a fully open source end-to-end flow to produce ASICs. But, over the years people all over the world have filled in the gaps and done the work bit by bit. Sometimes in the context of overarching programmes to advance open source silicon, sometimes in academic settings, sometimes coming from the industry and sometimes as completely unpaid hobby projects. And this year all these efforts came together, helped by funding, to produce four shuttle runs, each loaded with 40 different completely open source designs. The first of these runs are currently being fabricated, and it will be extremely interesting to see them coming back.
+One of the final pieces in this puzzle was the PDK. And while SkyWater should be rightfully lauded for their decicion to open up their 130nm PDK, it begs to ask the question: Why on Earth did it take this long? What could possibly the fabs have to lose by doing this? What they gain is easy to answer, a completely new market of users who can create chips at their fab. According to people within the project, it’s estimated that 75% of the people on the first shuttle define themselves as software engineers. It’s very likely that none of these people would ever dream of making an ASIC without this possibility. So I kind of feel that making the EDA industry open up their formats is a bit like trying to get your kids to eat vegetables. It’s a lot of groaning and complaining, but was it really all that bad in the end to get some nutritions. Or in the case of ASIC fabs, was it really all that horrible to release your PDK to get some more customers? Let’s just hope this opens up the eyes of more fabs. My, and many others, dream is to eventually see the same thing happening to ASIC fabs as has been happening with cheap PCB services over the past ten years. And using that analogy, I’m quite sure it pays off to be early in the race. So, get started folks!
+The other big thing happening this year is that we finally have an FPGA-vendor shipping an open source toolchain for their devices. The company that will go down in the annals of history for being the first to do this is QuickLogic and their EOS S3 FPGA. This is by no means the first FPGA with an open toolchain, and the QuickLogic-flavored version of SymbiFlow developed by FOSSi veterans Antmicro is based on all this prior work. But it is the first time we see a toolchain being created from the FPGA manufacturer’s specifications rather than being figured out from compiled FPGA binaries and it’s the first toolchain that is supported and funded by the vendor rather than being at best tolerated by them. And again I must ask, why did it take so long for this to happen? If I was running a small FPGA startup with limited resources, I can’t for my life understand why I would want to spend a lot of time and money to build and continouosly maintain a big unwieldy toolchain all by myself instead of adding the required device-specific bits to a known good open source toolchain and share the maintenance burden. If nothing else it would free up resources to build other value-add products on top of the tools. It’s like if every vendor of computer systems would first build their own operating system and compiler before shipping their products. This is what we had in the 80s and abandonded it for very good reasons. Because it made absolutely no one happy. And you know what? I think the users of FPGAs should put more effort into pushing their vendors to support open source toolchains, because it will save everyone a heap of time and money.
+Let me illustrate that last point with an example that actually happened when I was porting SERV to the QuickLogic devices. After synthesis I noticed that it used far more resources than expected. Looking at the synthesis logs I realized the memories in the design weren’t mapped to on-chip SRAM. So I asked the toolchain developers about this. They pointed me to the file in the toolchain that contained the rules for mapping to SRAM. I quickly found a badly tuned parameter, changed it to a more sensible value and ten minutes later it was working fine. An hour later I had submitted a patch back to the toolchain that fixed the problem for everyone else who would encounter it.
+let’s break this down into numbers. Finding the cause of the bug took about 15 minutes. Fixing it, another five. At that point I could use it myself, but after spending another 15 minutes or so, it was also fixed for everyone else.
+Now let’s do the same exercise for a proprietary closed source toolchain. Finding the cause of the bug takes… well…it depends… Let me explain.
+I started my professional career at a company which at that point was the world’s largest FPGA buyer. Whenever we had problems, they flew in two FAEs to sit in our lap, they could provide us with custom internal builds of their tools and generally tried to make sure the problem quickly went away so that we would continue to buy FPGAs from them. However, most companies are not the world’s largest FPGA buyer and does not get this treatment. Instead you will have to wade through layers of support people until you reach someone who is actually qualified enough to acknowledge the issue. I have been in this situation numerous times and would estimate this process usually takes around 2-3 months. Actually fixing the bug probably takes five minutes or so in this case too, but here comes the fun part. In most cases you will now have to wait, I don’t know, a year or so until the fixed bug ends up in a released product that you can download. What happens in practice is that the user tends to find a workaround instead. In the example above, the likely solution would be to instantiate a RAM macro instead of relying on inference. This however doesn’t come for free as it requires finding all the instances where this is a problem, add special handling for this case which results in a larger code base with more options to verify and maintain. This costs time and this costs money. So the moral of this story is that closed source tools are more expensive for everyone involved and users of FPGAs should get better at telling the FPGA vendors that they are done with this closed source nonsense.
+
+The QuickFeather. First FPGA board to ship with a FOSSi toolchain
There are numerous other news and projects that are well worth mentioning, but the above two are milestones that we have been waiting for a long time, so they deserved special attention. And if you want to keep up with the latest happenings in open source silicon, I highly recommend subscribing to the El Correo Libre newsletter which does a fantastic job of providing an overview of what goes on in all corners of the world. So let’s move on to some of my more personal victories that aren’t necessarily mentioned in other people’s year in review.
+When I am working on and talking about open source silicon I am often wearing many hats because I’m associated with several different organizations. Luckily they are all pretty much aligned on this topic which makes things far easier. But these organizations also have different motives and goals so I would like to mention a few words about them here.
+My dayjob is working for Qamcom Research & Technology and also there it has been more FOSSi work than usual, which I think is a good indication that open source silicon is becoming increasingly more common in chip design in general. The year started off by finishing up some work on SweRVolf together with a couple of my Qamcom colleagues. SweRVolf is a project under CHIPS Alliance, an organization that Qamcom has been part of since 2019 to help improve the state for open source and custom silicon. After that I was pulled into a project for doing climate research with a huge radar system. My task here was to handle sub-nanosecond time synchronization between systems located hundreds of miles from each other, using the White Rabbit system developed at CERN. I was pretty excited about getting to know White Rabbit. The timing section at CERN responsible for the White Rabbit project and associated technologies are household names within open source silicon and have a long history here. I know many of the people working there personally and have great respect for their work. But so far I haven’t had the chance until now to actually get down and dirty with the technology. Once my job was done there I moved on to another proprietary project that I can’t discuss here. I do get to use FuseSoC and Verilator though, so it’s fine 🙂
+The hat I tend to wear most when topic revolves around open source silicon is my FOSSi Foundation director hat. And despite doing a lot less of the things we normally spend time on, it turns out we did a lot of other great things instead. I will however not go into more detail here, but instead point to the excellent summary done by my FOSSi Foundation colleague Philipp Wagner.
+Arguably the most well-known project nowadays with ties to open source silicon is RISC-V. My RISC-V ties deepened in the beginning of the year when I was asked to become a RISC-V ambassador. Part of being an ambassador is to create awareness of RISC-V in the fields where I’m active. For well-known reasons the number and nature of events were a bit different from previous years which meant fewer opportunities to weild this new-found power, but I did participate in an ask-the-expert session during the RISC-V global forum and a couple of other events that will be described later. And I also got to be interviewed about RISC-V and open source silicon by Sweden’s largest electronics and tech news outlets as well as the Architecnologia blog.
+
+Current crop of RISC-V Ambassadors; AKA the Twantasic 12
In addition to my day job and participating in different organizations I also run a bunch of open source projects, so let’s take a look at the progress of the most important ones during 2020.
+SweRVolf is an extendable and portable reference SoC platform for the Western Digital / CHIPS Alliance SweRV cores. SweRVolf is designed for software engineers who wants a turn-key system to evaluate SweRV performance and features, for system designers who want a base platform to build upon and for learners of SoC design, computer architecture, embedded systems or open source silicon methodology. To easily achieve the goals of portability and extendability it is powered by FuseSoC, which just happens to be one of my other open source silicon projects mentioned later on.
+During 2020 SweRVolf gained support for booting from SPI Flash but most effort was spent on usability, by making it rock-solid, improve documentation, increase compatibility with more EDA tools, keep the underlying cores up-to-date and follow along with changes in the Zephyr operating system, which is the officially supported software platform for SweRVolf.
+But the biggest thing to happen SweRVolf this year is that SweRVolf will be used as the base of a new university course from Imagination University Programme called RVfpga: Understanding Computer Architecture. I’m very excited (and slightly scared) about soon having thousands of students getting familiar with computer architecture, RISC-V and open source silicon through a SoC that I have designed. And I would like to mention a few things about how SwerRVolf is built because I think it’s a great example of how to create chip designs. When I say that I have designed SweRVolf, most of the work has consisted of putting together various pieces and make sure it works well as a whole. Most of the underlying code has been written by other people, and from my perspective, that is really the most successful aspect of SweRVolf because it highlights the rich open source silicon ecosystem. The main CPU core is from Western Digital and governed by CHIPS Alliance. Most of the AXI infrastructure was developed through the [PULP project](PULP project) at ETH Zürich and University of Bologna. The UART and SPI controllers were developed for the OpenRISC project during the first wave of open source silicon almost 20 years ago. The Wishbone infrastructure was developed by me when I started out with open source silicon ten years ago and the memory controller was created by Enjoy Digital and is written in Migen as part of the Litex ecosystem. And to go full circle, the memory controller uses a tiny RISC-V CPU called SERV internally to aid with calibration. SERV, the world’s smallest RISC-V CPU is written by me. Small world. And of course the whole project is packaged with FuseSoC and uses Verilator by default for simulations, so it’s FOSSi all the way. As I hope you understand by now it’s not about some lone hero churning out code, but instead all this has been made possible by a huge amount of work by a ton of people over many years, and I’m proud to be one of them.
+Probably the hobby (read unpaid) project I spent most time on during 2020 was SERV, the world’s smallest RISC-V CPU, which turned from small to even smaller during the year. SERV is very much a project driven by numbers, so lets look at some of these numbers.
+In February I got hold of an ZCU106 development board with a huge Xilinx Ultrascale+ FPGA for a project I was assigned to. As this was the largest FPGA I had ever had in my home I got curious to see how many SERV cores I could squeeze into it. The year before, at the 2019 RISC-V workshop in Zürich, I had done a presentation on how to fit 8 RISC-V cores in a small Lattice iCE40 FPGA (spoiler: it ended up being slightly more than 8 eventually), giving each of them a single I/O to communicate with the outside world. Problem this time was that after stuffing in 360 cores I run out of I/O pins. It would also had been practically impossible to verify that all these external pins actually did what they were supposed to do, so I needed some way of using less than one I/O pin per core. Then it struck me that just a few months earlier I had created a heterogenous sensor aggregation platform based on SERV cores called Observer. The idea with Observer was to connect a lot of sensors to an FPGA, each serviced by its own SERV core and then merge the data to an output stream. I gave up on the platform when I realized that while I could fit a lot of SERV cores into the devices, I just had a few sensors so there wasn’t much data to to aggregate. But this platform was a very good starting point.
+
+Block diagram of the Observer platform
By removing all sensor interfaces and just have each core print out an identification message instead I had a system that I could instantiate with any number of cores. Trying this on the ZCU106 I could now run over 600 cores on the FPGA. The next problem then was that I was running out of on-chip RAM way before any of the other FPGA resources. In case you don’t know, most FPGAs contain a number of fixed-size SRAM spread out over the devices, each typically being 1-8kB large. For SERV, each core used one for the RF (register file), and another one for the program/data memory. With RISC-V using 32 32-bit registers, this means that only 128 bytes of the RF RAM is used but since the fixed-size SRAM on FPGAs are typically being far larger than that most of the RAM ends up unused. That’s bad, but I had a plan. With a bit of work I managed to share RF, program and data in the same RAM so that the RF is allocated to the top 128 bytes of the RAM. This freed up half of the on-chip RAM blocks and I could eventually hit 1000 SERV cores on the ZCU106 board. Of course, at this point I was curious to see what the situation was for other boards after all these optimizations. Taking it one step further I figured I should turn this into a real thing by creating a benchmark so that people can have a quick way to see roughly how large the FPGAs are on different boards. And with that ServMark was born.
+
ServMark lasted for about three minutes until I realized CoreScore was a much catchier name, so that’s we have now.
+
I had originally planned to do a presentation about SERV at Latch-Up in Boston. But for well-known reasons we cancelled all FOSSi Foundation physical events. Instead I accepted an invitation to speak at the First virtual RISC-V Munich meetup. By this point I had attended a couple of virtual meetups and I hated it. It was in most cases awful to watch a narrated slide deck without a stage and a speaker to bring it to life at least a bit. So, I decided to take a fresh look and look at the possibilities instead of being limited by the medium. I decided to make videos instead. First of all, since people would watch on a computer screen with proper resolution instead of a washed-out image projected on canvas. This meant I could have much more detailed pictures and smaller font sizes. I could also freely mix pictures and animations, fine-tune timings, do several takes of the audio and add sound effects. And despite being done by someone who has pretty much zero experience in these sort of things, I think it turned out pretty well. So on the day of the event, I just introduced myself and let the audience indulge in my fully immersive multimedia edutainment experience about SERV. Not sure why the Oscars committee hasn’t got in touch yet.
+Is CoreScore the only attempt to put a mind-boggling number of RISC-V cores inside chips? Absolutely not, and during the summer I learned of the Manticore project from Florian Zaruba and Fabian Schuiki (jointly known as Flobian Schuba) from ETH Zürich, both well-known names in the FOSSisphere from their work in the PULP ecosystem. Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing had been accepted into the prestigious Hot chips conference. Manticore is an impressive project, but I still thought it was a bit unfair that I wasn’t invited as well. So I reached out for the biggest FPGA board I could find and then wrote my first academic paper of the year called Plenticore: A 4097-core RISC-V SoClet Architecture for Ultra-inefficient Floating-point Computing. Unfortunately I did not recieve an invitation to Hot chips despite this. I assume it must have gotten lost in the mail somewhere.
+Oh well, let’s look at some more numbers instead.
+
+SERV resource usage over time on a Lattice iCE40 FPGA
Coming back to CoreScore, the results right now range from 10 cores on a smaller Lattice iCE40 device up to 5087 cores on a large Xilinx device and the high score table can even be [viewed interactively online](https://corescore.store/! If you can’t find your favorite board there, just send a PR and we’ll get it added. And if any people with access to crazy large FPGAs happen to read this, please get in touch with me. I’m very curious to see who will be first to get above 10000 cores.
+SERV also saw another great improvement in the form of documentation. While not completely there yet, the functionality of most SERV modules have been documented together with detailed schematics showing the implementation down the individual gates, muxes and flip-flops. And most changes to the source are now accompanied by a code comment to clarify what is going on. Since SERV is optimized for size rather than readability, many parts of the core are difficult to figure out by just looking at the source code. Hopefully this will make it easier for other who want to understand or work on the core, but frankly it has also been very useful for me since I tend to forget why I did things in a certain way so I have had to spend a lot of time following my own tracks.
+
+Schematic of the SERV control unit from the SERV documentation
The oldest of my open source silicon project still going strong is FuseSoC. It is now about to turn ten years old and keeps growing in features and users for each year. Looking back at the changes through 2020 I can see some new trends in the development. The most important one is that for the first year ever, most of the work was not done by me. During 2020, my fellow FOSSi Foundation director and LowRISC employee Philipp Wagner has been pulling the heaviest load of FuseSoC development. And with Philipp came quality. Dr. Wagner has improved FuseSoC in pretty much every aspect. Bugs have been fixed and features has been added. The development experience has been improved by CI testing, automatic code formatting checks and improved testing coverage. And what makes me happiest is that the user experience has been improved not least by a total rewrite of the documentation into something that is actually useful and can be proudly shown to the world. All this is very much needed as FuseSoC is becoming increasingly popular. It has already been picked up by many of the flagship open source silicon projects like OpenTitan, SweRVolf, OpenPiton and with the RVFPGA university programme there will soon be a whole new generation who will get familiar with it as well.
+In 2018, the part of FuseSoC that interacted with the EDA tools was spun off into Edalize. The reason was that it was believed this part could be useful for others who weren’t interested in the whole FuseSoC package. This prediction seems to have been correct and Edalize has very much started a life on its own by now. In addition to FuseSoC, Edalize is now used by several other projects such as Silice, Clash and fpga-perf-tool and over the year Edalize has gained support for 7 new EDA tool flows, bringing the total number up to 25.
+2020 was also the year when Edalize had it’s first taste of being in the spotlight on its own merits. For the Workshop on Open-Source EDA Technology (WOSET) 2020 I decided to submit a presentation about Edalize. Being an academic conference this also prompted me to write an accompanying paper as is the common courtesy for these kind of events. The paper received a lukewarm response but was accepted anyway. Once again I did not feel like reciting slides to a camera so I turned back to my new-found interest in advanced multimedia productions. And it paid off. The Edalize video won an award for best video at WOSET 2020. Well done Edalize!
+All of the above projects use FuseSoC and Edalize because – well it’s kind of why I created FuseSoC in the first place – to easily reuse components and retarget to different devices. But I also realized there was a need for a dead simple project to help people getting started with FuseSoC – the Hello world of silicon, so to speak. And the Hello World of silicon is of course the blinking LED. So in 2018 I created project LED to Believe with the ambitious goal to create FuseSoC-powered LED blinkers for every FPGA board ever made. The project has several aspects that are useful in different ways. It serves as a very simple introduction to FuseSoC and how to make a design that targets multiple hardware. It is also an excellent pipe cleaner for when you receive a new board. If you can run the project successfully and get the LED to blink, it likely means you have managed to install all the EDA tools correctly which is no small feat, and you also have a template to take on bigger projects. And it’s also fun to see what boards are available out there. While I have submitted a bunch of the board ports myself, the vast majority have come from all the fantastic contributors out there. And during 2020 the number of supported boards grew from 16 to 44. Perhaps not all the FPGA boards ever made, but a considerable chunk of them. And already in the short amount of 2021 that has passed, there have been numerous more contributions so we’re getting closer all the time.
+In closing, 2020 was a busy year FOSSi-wise. And this has just touched upon the surface of all things that have been happening during the year. And just as we were about to close the books on 2020, I was informed that Lattice had incorporated one of my FOSSi projects into their shiny new award-winning Propel design suite. Which project, you might ask? Was it the similarly award-winning FuseSoC, to give Lattice users immediate access to a rich ecosystem of Open IP cores? Or was it the Rosetta stone of Edalize, with its award-winning video, that would easily provide a coherent interface for a dozen simulators and make it easy to switch between Lattice’s multitude of FPGA tools such as Diamond, icecube2 and Radiant? Or was it SERV itself, the award-winning CPU capable of offering a RISC-V experience for all but their absolutely smallest offerings? Well, actually, none of the above. It turns out that Propel now contains ipyxact, my somewhat feature-limited Python library for working with IP-XACT files. Not my first choice, but fair enough. I wonder if they have read my somewhat complicated relationship with IP-XACT.
+
+Finally my work is recognized by big EDA vendors (picture by Gatecat)
+
+This post was originally published at Antmicro.
+In our daily work at Antmicro we use FPGAs primarily for their flexibility and parallel data processing capabilities that make them remarkably effective in advanced vision and audio processing systems involving high-speed interfaces such as PCI Express, USB, Ethernet, HDMI, SDI etc. that we develop and integrate as open source, portable building blocks. Many of our customers, however, use FPGAs also in a different context, namely for designing ASICs, which is a highly specialized market that typically involves large FPGAs, proprietary flows and IP. In one such project, we were working with one of the largest FPGAs in production today, the 9-million LUT Xilinx VU19. Being a design with considerable complexity, it needed a high-throughput link between the FPGA and the host PC that could be thoroughly benchmarked, analyzed and optimized for the use case.
+Implementing PCIe is not completely straightforward as you have to synchronize multiple lines of high-speed bi-directional data. If you hit a bug somewhere in your data flow, things get very tricky to debug, especially if you have no ability to inspect and change the source code of the IPs involved. Being active developers of a variety of portable and reusable open source FPGA IP cores, for the project in question we were able to integrate a fully open PCIe interface into the Xilinx VU19-based ASIC prototyping platform using LiteX/LitePCIe, achieving a pretty respectable throughput of 31 Gbits/s on an 8-lane bandwidth. Although the FPGA chip itself is capable of 16-lane bandwidth for transferring data, the proFPGA board used in the setup supports only 8 lanes, but with hardware capable of bigger bandwidth we can achieve even greater throughput if needed. In fact, the repository also contains instructions for a 16-lane capable VU9-based setup – using a popular and not as prohibitively expensive devboard available from after-market- where we could measure as much as 59 Gbits/s.
+
Our ability to rapidly iterate as well as track down and fix bugs in the system we have created for this customer project demonstrates the scalability and portability of the open source-based approach, and is an example of Antmicro’s wider efforts aimed at developing reusable building blocks and introducing improvements to the whole FPGA ecosystem.
+Open source-licensed IP cores play well with the open source FPGA and ASIC tooling that we are building to enable a faster, collaborative and modular system development workflow – a goal that is shared by CHIPS Alliance, of which we are proud to be a Platinum member. As one of the many examples, we are making great progress in enabling open source synthesis and simulation of complex SystemVerilog-based designs, such as security-focused RISC-V cores like OpenTitan’s Ibex. Some of our other projects focus on open source synthesis and place & route flows, linters, formatters, CI systems, simulation platforms, test suites and more.
+The PCIe core used in the ASIC prototyping project also works great in sophisticated computer systems we have been building for our customers. The wide array of customizable and licence-free FPGA IPs and SoC generators that we work with allows us to implement specific functionalities in the devices we build and it includes MIPI CSI and other camera interfaces, SDI, HDMI, ISP processing, video codecs, AI and 2D GPU acceleration, I2S, SPDIF, PCIe, USB, Ethernet, DMA, SATA and DRAM controllers.
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+CHIPS Alliance’s latest Deep Dive Cafe featured an outstanding talk by a Google physical design engineer, Young-Joon Lee, who has a PhD from Georgia Tech, and has been working on machine learning physical design projects for the past two years.
+The chip placement problem is a notoriously challenging design problem, and has been explored in the electronic design automation research and development community for years. For those unfamiliar with the problem, it involves finding the optimal placement of physical cells implementing the logical function on a chip image to minimize performance, power, and area of the silicon, which in the end affects the cost of the product. The effort by Google to apply machine learning to the placement problem started as part of the Google Brain effort, which in part focuses on running algorithms at scale on large amounts of data.
+Deep learning itself started taking off in 2012, with computational needs rapidly increasing every three to four months. Machine learning is particularly applicable to the placement problem as different moves that are tried for training can be fed back to the underlying network as part of reinforcement learning. Models are trained and scale on distributed systems with billions of parameters.
+In this talk, Young-Joon shared how Google devised a hybrid approach to the placement problem, first placing large macros with reinforcement learning, and then using force directed placement for standard cells. As part of this effort, Google used an open source RISC-V processor called Ariane. The presentation highlighted the quality of results achieved, challenges, and the overall designer productivity that was afforded with the development of this technique. Of note, the recently released TPU v4 was able to be placed within 24 hours by the machine learning approach compared to six to eight weeks by a physical design engineer, achieving 3% shorter wirelengths and 23 more DRC violations.
+Finally, next steps in the project were discussed as well as how Google is exploring more machine learning techniques to use for other parts of electronic design automation.
+Watch the presentation below and check out the slides here: Learning To Play the Game of Macro Placement with Deep Reinforcement Learning
+ +
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+This post was originally published at Antmicro.
+Throughout 2020 we were hard at work developing proper, portable SystemVerilog support for multiple open-source FPGA and ASIC design tools used by us and our customers, most notably Yosys and Verilator. We strongly believe that the support is a necessary step in building a collaborative ecosystem and scalable and reproducible CIs, especially publicly accessible ones that are common in multi-organization projects such as OpenTitan and CHIPS Alliance. Leading the efforts towards achieving this goal, we’ve been developing a fully open source SystemVerilog parsing flow for Yosys and Verilator using UHDM and Surelog, achieving an important milestone: being able to fully parse, synthesize and simulate OpenTitan’s Ibex core directly from the SystemVerilog source.
+In this effort, Antmicro has been gradually covering various SystemVerilog functionalities and real-world implementations, developing support for different open source RISC-V cores and moving closer to a complete open-source synthesis and simulation tools support for Ibex – a small and efficient, 32-bit, RISC-V core used in the OpenTitan project. Originally developed at ETH Zürich as RI5CY, it is now maintained and developed further by lowRISC – a not-for-profit organization promoting collaborative engineering that targets open source silicon designs and tools.
+
What has proved very helpful in this process is the SystemVerilog test suite that we developed last year and continue to maintain together with a broad open source community in order to keep track of the supported and missing SystemVerilog features in a number of Verilog tools. It runs tests dedicated to various tools classes, covering a range of features, from single SV functionalities up to complex designs.
+Earlier this year, while closely tracking our progress using sv-tests, we have completed a number of milestones such as parsing Ibex in the Yosys synthesis tool directly or enabling SystemVerilog linting in formatting with Google’s Verible SystemVerilog parser and FuseSoC an open source tooling and IP package manager that is easy to integrate with existing workflows. The results of this ongoing work are now being used in several open source silicon projects, most notably OpenTitan. You can find a demo integration on our GitHub as described in dedicated blog note earlier this year.
+However, our overarching goal in this space was to enable parsing various complex SystemVerilog designs (with Ibex being the tip of the proverbial iceberg) with higher order tools which could be used as a front-end to multiple other tools, without the necessity to redo the work every time and to maintain SystemVerilog support in multiple tools.
+
This can be achieved with UHDM and Surelog – two open source tools originally developed by Alain Marcel. UHDM (Universal Hardware Data Model) is a multi-purpose intermediate library that enables plugging a parser into many different tools, while Surelog is a versatile, comprehensive SystemVerilog parser, pre-processor, elaborator and UHDM compiler.
+Adding enough coverage of SystemVerilog in UHDM/Surelog to support the Ibex core in two critical open source hardware development tools is an important milestone in Antmicro’s long-running collaboration with Google and Western Digital, both of which are driving the OpenTitan project as well as the FOSSi community, interested in open source simulation, synthesis, place & route and verification of designs of similar or bigger complexity than Ibex. A guide on using the Surelog/UHDM flow to synthesize the Ibex design is available on our GitHub.
+Open source technologies are bringing a new dimension to FPGA/ASIC development flows. Learn more at antmicro.com.
+
+
+This post was originally published at Antmicro.
+Open source toolchains are key to building collaborative ecosystems, welcoming to new approaches, opportunistic/focused innovations and niche use cases. The ASIC design domain, especially in the view of the rising tensions around manufacturing and supply chains, are in dire need of a software-driven innovation based on an open source approach. The fledgling open source hardware ecosystem has been energized by the success of RISC-V and is now being vastly expanded to cover the entire ASIC design flow by CHIPS Alliance, and Antmicro has been playing a leadership role in both of these organizations as well as offering commercial engineering and support services to assist with early adoption of open source approaches in hardware.
+One of CHIPS Alliance’s projects, the DARPA-funded OpenROAD, has created the necessary tooling to build open source ASIC-oriented flows such as OpenLane and OpenFASoC, becoming one of the central elements of the open ASIC ecosystem. The OpenROAD project, led by prof. Andrew Kahng from University of California San Diego, aims at a fully end-to-end, RTL-GDSII flow, providing accessibility and collaboration options that are often not available for proprietary tools.
+Antmicro is helping early adopters of OpenROAD-based flows, providing development services improving the tools themselves – such as the open source SystemVerilog support described in this note. Our engineering services involve introducing better, open workflows on the design and implementation level, but also scaling up into the cloud in collaboration with Google Cloud.
+There has been a lot of progress recently in the practical adoption of open ASIC design workflows, with most of the effort currently focused around the fully open source 130 nm SkyWater PDK for the release of which we collaborated with Google, efabless, SkyWater Technologies and many others. What is perhaps less known is that there have been successful tapeouts based on OpenROAD in more modern processes such as GF12 (and together with our customers we are planning more next year), but of course there is a long way to go until the toolchain can be considered a viable replacement for your latest-gen smartphone SoC design. There are, however, serious advantages in favor of an open source ASIC design flow, and to get there, delivering practical value in useful increments is needed. This is why we are working in CHIPS Alliance on making the flow more useful for practical designs.
+The hope for open source ASIC flows like OpenLane is to provide multiple benefits:
+In this early and emerging ecosystem, having a commercial support partner like Antmicro which can be relied on for the tools development is important for success – this lets you focus on your design while we take care of the infrastructure needs. Already now there are many niche use cases which can benefit from employing point open source improvements, and our work in CHIPS aims at broadening the application area of open source ASIC design flows to capture the needs of the broader market and bring the benefits of software innovation to hardware. We offer flexible, scalable engineering services to support our customers every step of the way.
+OpenLane is an automated RTL to GDSII flow that is composed of several tools such as OpenROAD, Yosys, Magic, Netgen, Fault, CVC, SPEF-Extractor, CU-GR, Klayout and a number of scripts used for design exploration and optimization. This collection of tools performs all steps required in a full ASIC implementation from RTL to GDSII.
+The flow, depicted below, consists of several highly customizable stages. In the initial stage the RTL source files written in an HDL (Hardware Description Language) are synthesized, technology mapped and analyzed in terms of timing. In the following step the floorplan and power distribution network are prepared for the design placement. Once finished, the design and clock placement is performed followed by global routing. With the physical layout ready in the form of a DEF (Design Exchange Format) file, it’s possible to perform several DRC checks, including Antenna Net or LVS (Layout vs. Schematic), to eventually generate the final GDSII layout file which contains a complete layout description that is now ready to be sent to the foundry.
+
Our latest improvement in the OpenLane open source ASIC build flow is adding a Surelog/UHDM/Yosys flow that enables SystemVerilog synthesis without the necessity of converting the HDL code to Verilog as an intermediate step.
+Yosys is a highly extensible open source HDL synthesis tool used in the RTL synthesis step of the OpenLane flow. Yosys has extensive Verilog-2005 support, but it needs additional plugins to support other languages such as VHDL or SystemVerilog. Previously, SystemVerilog support was only supported with a proprietary plugin, but Antmicro has been involved in adding the SystemVerilog support to Yosys through recent contributions adding UHDM (Universal Hardware Data Model) frontend which has been described in a separate Blog note. UHDM is a file format for storing hardware designs and at the same time a library able to manipulate this format. Designs written in SystemVerilog can be elaborated to the UHDM format by Surelog, which is a tool that aims to be a fully-featured SystemVerilog 2017 preprocessor, parser and elaborator. In our recent efforts both the Surelog parser library and the UHDM library have been integrated with Yosys which essentially enabled seamless SystemVerilog support.
+
This combination of Surelog/UHDM/Yosys is a very practical improvement for the OpenLane ASIC build flow as it enables using it with a number of existing ASIC designs which are often implemented with SystemVerilog (e.g. OpenTitan’s Ibex/Earl Grey (an SoC based on Ibex), OHG’s Core-V, University of Washington’s BlackParrot, CHIPS Alliance’s SWeRV).
+Together with Google, we are working with relevant communities to prove the feasibility of these designs with our open source flows and the open source SkyWater PDK.
+The OpenLane toolchain relies on dockerized tools to implement the flow in practice. This allows the users to focus on building the designs without the necessity of handling complex tools dependencies.
+In order to add SystemVerilog support to OpenLane, you need to have a Docker container with Yosys with UHDM support. First you will need to install the OpenLane flow files as well as the PDK (Process Design Kit) files.
+git clone https://github.com/The-OpenROAD-Project/OpenLane.git
+cd OpenLane
+
+make openlane
+make pdk
+cd docker_build/
+make build-yosys DOCKER_BUILD_OPTS=--no-cache
+make merge
+Once the tools are built and containers recreated, you can see the tools in action using this example CI run:
+export IMAGE_NAME=<docker image name>
+make test
+Optionally, you can run the OpenLane container in interactive mode and manually run the OpenLane flow script.
+export IMAGE_NAME=<docker image name>
+make mount
+./flow.tcl -design spm
+exit
+The IMAGE_NAME environment variable selects which Docker image will be used. If not set, a default OpenLane image will be fetched from DockerHub. The default image does not implement the Surelog/UHDM/Yosys flow and will, most likely, fail when used with the synthesis scripts from the repository.
+The Surelog/UHDM flow is very similar to the original (Verilog only) flow, but differs in the way Yosys handles the RTL design. This is because Surelog and UHDM (along with the Yosys UHDM frontend) are packed into a library and loaded into Yosys as a plugin. Loading the plugin is one of the first steps of the synthesis process. Once the plugin is loaded, you can proceed to loading the RTL files and continue with the rest of the flow.
+At Antmicro, we are providing services to our customers developing custom ASICs on many levels both IP, tools (Yosys, VPR, OpenROAD, Renode etc.) as well as cloud scaling (distant, custom GitHub runners etc.), focusing on interoperability between the many building blocks needed for a complete ASIC design flow.
+Our collaboration with CHIPS Alliance partners like Google and Western Digital has been spawning many interesting projects which contributed to maturing the open source ecosystem. Our linting and formatting work, used by such projects like OpenTitan and Core-V, recently presented at the CHIPS Alliance Fall Workshop, is a very good example of delivering incremental value with solutions to practical problems. Other projects which enable the blending of old and new methodologies for chip design are the efforts towards UVM support in Verilator or co-simulation in Renode.
+
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+A more collaborative, open and software driven ASIC design methodology pioneered by the CHIPS Alliance requires an open source tooling stack to enable sharing of workflows, artifacts and fostering a free exchange of insights and improvements.
+While internally often using new design methodologies and languages such as Migen, Chisel or XLS, Antmicro is conscious of the fact that a lot of the world’s ASIC development involves SystemVerilog and UVM, and so we are working on bridging traditional and new ASIC development methodologies as described in a recent blog note.
+Another notable example of an effort to provide open source tools for a key part of the ASIC flow, the RTL creation itself, is Verible, an open source SystemVerilog toolkit developed by Google in collaboration with Antmicro within the CHIPS Alliance.
+The Verible project offers a variety of SystemVerilog development tools, including a parser, a linter and a formatter, that together make finding and fixing syntactic and stylistic errors and bugs in SystemVerilog code simpler and faster. Being completely open source, it enables implementation of open CI and massively scalable infrastructure, and since some time it also features a Language Server, which is currently under active development. The capabilities and new features will be described in this note.
+Modern code editors (both GUI- and command line-driven) offer many useful features: syntax highlighting, autocompletion, inline errors and warnings reporting, quick fixes, code refactoring and formatting, and more. In the past enabling these features required a separate implementation for each editor, usually resulting in multiple plugins with varying levels of coverage. As a result, support for language-related operations in different editors varied greatly, and making it consistently good was a tedious task.
+The Language Server Protocol (LSP) brought some much-needed standardization to the space, enabling a unified communication method between code editors (or IDEs) and language servers that provide the necessary language features. Since 2016 when the LSP became public and open, many language servers targeting a variety of languages have been created or adapted to follow the standard. Most of the popular editors support LSP, including VS Code (via specific extensions), Vim (via vim-lsp), Emacs (via lsp-mode), Neovim (built-in), Kakoune (via kak-lsp) and Helix (built-in). There are even LSP plugins for IDEs like IntelliJ.
We can distinguish three main parts in an LSP setup:
+
The editor and the language server are connected via the Language Server Protocol - with a language client on the editor side and a transport & router block on the language server side. Any changes in a file are stored in the text buffer. The editor can ask for diagnostics, symbols, location of definitions, the language server receives updates in the buffer delivered by the editor and analyzes the edited code, as well as the code present in the workspace, and then creates an indexer. This indexer holds all data about the code: available symbols, references, origin of variables etc. but also provides information about other kinds of relationships, e.g. inheritance between classes. This indexer, along with syntax trees coming from parsing the files, provide various services in the language server, such as completion, diagnostics or code action that help with code refactoring.
+The Verible project offers an impressive list of features, is regularly tested against an ever-growing suite of language compliance tests provided by the SystemVerilog Tester and is in active use by a variety of projects, including the security-oriented OpenTitan initiative. Antmicro has been involved in Verible’s development since its initial open source release and we are now leading the efforts focused on extending the LSP implementation, which has already yielded promising results.
+Although several SystemVerilog language server implementations existed before, they weren’t as comprehensive as Verible’s. verible-verilog-ls provides the functionalities that come with the Verible command line tools directly in the code editor. These include:
For more details about Verible’s tools and their capabilities, refer to the project’s documentation.
+verible-verilog-ls implements the standardized Language Server Protocol, which as mentioned before, enables support for editors and IDEs such as VS Code, Vim, Neovim, Emacs, Sublime, Kakoune and Kate. It helps highlight syntax errors or lint violations and, if available, suggests fixes. The specific way of hooking up the language server depends on the editor; as VS Code is one of the most popular code editors and also the original target for the LSP, the example shown below focuses on this editor.
VS Code typically adds new features and tools via extensions, in this case the Verible Language Server Extension.
+A demo of the AUTO-expansion feature in VS Code is shown below:
+ +You can get the extension by downloading the verible.vsix archive from the release files. Then, run VS Code with the following flag to install the extension:
code --install-extension verible.vsix
+For examples how to hook Verible’s LSP into other applications please refer to the verible-verilog-ls README.
The Verible language server, as well as the VS Code extension, are being actively developed by Antmicro, Google and the CHIPS Alliance community. Future updates will include, among others, expanding the information available on hover and finding symbol definitions across different files.
+Verible’s open and comprehensive nature, combined with dedicated GitHub actions and custom, scalable GCP-based GitHub runners, provides a software-driven, scalable solution for working with SystemVerilog codebases. If you’re interested in benefiting from this approach or would like to adapt other open source tools to speed up your ASIC development process, join the CHIPS Alliance Tools working group or reach out at contact@antmicro.com.
+
+
+Open development for SOCs gets major boost with new collaboration
+SAN FRANCISCO, Jan. 22, 2020 /PRNewswire/ — CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced industry leading chipmaker Intel as it’s newest member. Intel is contributing the Advanced Interface Bus (AIB) to CHIPS Alliance to foster broad adoption.
+CHIPS Alliance is hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code and software development tools relevant to the design of open source CPUs, SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.
+Intel is joining CHIPS Alliance to share the Advanced Interface Bus (AIB) as an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package. This effort is intended to encourage an industry environment in which silicon IP can be developed using any semiconductor process as a “chiplet,” and easily integrated with other chiplets into a single device to deliver new levels of functionality and optimization. Broader adoption and support for AIB-enabled chiplets will help device developers grow beyond the limits of traditional monolithic semiconductor manufacturing and reduce the cost of development. Working together, Intel and CHIPS Alliance will encourage the growth of an industry ecosystem which engenders more device innovation via heterogeneous integration.
+The AIB specifications and collateral will be further developed in the Interconnects workgroup. The group will begin work imminently to make new contributions to foster increased innovation and adoption. All AIB technical details will be placed in the CHIPS Alliance github. In addition, Intel will have a seat on the governing board of CHIPS Alliance. Go to www.chipsalliance.org to learn more about the organization or to join the workgroup mailing list.
+“We couldn’t be more happy to welcome Intel to CHIPS Alliance.” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital. “Intel’s selection of CHIPS Alliance for the AIB specifications affirms the leading role that the organization impacts for open source hardware and software development tools. We look forward to faster adoption of AIB as an open source chiplet interface.”
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
+
+Please join us for a special joint panel webinar session for the CHIPS Alliance Analog Workgroup and MOS-AK Foundation.
+This panel will feature speakers with 20 minute talks on the following topic areas:
+This webinar can be accessed via the following Zoom link, and will be recorded:
+Dec 7, 2022 12:00 PM Eastern Time (US and Canada)
+Topic: AWG/MOS-AK Panel Discussion
+Please click the link below to join the webinar: https://zoom.us/j/93058965332
+
+
+New Linux Foundation Project to Foster Flexible, Next-Generation Chip Design for Diverse Data-Centric Applications and Workloads
+SAN FRANCISCO – March 11, 2019 – The Linux Foundation, the nonprofit organization enabling mass innovation through open source, today announced its intent to form the CHIPS Alliance project to host and curate high-quality open source code relevant to the design of silicon devices. CHIPS Alliance will foster a collaborative environment that will enable accelerated creation and deployment of more efficient and flexible chip designs for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications.
+Early CHIPS Alliance backers include Esperanto Technologies, Google, SiFive and Western Digital, all committed to both open source hardware and continued momentum behind the free and open RISC-V architecture.
+“The RISC-V community is working to foster open source foundation technologies that will help unlock market innovation to move [artificial intelligence/machine learning and infrastructure composability] forward,” said Eric Burgener, research vice president of IDC’s Infrastructure Systems, Platforms, and Technologies Group, via a recent IDC report.
+The project will create an independent entity so companies and individuals can collaborate and contribute resources to make open source CPU chip and system-on-a-chip (SoC) design more accessible to the market.
+“Open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards,” said Mike Dolan, vice president of strategic programs, the Linux Foundation. “The same collaboration model applies to the hardware in a system, just as it does to software components. We are eager to host the CHIPS Alliance and invite more organizations to join the initiative to help propel collaborative innovation within the CPU and SoC markets.”
+“As new workloads surface every day, we need new silicon designs in order to optimize processing requirements,” said Martin Fink, interim CEO of RISC-V Foundation and executive vice president and CTO of Western Digital. “Today’s legacy general-purpose architectures are, in some cases, decades old. With the creation of the CHIPS Alliance, we are expecting to fast-track silicon innovation through the open source community.”
+CHIPS Alliance will follow governance practices consistent with other Linux Foundation projects, which will include a Board of Directors, a Technical Steering Committee, and community contributors who will work collectively to manage the project. Initial plans will focus on establishing a curation process aimed at providing the chip community with access to high-quality, enterprise grade hardware.
+Google is planning to contribute a Universal Verification Methodology (UVM)-based instruction stream generator environment for RISC-V cores. The environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs.
+Western Digital is planning to contribute their high performance, 9-stage, dual issue, 32-bit SweRV Core, together with a test bench, and high-performance SweRV Instruction set simulator. Additional contribution will be specification and early implementations of OmniXtend cache coherence protocol.
+SiFive was founded by the inventors of the free and open RISC-V Instruction Set Architecture, who, together with their colleagues at UC Berkeley, developed the first open source RISC-V microprocessors and a new open source hardware description language Chisel. This initial work at UC Berkeley also developed the RocketChip SoC generator, including the initial version of the TileLink coherent interconnect fabric.
+SiFive remains committed to maintaining and improving the RocketChip SoC generator and the TileLink interconnect fabric in opensource as a member of the CHIPS Alliance, and contributing to Chisel and the FIRRTL intermediate representation specification and transformation toolkit. SiFive will also contribute and maintain Diplomacy, the SoC parameter negotiation framework.
+To learn more about CHIPS Alliance, please visit www.chipsalliance.org.
+“Intellectual property for VLSI chip designs ought to be able to reap similar benefits as open source software has for years. We hope that the CHIPS Alliance will be a catalyst where all hardware designers feel comfortable both contributing and finding useful designs for their projects,” said Dave Ditzel, founder and CEO of Esperanto Technologies, Inc.
+“We are entering a new golden age of computer architecture highlighted by accelerators, rapid hardware development and open source architecture and implementations. Google is committed to fostering an open community of collaboration and innovation in both hardware and software,” said Dr. Amir Salek, senior director, Technical Infrastructure, Google Cloud. “TheCHIPS Alliance will provide the support and framework needed to nurture a vibrant open source hardware ecosystem for high-quality, well-verified and documented components to accelerate and simplify chip design.”
+“Semiconductor design starts have evaporated due to the skyrocketing cost of building a custom SoC,” said Dr. Yunsup Lee, co-founder and CTO, SiFive. “A healthy, vibrant semiconductor industry needs a significant number of design starts, and the CHIPS Alliance will fill this need. SiFive is excited to continue to work on and contribute to the RocketChip SoC generator, TileLink, Chisel, and FIRRTL projects as we push the boundaries of open source innovation.”
+“The data-centric universe continues to grow and expand in ways many of us never imagined,” said Dr. Zvonimir Bandic, senior director of next generation platforms architecture at Western Digital, a co-founder of RISC-V as well as CHIPS Alliance. “The CHIPS Alliance will provide access to an open source silicon solution that can democratize key memory and storage interfaces and enable revolutionary new data centric architectures. It paves the way for a new generation of compute devices and intelligent accelerators that are close to the memory and can transform how data is moved, shared, and consumed across a wide range of applications. By extending Western Digital’s commitment to the RISC-V architecture and instruction set, and teaming up with fellow industry leaders to form the CHIPS Alliance, we make another important stride forward toward unlocking the true potential of the data.”
+Founded in 2000, the Linux Foundation is supported by more than 1,000 members and is the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Linux Foundation’s projects are critical to the world’s infrastructure including Linux, Kubernetes, Node.js, and more. The Linux Foundation’s methodology focuses on leveraging best practices and addressing the needs of contributors, users and solution providers to create sustainable models for open collaboration. For more information, please visit us at linuxfoundation.org.
+Jill Lovato
+The Linux Foundation
+jlovato@linuxfoundation.org
+
+CHIPS Alliance’s general manager Rob Mains joined Amelia Dalton at EE Journal’s FishFry podcast for a lively discussion about how we’re working to make chip design more accessible. Rob discussed CHIPS Alliance’s work with RISC-V International to develop a new unified memory standard, along with our work to accelerate the design of open source chipsets with the AIB 2.0 specification. The conversation also touched on our efforts to provide better support for SystemVerilog using open source tools and to create a dynamic stratified scheduler implementation in Verilator.
+Check out the podcast here. The conversation with Rob starts at 7:03.
+
+
+This post was originally published at Antmicro.
+The flexibility of FPGAs makes them an excellent choice not only for parallel processing applications but also for research and experimentation in a range of technological areas.
+We often provide our customers with flexible R&D platforms that can be easily adapted to changing requirements and new use cases as a result of our practice of using open source hardware, software, FPGA IP and tooling.
+As an example of such activity, we have recently been contracted to develop a hardware test platform for experimenting with memory controllers and measuring vulnerability of various LPDDR4 memory chips to the Row hammer attack and similar exploits.
+
Targeting high-volume customer-facing devices where size, power use and unit cost are a priority, LPDDR4 does not come in the form of modules, while the hardware tools and software frameworks for testing it can be prohibitively expensive. +Despite efforts to mitigate the Row hammer exploit, a number number of memories available on the market remain vulnerable to the problem, which calls for a test platform that would allow experimenting with memory chips and memory controllers to devise new mitigation techniques.
+Another issue is that preexisting work mostly relies on proprietary memory controllers which cannot be adapted to specific memory access patterns that trigger Row hammer.
+To address this need, we have created a fully open source flow including Enjoy Digital’s open source memory controller LiteDRAM for which we implemented LPDDR4 support, to enable testing LPDDR4 memory chips.
+What our customer needed was a flexible platform for developing security measures that would be cost-optimized for high volume production.
+To accomplish that we’ve built a modular device that consists of the main test board and a series of easily swappable testbeds for different memory types, the first of which is already available on our GitHub.
+What is more, thanks to being open source, the platform enables various research teams to combine efforts and work collaboratively on coming up with new attacks and mitigations, as well as fully reproduce the results of the work.
+
The platform is based on Xilinx Kintex-7 FPGA and it features several I/O options: HDMI, which can be used for processing video data and experimenting with streaming and HDMI preview applications featuring RAM, USB for uploading your bitstream or debugging, as well as an SD card slot and GbE.
+There is also additional 64MB of on-board HyperRAM that enables safe experimentation with interchangeable RAM chips under extreme conditions.
+With Antmicro’s commercial development services the platform can be customized to meet your specific requirements, while the open source character of the solutions we use gives you full control over the product and vendor independence.
+We help our customers build complicated FPGA solutions, embrace the dynamically growing open source tooling ecosystem and develop various technologies that allow developers to work more efficiently across the whole FPGA spectrum.
+
+
+CHIPS Alliance is excited to announce that the hardware development community can submit their open source design projects to Efabless.com for space on their forthcoming shuttle. This opportunity comes after the success of having 40 submissions for the MPW-ONE shuttle; 60% of those designs were submitted by first-time ASIC designers. MPW-TWO is the second Open MPW Shuttle providing fabrication for fully open-source projects using the SkyWater Open Source PDK announced by Google and SkyWater.
+The shuttle gives designers the freedom to innovate without having to worry about the risks associated with the cost of fabrication. This is a great opportunity for individuals, universities, and industry to create their own IP and have it manufactured.
+The deadline for submission is June 18. Submissions must be open source designs and leverage open source tooling such as OpenROAD, OpenLane and other EDA applications that Efabless.com has at its design portal. Read more about the project requirements and submit here: https://efabless.com/open_shuttle_program/2.
+I look forward to seeing the community’s contributions for this generous offering from Efabless.com and Google.
+
+
+CHIPS Alliance to host online event to help community innovating with SweRV Core EH2 and EL2 Solutions
+SAN FRANCISCO, May 14, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced new enhancements to the SweRV Core™ EH2 and SweRV Core EL2, developed for the open-source community by Western Digital. Since the introduction of the cores earlier this year, the CHIPS Alliance has worked with its community to exhaustedly validate the cores through a transparent and rigorous process, as well as incorporate a variety of new updates.
+The SweRV Core EH2, the world’s first dual-threaded, commercial, embedded RISC-V core, is designed for embedded devices supporting data-intensive edge, artificial intelligence (AI) and Internet of Things (IoT) applications. SweRV Core EL2 is an ultra-small, ultra-low-power RISC-V core optimized for applications such as state-machine sequencers and waveform generators. The newly updated cores are now available to everyone for free.
+CHIPS Alliance will host an online event to discuss the SweRV Core EH2 and EL2, along with the available software support and solutions for programmers on May 20, 2020 at 5:30 p.m. PT. The event will feature talks from representatives of Antmicro, CHIPS Alliance, Codasip, Metrics and Western Digital.
+“Our work to help bring the newly enhanced SweRV Core EL2 and EH2 to the open hardware community demonstrates key progress towards our goal of accelerating RISC-V innovation. We’ve already seen significant industry interest in the SweRV Core EH1 and are pleased to offer two compelling additional options to engineers designing IoT, consumer, mobile and other embedded applications,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance.
+To register for the CHIPS Alliance virtual event on May 20, please visit: https://zoom.us/webinar/register/WN_fbjiN5uvSuGbGdWUGlI65g.
+To learn more about the SweRV Cores, please visit: https://github.com/chipsalliance/Cores-SweRV.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
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+CHIPS Alliance to highlight OmniXtend advances at RISC-V Summit
+SAN FRANCISCO, Dec. 8, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that the organization will highlight OmniXtend advances in a presentation at the RISC-V Summit, taking place virtually from Dec. 8-10, 2020. The CHIPS Alliance plans to work with RISC-V International to standardize an open unified memory coherency bus leveraging OmniXtend to foster innovation for data-centric applications.
+“As RISC-V is increasingly being considered for high end data center and enterprise applications, there is a need for seamless cache-coherent sharing memory systems,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital. “CHIPS Alliance is cooperating with RISC-V to standardize on a unified memory fabric and leverage OmniXtend, which allows heterogenous systems that use TileLink cache-coherence protocol to share the memory coherently. We see a unique opportunity because RISC-V is freely open, while other architectures don’t open up the coherency bus, with RISC-V we can create an open unified memory standard to accelerate innovation for data-centric, heterogeneous applications.”
+Said Mark Himelstein, CTO at RISC-V International: “ISAs do not stand alone. RISC-V needs a robust ecosystem and the OmniXtend roadmap will enable RISC-V members to create systems that deliver coherent, robust and performant solutions spanning the memory and storage hierarchies.”
+Dr. Bandić will be presenting the session “OmniXtend: Open Source Cache-coherence over Ethernet” on Wednesday, Dec. 9 at 12:30 p.m. PT. The session will discuss OmniXtend, a cache-coherency protocol architecture that exports Tilelink cache-coherence messages on the top of L2 ethernet frames. The presentation will report the results of four RISC-V nodes, each running four independent RISC-V harts, connecting via commercial ethernet switch, and establishing a ccNUMA (cache coherent non-uniform memory access) architecture. The session will also highlight a detailed study of local and non-local (i.e. going through ethernet switch) cache access latencies, and propose several software models for OmniXtend-backed architectures.
+Omnixtend will also be discussed in another session at the RISC-V Summit, “Building Cache-coherent Scaleout Systems with Omnixtend” with Atish Patra and Tu Dang at Western Digital on Tuesday, Dec. 8 at 3:30 p.m. PT. Atish and Tu will discuss how to provide the necessary support for OmniXtend to build a scalable system with thousands of nodes, since designing, verifying and deploying these scale-out systems in hardware is time consuming. The session will cover a two-fold approach to build and accelerate the development of OmniXtend scale-out systems: an initialization and configuration protocol defining a simple yet race-free approach to setting up multiple OmniXtend nodes during boot, and a software simulation/emulation framework which implements the OmniXtend protocol and an Omnixtend system emulation using Qemu.
+The RISC-V Summit will also feature a keynote about the open ecosystem of modern tools, frameworks and platforms that are creating a seamless environment for developers to build advanced ML applications on RISC-V. The session, “Building an Open Edge Machine Learning Ecosystem with RISC-V, Zephyr, TensorFlow Lite Micro and Renode,” will take place on Tuesday, Dec. 8 at 10 a.m. PT and will be moderated by Michael Gielda at Antmicro and feature Tim Ansell at Google, Kate Stewart at the Zephyr Project and Brian Faith at QuickLogic.
+To learn more about the RISC-V Summit, please visit: https://tmt.knect365.com/risc-v-summit/.
+To register for the RISC-V Summit, please visit: https://riscv.informatech.com/2020/registrations/Attendee.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
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+Antmicro Joins CHIPS Alliance to develop open source cores, IP blocks and tools for CPUs, RISC-V-based SoCs and peripherals
+SAN FRANCISCO – April 18, 2019 – CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Antmicro is joining the organization. Antmicro is a software-driven technology company focused on introducing open source into strategic areas of industry, especially edge AI. Announced just last month, the CHIPS Alliance welcomes Antmicro among its initial members Esperanto Technologies, Google, SiFive, and Western Digital.
+CHIPS Alliance is a project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of more efficient and flexible CPUs, SoCs, and peripherals for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications. The CHIPS Alliance project hosts and curates high-quality open source Register Transfer Level (RTL) code relevant to the design of open source CPUs, RISC-V-based SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon. Members are committed to both open source hardware and continued momentum behind the free and open RISC-V architecture.
+“The RISC-V Foundation directs the standards and promotes the adoption of the open and free Instruction Set Architecture. This enables organizations to innovate for the next generation of hardware development. CHIPS Alliance is a natural extension for companies and universities who want to collaborate and create RTL based on RISC-V and related peripherals,” said Calista Redmond, CEO of the RISC-V Foundation.
+“Antmicro believes in open source collaboration around portable, extendible and vendor-neutral technologies, which we consider a strong foundation for transparent, shared development processes based on good practices. We’re joining CHIPS Alliance because it is the conduit through which we can all realize the vision of open source RTL designs for silicon and FPGAs,” said Peter Gielda, CEO of Antmicro.
+The CHIPS Alliance community includes technology developers and contributors supported by a Board of Directors and a Technical Steering Committee. Its initial plans focus on establishing a curation process aimed at providing the FPGA and chip community access to high-quality, enterprise grade hardware.
+Antmicro (www.antmicro.com) is a software-driven tech company developing advanced open source-based cyber-physical and edge AI systems. Antmicro provides open software, hardware, tooling, new development methodologies and applied R&D to customers worldwide, accelerating new product development and adoption of modern computing platforms, both CPU/ASIC, GPU and FPGA-based. A Platinum Founding Member of the RISC-V Foundation, Antmicro supports, uses, contributes to and helps promote a broad range of open source technologies such as RISC‑V, Renode, Tensorflow, Zephyr, Linux and Android.
+Founded in 2000, the Linux Foundation is supported by more than 1,000 members and is the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Linux Foundation’s projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation’s methodology focuses on leveraging best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, please visit us at linuxfoundation.org.
+Jill Lovato
+The Linux Foundation
+jlovato@linuxfoundation.org
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+This post was originally published at Antmicro.
+In order to fulfill our internal and our customers’ needs, we have developed and successfully deployed an open source custom GitHub Actions runner that allows us to mix the GitHub default and your custom hardware and software. The runner software itself operates within a Google Cloud Platform project, spawns Compute Engine instances and orchestrates the build, providing a number of interesting advantages that were needed in our ASIC and FPGA-related work. As is typical for us, we have released all the necessary components as open source – read on to learn how the solution works, the benefits it offers and how to build and deploy this software in your organization (which we can also help with as part of our commercial support and engineering services).
+As we continue our push for more software-driven hardware development as part of our work within CHIPS Alliance and RISC-V, we see an increasing need for scalable and flexible CI solutions that can be used with a mix of open source and proprietary components. By building on top of existing infrastructure such as GCP, GH Actions and Terraform, it’s possible to achieve noticeable performance gains, better traceability and runtime isolation for some of the advanced use cases we are helping our customers tackle (we have highlighted some of those aspects previously in a blog note earlier this year).
+By default, the software leverages virtual infrastructure created within a GCP project in order to perform builds, consisting of a coordinator instance (which receives jobs from GitHub backend and reports back progress), a virtual subnetwork and dynamically spawned worker instances.
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In order to reduce the cognitive strain and encapsulate complexity, we’ve prepared a Terraform module that can be used to provision these necessary components easily and make it possible to store the configuration of individual coordinators according to the principles of Infrastructure as Code.
+Once provisioned and configured, the coordinator is able to spawn instances of any type available within Google Compute Engine. In projects where cost optimizations are a necessity, it is possible to configure the coordinator to spawn preemptible instances.
+The setup is flexible enough that you can self-host it in your internal infrastructure and connect custom hardware such as FPGA platforms to the coordinator machine, which will then spawn per-job virtual machines with hardware attached using a pass-through mechanism. This capability makes it possible to build automated hardware in the loop testing platforms – something we see as an increasingly useful feature especially given the growing portfolio of our server-oriented platforms like Scalenode and the FPGA-based DC-SCM.
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When creating increasingly complex CI pipelines, we also need a better overview of the builds we are performing. In order to address this requirement, our runner introduces a couple of changes that at the first glance might seem minor, but contribute to a significant improvement in readability.
+Firstly, in the build logs, each line of output is prefixed with a green or red-colored timestamp, depending on whether the output is coming from standard output or standard error. As a measure to augment the output of Bash scripts, lines that come out as a result of the “set -x” option are highlighted as well, providing a yet another visual cue for the reader.
+Another important improvement is related to performance analysis and resource usage. To get more insight into our complex and often resource-heavy builds (related to the fact that activities such as place and route or physical layout may take many hours if not days to complete), each worker collects a performance graph using sargraph that can be later retrieved using the upload-artifact action.
+This kind of rich context for our CI infrastructure is a necessity for our work related to e.g. to the FPGA interchange format or dynamic scheduling in Verilator whose goals are to enable radical improvements in FPGA and ASIC design. We are doing this by visiting previously unexplored avenues and encouraging a broad collaboration with the research community, customers and partners to achieve a step function progress in areas which are only now starting to experience the explosion of creativity related to new open source and software-driven approaches.
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Apart from supercharging the logs with visual metadata, we’ve addressed the issue of log storage. Google’s BES and ResultStore APIs lend themselves to this use case, allowing the upload of rich metadata associated with the builds and providing a pretty front-end for viewing the logs. Thanks to that, we have an alternative place where logs, artifacts and the aforementioned performance graphs can be stored and viewed independently of GitHub. An example of how this works can be seen in the SymbiFlow examples repository by clicking on any tick associated with a commit and scrolling down to the bottom. This functionality was implemented using our open source distant-bes and distant-rs libraries.
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The ongoing effort to enable cloud-assisted ASIC design as well as new development methodologies for FPGAs is bound to accelerate going forward, given the high interest among our customers and groups such as CHIPS Alliance.
+We always look forward to projects with partners who want to make full use of modern (and open) tooling and environments which, with knowledge and experience, we’re confident to modify for better, scalable and vendor-neutral system development.
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+This post was originally published at Antmicro.
+Rowhammer is a hardware vulnerability that affects DRAM memory chips and can be exploited to modify memory contents, potentially providing root access to the system. It occurs because Dynamic RAM consists of multiple memory cells packed tightly together and specific access patterns can cause unwanted effects that propagate to nearby memory cells and cause bit-flips in cells which have not been accessed by the attacker.
+The problem has been known for several years, but as shown by most recent research from Google performed with the open source platform Antmicro developed that we’ll describe in this note, it has yet to be completely solved. The tendency in DRAM manufacturing is to make the chips denser to pack more memory in the same size which inevitably results in increased interdependency between memory cells, making Rowhammer an ongoing problem.
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Solutions like TRR (Target Row Refresh) introduced in newer memory chips help mitigate the issue, although usually only in part – and new attack methods like Half-Double or TRRespass keep emerging. To go beyond the all-too-often used “security through obscurity” approach, Antmicro has been helping build open source platforms which give security researchers full control over the entire technology stack, and enables them to find new solutions to emerging threats.
+The Rowhammer Tester platform was developed for and with Google, who just like Antmicro believe that open source, well documented technical infrastructure is critical in speeding up research and increasing collaboration with the industry. In this case, we wanted to enable the memory security researchers as well manufacturers to have access to a flexible platform for experimenting with new types of attacks and finding better Rowhammer mitigation techniques.
+Current Rowhammer test methods involve using the chip-specific MBIST (Memory Built-in Self-Test) or costly ATE (Automated Test Equipment), which means that the existing approaches are either costly, inflexible or both. MBIST are specialized IP cores that test memory chips for errors. Although effective, they lack flexibility in terms of changing testing algorithms hardcoded into the IP core. ATEs devices are usually used at foundries to run various tests on wafers. Access to these devices is quite limited and expensive therefore chip vendors have to rely on DFT (Design for Test) software to produce compressed test patterns which require less access time to ATE while ensuring high test coverage.
+The main goal of the project was to address those limitations, providing an FPGA-based Rowhammer testing platform that enables full control over the commands sent to the DRAM chip. This is important because DRAM memory requires specialized hardware controllers and any software-based testing approaches have to communicate with the DRAM indirectly via the controller, which pulls the researchers away from the main research subject when studying the DRAM chip behaviour itself.
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The Rowhammer Tester consists of two parts: the FPGA gateware that is loaded to the hardware platform and a set of Python scripts used to communicate with the FPGA system from the user’s PC. Internally all the important modules of the FPGA system are connected to a shared WishBone bus. We use an EtherBone bridge to be able to interface with the FPGA WishBone bus from the host PC. [EtherBone] +(https://ohwr.org/project/etherbone-core/wikis/home) is a protocol that allows to perform regular WishBone transactions over Ethernet. This way we can perform all of the communication between the user PC and the FPGA efficiently through an Ethernet cable.
+The FPGA gateware has 3 main parts: a Bulk transfer module, a Payload Executor and the LiteDRAM controller along with a VexRiscv CPU. The Bulk transfer module provides an efficient way of filling and testing the whole memory contents. It supports user-configurable access and data patterns, using high-performance DMA to make use of full bandwidth offered by the LiteDRAM controller. When using the Bulk transfer module, LiteDRAM handles all the required DRAM logic, including row activation, refreshing, etc. and ensuring that all DRAM timings are met.
+In case when more fine-grained control is required, our Rowhammer Tester provides the Payload Executor module. Payload Executor can be thought of as a simple processor that can execute our custom instruction set. Most of the instructions map directly to DRAM commands, with minimal control flow provided by the LOOP instruction. A user can compile a “program” and load it to Rowhammer Tester’s instruction SRAM, which will be then executed. To execute a program, Payload Executor will disconnect the LiteDRAM controller and send the requested command sequences directly to the DRAM chip via the PHY’s DFI interface. After execution the LiteDRAM controller gets reconnected and the contents of the memory can be inspected to search for potential bit-flips.
+In our platform we use LiteDRAM which is an open-source controller that we have been using in multiple different projects. It is part of the wider LiteX ecosystem, which is also a very popular choice for many of our FPGA projects. The controller supports different memory types (SDR, DDR, DDR2, DDR3, DDR4, …), as well as many FPGA platforms (Lattice ECP5, Xilinx Series 6, 7, UltraScale, UltraScale+, …). Because it is an open source FPGA IP core, we have complete control over its internals. That means two things: firstly, we were able to easily integrate it with the rest of our system and contribute back to improve LiteDRAM itself. Secondly and perhaps even more importantly, the controller can be modified by groups focused on researching new memory attacking methods in order to expose existing vulnerabilities. The results of such experiments should essentially motivate vendors to work on mitigating the uncovered flaws rather than rely on the “security by obscurity” based approach.
+Our Rowhammer Tester is fully open source. We provide an extensive set of Python scripts for controlling the board, performing rowhammer attacks and harvesting the results. For more complex testing you can use the so-called Playbook, which is a framework that allows to describe complex testing scenarios using JSON files, providing some predefined attack configurations.
+Antmicro is actively collaborating with Google and memory makers to help study the Rowhammer vulnerability, contributing to standardization efforts under the JEDEC initiative. The platform has already been used to a lot of success in state-of-the-art Rowhammer research (like the case of finding a new type of Rowhammer attack called Half-Double, as mentioned in the opening paragraph).
+Initially our Rowhammer Tester targeted two easily available and price-optimized boards: Digilent Arty (DDR3, Xilinx Series7 FPGA) and Xilinx ZCU104 (DDR4, Xilinx UltraScale+ FPGA). They were a good starting point, as DDR3 and DDR4 PHYs for these boards were already supported by LiteDRAM. After the initial version of the Rowhammer Tester was ready and tested on these boards, proving the validity of the concept, the next step was to cover more memory types, some of which find their way into many devices that we interact with on a daily basis.
+A natural target was the LPDDR4 DRAM – a relatively new type of memory designed for low-power operation with throughputs up to 3200 MT/s. For this end, we designed our dedicated LPDDR4 Test Board, which has already been covered in a previous blog note.
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The design is quite interesting because we decided to put the LPDDR4 memory chips on a module, which is against the usual practice of putting LPDDR4 directly on the PCB, as close as possible to the CPU/FPGA to minimize traces impedance. The reason was trivial – we needed the platform to be able to test many memory types interchangeably without having to desolder and resolder parts, using complicated interposers or other niche techniques – the platform is supposed to be open and approachable to all.
+Alongside the hardware platform we had to develop a new LPDDR4 PHY IP as LiteDRAM didn’t have support for LPDDR4 at that time, resolving challenges related to the differences between LPDDR4 and previously supported DRAM types, such as new training modes. After a phase of verification and testing on our hardware, the newly implemented PHY has been contributed back to LiteDRAM.
+The project does not stop there; we are already working on an LPDDR5 PHY for next-gen low power memory support. This latest low-power memory standard published by JEDEC poses some new and interesting challenges including a new clocking architecture and operation on an even lower voltage. As of today LPDDR5 chips are still hardly available on the market as a bleeding-edge technology, but we are continuing our work to prepare LPDDR5 support for our future hardware platform in simulation using custom and vendor provided simulation models.
+The fact that our platform has already been successfully used to demonstrate new types of Rowhammer attacks proves that open source test platforms can make a difference, and we are happy to see a growing collaborative ecosystem around the project in a joint effort to ensure that we find robust and transparent mitigation techniques for all variants of Rowhammer for the foreseeable future.
+Ultimately, our work with the Rowhammer Tester platform shows that by using open source, vendor-neutral IP, tools and hardware, we can create better platforms for more effective research and product development. In the future, building on the success of the FPGA version, our work as part of the CHIPS Alliance will most likely lead to demonstrating the LiteDRAM controller in ASIC form, unlocking even more performance based on the same robust platform.
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+This post was originally published at Antmicro.
+In modern digital camera systems, the captured image undergoes a complex process involving various image signal processing (ISP) techniques to reproduce the observed scene as accurately as possible while preserving bandwidth. On the most basic level, most CCD and CMOS image sensors use the Bayer pattern filter, where 50% of the pixels are green, 25% are red and 25% are blue (corresponding to the increased sensitivity of the human eye to the green color). Demosaicing, also known as debayering, is an important part of any ISP pipeline whereby an algorithm reconstructs the missing RGB components/channels of each pixel by performing interpolation of the values collected for individual pixels.
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The rapid development of FPGA technologies has made it possible to use advanced ISP algorithms in FPGAs even for high-res, multi-camera arrays, which is great news for resource-constrained real-time applications where image quality is essential. In our R&D work, we are developing reusable open source building blocks for various I/O and data processing purposes that can be used as a starting point for customer projects which need to be bootstrapped quickly, and those include IP cores for debayerization.
+As part of a recent project, we implemented and tested an open source FPGA-based demosaicing system that converts raw data obtained from CCD or CMOS sensors and reconstructs the image using three different interpolation algorithms controlled via a dedicated wrapper. The three interpolation methods are:
+The demosaicing system consists of two parts. The most important part is formed by the demosaicing cores representing the three algorithms described earlier.
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The software part of the system runs in the FPGA and features the bootloader, operating system (Linux), Antmicro’s open source FastVDMA IP core that controls data transmission between the demosaicing setup and the DDR3 memory, and a dedicated Linux driver that makes it possible to control the demosaicing cores from software.
+Apart from building highly-capable vision systems based on FPGA platforms, we are developing various tools, open source IP cores and other resources to provide our customers with a complete, end-to-end workflow that they can fully control.
+Some of our recent projects include the FPGA Interchange Format to enable interoperability between FPGA development tools, an open source PCIe link for ASIC prototyping in FPGA or an FPGA-based testing framework for hardware security of DRAM. If you would like to benefit from introducing a more software-driven, open source friendly work methodology into your next product development cycle, reach out to us at contact@antmicro.com and keep track of our growing list of open IP cores at the Antmicro Open Source Portal.
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+This post was originally published at Antmicro.
+Our work together with Google and the world’s research community on detecting and mitigating the Rowhammer problem in DRAM memories has been proving that the challenge is far from being solved and a lot of systems are still vulnerable. +The DDR Rowhammer testing framework that we developed together with an open hardware LPDDR4 DRAM tester board has been used to detect new attack methods such as Half-Double and Blacksmith and all data seems to suggest this more such methods will be discovered with time.
+But consumer-facing devices are not the only ones at risk. With the growing role of shared compute infrastructure in the data center, keeping the cloud secure is critical. That is why we again teamed up with Google to bring the open source FPGA-based Rowhammer security research methodology to DDR4 RDIMM used in servers by designing a new Kintex-7 platform for that use case specifically, to foster collaboration around what seems to be one of the world’s largest security challenges.
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The data center DRAM tester is an open source hardware test platform that enables testing and experimenting with various DDR4 RDIMMs (Registered Dual In-Line Memory Module).
+The main processing platform on this board is a Xilinx Kintex-7 FPGA which interfaces directly with a regular DDR4 DIMM connector. The new design required more IOs compared to the LPDDR version, which was a major driving factor for changing the Kintex-7 FPGA package from 484 to 686 pins.
+Basing the test platform on the Kintex-7 FPGA allowed us to implement a completely open source memory controller – LiteDRAM – fully within the FPGA just like for the LPDDR case. The system can thus be modified and re-configured on both hardware and software level to freely sculpt memory testing scenarios, providing developers with a flexible platform that can be easily adjusted to new data center use cases. Our previous design was targeting a single channel from a single LPDDR4 IC, featuring specially-designed modules to cover for the fact that LPDDR memories aren’t meant to particulary “modular”. For the data center use case however, as reflecting the more standardized nature of that space, the new board can handle a full-fledged, off-the-shelf DDR4 RDIMM with multiple DRAM chips.
+As in the LPDDR4 version, the new board features different interfaces to communicate with the FPGA, such as RJ45 Gigabit Ethernet and a Micro USB console. Additionally, there is an HDMI output connector for development purposes. Other features include:
+What is worth stressing here is that unlike LPDDR4, DDR4 modules don’t have to be custom made and are available to buy off the shelf – an advantage that greatly expands the potential applicability and outreach of the platform.
+
The DRAM tester described here is meant, of course, to be used with the Antmicro open source Rowhammer testing framework mentioned in the opening of this blog note. The list of devices discovered to be vulnerable to attacks so far is significant, and the new design will help to cover a huge chunk of data center oriented memory modules.
+The DRAM testing capabilities of the Rowhammer tester are not limited to DDR4 RDIMM memories and LPDDR4 only. Plans for 2022 include support for LPDDR5 and DDR5, which will result in more hardware and collaborations, and hopefully more mitigation techniques. With an open source DRAM controller at the heart, the framework offers potential of collaboration around building Rowhammer mitigations into the controller itself, using the transparency of open source IP to stay one step ahead of the potential attacks.
+The recent data center security work is part of our wider effort to push open source tooling, methodologies and approach to data center customers. In a similar vein, within the LibreBMC group in OpenPOWER Foundation, we are leading a project to replace ASIC-based BMC (board management controllers) with soft CPUs running on popular and low-cost FPGA platforms. LibreBMC will be a completely transparent security and management solution both in terms of hardware and software and includes two boards compatible with OCP’s DC-SCM standard based on the Xilinx Artix-7 and Lattice ECP5 FPGAs respectively.
+Complementing our software capabilities in scaling huge workloads and building robust design, development, test and CI, simulation and verification pipelines, our data center oriented platforms also include Scalenode, which shows how open source hardware can be used to build modular servers based on both ARM (Raspberry Pi 4 CM) and RISC-V (ARVSOM).
+Our open source based services ranging from ASIC and hardware design through IP and software development lets us offer comprehensive help to a wide array of data center customers, to improve their security, development speed and collaboration capacities.
+The data center DRAM tester is further proof that the open source hardware trend spearheaded by Antmicro can bring practical value, especially in terms of security and collaboration capability. Developing a completely open framework, configurable down to the DRAM controller itself, has led us to some fantastic collaborations and sparked ideas which would otherwise be impossible to implement. Both the CHIPS Alliance, the OpenPOWER Foundation and RISC-V International have a keen interest in taking the memory controller work forward, potentially leading up to ASIC-proven DDR controller IP.
+An open source IP ecosystem which we are actively participating in could revolutionize how ASIC and FPGA systems are built. It is one of the key components in a wider push for a more open source, pragmatic and software-centric approach to hardware that we are helping shape at the global level by participating in policy-making initiatives in the EU and US.
+On a more down-to-earth note, the data center platform is yet another permissively licensed open source board in our arsenal, and can serve as a good reference design for Kintex-7 projects which we are happy to customize and build upon for other areas or types of research for our customers.
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+SystemVerilog is a rich hardware design description and verification language that is seeing increased usage in industry. In the second Deep Dive Cafe Talk by CHIPS Alliance on July 20, Henner Zeller, who is an software developer with Google, provided an excellent in depth technical talk on building out an open source tooling ecosystem around SystemVerilog to provide a common framework that can be used by both functional simulation applications as well as logic synthesis. In case you missed the live presentation, you can watch it here.
+ +Henner started the talk by providing background and motivation for the work on expanding the tooling available for SystemVerilog. It was noted that SystemVerilog is being used by a large cohort in industry, but there is little awareness that open source tools supporting SystemVerilog exist. Of note is that SystemVerilog is analogous to C++ as is Verilog to C in terms of language robustness and complexity. As such, developing a framework and metric-based scorecard to measure the quality of applications supporting this is of importance. A key aspect of adoption of SystemVerilog and associated open source tooling is that it works out of the box. Subsequently, the so-called sv-tests framework was created by Antmicro and Google – and subsequently transferred to CHIPS Alliance – as a unit test system for SystemVerilog tools to assess the quality of the parsing and handling of different attributes of the language. To incentivize participation, a leader board has been created to show quality of results.
+The talk also provided an overview of the different parsers Surelog, sv-parser, and Verible, along with discussion of their positive attributes and limitations. This was followed by presentation of UHDM (Unified Hardware Data Model) – a data model allowing transferring parsed and elaborated SystemVerilog between frontend and simulation or synthesis software.
+An example integration of the UHDM based flow developed collaboratively by CHIPS members Google and Antmicro was presented next. The development aims to integrate the UHDM handling capability with Verilator simulator and Yosys synthesis tools. The work is done publicly in CHIPS Alliance’s GitHub repositories. The UHDM integration tests repository collects all the pieces of the system and allows running the integration tests.
+The development and measurement of different applications to parse SystemVerilog and robustly represent in a common data representation will do much to ensure the development of a solid framework for construction of different design automation tools.
+The next CHIPS Alliance Deep Dive Cafe is on Tuesday, Aug. 10 at 4 p.m. PT. Experts from Intel and Blue Cheetah will present on PHYS, protocols, EDA, and heterogeneous integration as well as latest developments on die-to-die interfacing. You can register for the event here.
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+This post was originally published at Antmicro.
+The ASIC design and manufacturing flow has for a long time been dominated by proprietary tools and processes. The growing complexity of chip-building has been reinforcing the claim that “hardware is too hard to be open source”, as the cost and time needed to build an ASIC have kept small, more agile, software-oriented teams and individuals away from the hardware domain. Thus, ASICs have not been able to benefit from the enthusiasm and collaboration which have been fuelling software development for decades now. Thanks to the continued effort of many entities which Antmicro is very proud to be among, this is now changing quickly.
+The first shift in the walled garden, proprietary chips design landscape came with the creation of the RISC-V Foundation in 2015 centered around the open source RISC-V ISA. Antmicro has been on board as a Platinum Founding Member of the Foundation (now, several hundred members strong, transitioning into a Swiss-based entity called RISC-V International) since the very beginning, as it reflected our belief that an open source approach can – and is bound to, eventually – revolutionize all areas of computing, even the less obvious ones.
+RISC-V proved ASIC design can be a collaborative process, with players big and small working together to compliment each other’s strengths not only in developing the ISA but also many of the tools needed to make it practically useful. For example, Microsemi worked with SiFive to provide the SoC complex at the heart of their new and exciting PolarFire FPGA SoC, and then turned to Antmicro to provide a simulation environment – using our open source Renode Framework – to make development possible before the SoC hits the market later this year. The OpenTitan project, driven by key RISC-V adopters Google and Western Digital together with the UK not-for-profit lowRISC, strives to build a more transparent, trustworthy, high-quality reference design and integration guidelines for silicon Root of Trust chips. Such examples abound in the RISC-V world, but the un-core, design tools, verification and other parts of the ecosystem have mostly remained closed.
+Established in 2019, CHIPS Alliance takes the open, collaborative aspect of RISC-V even further. CHIPS wants to generate and integrate fully open source, high quality IP and tooling for ASIC design; the organization extends beyond cores and specifications, and acknowledges the importance not only of the result but the process itself; thus, the aim is to make both ASICs and the ASIC design processes open source all the way. Why? Again, a lesson learned from software: if you open up to collaboration, adaptation and change on all levels, the long-term results will be surprisingly good.
+CHIPS has been home to such important projects as the Chisel HDL, the Rocket core generator and related tools, the SweRV cores or AIB interconnect. There is work under way to enable fully open source SystemVerilog/UVM support in tools like Verilator and Yosys (with some milestones like fully open source linting, formatting or synthesis of SystemVerilog code already accomplished), opening the door to more open source collaboration around design verification which constitutes the highest cost in modern chip design.
+Also in the tools area, the very ambitious OpenROAD project, also a CHIPS member, is a DARPA-backed activity aiming to create a fully open source, quick, automated digital design flow. If you want to see how open source, automated chip design might look like in the future, see OpenROAD’s excellent ChipKit tutorial from ISCA 2020.
+Aggregating those activities a vastly different landscape begins to emerge, one where chip design can be innovated upon on various levels, and teams can go back and forth between hardware and software optimizations for new use cases such as machine learning without NDAs and costly licences. But – until now – there was one element notably missing.
+We are excited to announce Antmicro’s participation in yet another historic first in the area of semiconductor process technology. In a project led by Google and SkyWater Technology, and in collaboration with partners including Antmicro, Blue Cheetah, efabless and numerous Universities, an open source SkyWater PDK (Process Design Kit) for the 130 nm MOSFET fabrication process, along with related sources, is being made available. This development greatly lowers the cost of entry into chip manufacturing and paves the way for even more exciting collaborations to happen in the open source silicon domain.
+
For some background, a PDK is a set of data files and tools used to model a specific process in a given foundry used with EDA (Electronic Design Automation) tools in the chip design flow. PDKs traditionally have been closed – to the point where some would say it’s impossible to make them open! This collaboration, where Antmicro worked together with Google and efabless to convert the PDK data for the public release, is an important step towards truly open source chips. The 130nm PDK process is a mature technology that is useful for a range of applications, especially in the area of microcontroller development and research as well as mixed signal embedded designs and other use cases which combine digital and analog circuits. The SKY130 technology stack consists of:
+SkyWater is an American technology foundry accredited by the US Department of Defense, which offers custom integrated circuit design and manufacturing services. It is predicted that the launch of the open source SKY130 process node will be followed by other, more advanced nodes, ultimately enabling more advanced processor applications, including ones that are Linux-capable.
+
On Tuesday, June 30 at 16:00 GMT, Google’s Tim Ansell will give a talk at the FOSSi Dial-up meeting, presenting a thorough overview of the technical details of the PDK, as well as outlining the project’s goals and its roadmap. The event will be livestreamed on YouTube and will be followed by a Q&A session, so tune in to find out more about this historic step towards an open, accessible and collaborative chip-making process.
+
+
+As part of CHIPS Alliance’s mission to enable a software-driven approach to silicon, working with Google and other CHIPS members, Antmicro has been developing and improving a growing number of open source tools to enable effective, CI-driven silicon development.
+Fully reproducible and scalable workflows based on open source tooling are especially beneficial for efforts spanning across multiple industrial and academic actors such as Caliptra, a Root of Trust project driven by Google, AMD, NVIDIA and Microsoft which recently joined CHIPS in order to host the ongoing development and provide the necessary structure, working environment and support for the reference implementation of the standard, originally hosted by Open Compute Project.
+In this note, we describe Antmicro and Google’s collaborative effort focused on introducing a Continuous Integration (CI) based code quality checks, code indexing, coverage and functional testing pipeline into the RISC-V VeeR core family, as used within the Caliptra project.
+VeeR (Very Efficient & Elegant RISC-V) is an open source production-grade RISC-V core family hosted by CHIPS Alliance and comes in three variants:
+Caliptra’s hardware block structure with an EL2 VeeR CPU core includes the following elements:
+
As can be seen in the diagram, VeeR EL2 plays a central role in the implementation and, while it is a mature and well-tested technology, keeping both the core itself and its integration with Caliptra consistently tested is important.
+Many of Antmicro’s efforts focus around building not only the end products but the scalable CI solutions for collaborative hardware development environments that power them. Since Caliptra’s needs for establishing a more open process tie in perfectly with Antmicro’s and all of CHIPS Alliance’s open source-based approach to tooling, we gladly utilized our expertise to help advance VeeR, and by extension, the Caliptra project, in that direction.
+One of the core parts of this effort involved Verible, an open source SystemVerilog parser developed by Google in collaboration with Antmicro within CHIPS Alliance, offering a number of code processing functionalities, including linting, formatting, indexing and producing a Kythe schema. Verible comes with a Language Server Protocol which enables integration with popular text editors such as VS Code, Vim, Neovim, Emacs, Sublime, Kakoune and Kate, described in detail in a separate note.
+Antmicro’s work with Caliptra involved adding the Verible formatter to the VeeR CI which marks non-compliant formatting changes and uses the reviewdog bot to add comments in the Pull Request Discussion with suggested fixes. Furthermore, we added a Verible linting Action that helps developers maintain good coding practices by providing lint rules for continuous validation of the code, before it even reaches the compilation phase. Notably, the provided lint rules are flexible and can be adjusted based on the project’s requirements, or even turned off completely through creation of a waiver-file or by an inline directive.
+
Thanks to Verible’s ability to output a Kythe schema, besides linting and formatting code changes we can also provide an indexed overview of the entire codebase, viewable online. The Kythe Verible Indexer, using Verible Indexing Action, enables the user to select multiple repositories to create a set of indexed webpages.
+
The workflow also checks if a newer revision is available for any of the defined repositories and, if needed, performs indexing. The indexed code browser webpages were deployed for Cores-VeeR-EL2 and Caliptra-rtl.
+
The riscv-dv framework is another tool hosted by CHIPS Alliance helping address the complexities of SoC design and verification. It is an SV/UVM based open source instruction generator for RISC-V processors, originally developed for Google’s own needs but currently in use by a wide array of organizations and companies working with verification of RISC-V cores.
+The riscv-dv framework generates random instruction chains to exercise certain core features. These instructions are then simultaneously executed by the core (through RTL simulation) and by a reference RISC-V ISS (instruction set simulator), for example Spike or Renode, Antmicro’s open source simulation framework.
+Core states of both are then compared after each executed instruction and an error is reported in case of a mismatch.
+
While working on the Caliptra project, Antmicro introduced the riscv-dv framework for testing the VeeR-EL2 core as well as a GH Actions CI flow which builds or downloads all the dependencies (Verilator, Spike, VeeR-ISS and Renode) and runs the tests. For the purpose of using riscv-dv with VeeR we had to write a VeeR-specific execution trace log parser. The task of this parser is to translate the log to the format understandable by the riscv-dv framework.
+As an interesting detail, VeeR implements division (div) and remainder (rem) instructions in a way it delegates the calculations to the division logic and proceeds with the execution of the program. Once the division core ends, the result is written back to the div/rem instruction result register. This flow takes into account the situation where any instruction following div/rem requires the div/rem result. In such cases the pipeline is stalled until the result is available. If any instruction following div/rem overwrites the result register before division logic finishes, the division operation is canceled.
+To handle the case where the division results are available after a few other instructions were executed we’ve developed a lazy parsing method of the VeeR trace log to be able to catch the result register update even if it is not immediate. The second case - cancellation of the division calculation has been handled by adding a code post-processing script. It can detect a situation where a cancellation would happen and prevent it by injecting a number of the NOP instructions (allowing the division core to finish).
+Much like a large part of the industry, the Caliptra project uses Universal Verification Methodology (UVM) as its verification methodology. While Antmicro’s ongoing work on enabling fully open source UVM support in Verilator should ultimately enable completely open source verification, today UVM testbenches or tools like RISC-V DV cannot be run using open source tools only.
+Fortunately, this problem already has a solution, also developed within the CHIPS Alliance - custom GitHub Actions Runners that are already in use by a large number of CHIPS projects.
+A custom runner setup, currently in development for Caliptra, allows mixing and matching open and closed source tools for CI testing purposes, exposing only the results (such as pass/fail or coverage) with fine-grained control.
+What is more, given that RTL design testing and verification of RISC-V based cores and SoCs often require long, memory-consuming and computationally demanding simulations, the custom runners will play another very important role in Caliptra. While GitHub is the obvious choice for hosting the reference RTL, the processing power and throughput of the CI machines available in GitHub Actions is simply not enough to cover the needs of simulation of complex designs, especially in a highly dynamic, collaborative environment with lots of CI angles.
+In order to enable public-facing yet secure CI, and improve the flexibility and scalability of Caliptra’s/VeeR’s pipelines, the custom runners will be deployed for the respective repositories. This setup will enable us to precisely select machines to be used for specific workloads (i.e. the architecture, virtual CPU count, memory size and disk space) but also to use tools stored on an external cloud disk that can be attached to a virtual machine running the job workload.
+The Caliptra SoC is meant as a macro for use in a variety of chip designs, big and small. Various teams adopting Caliptra/VeeR as their Root of Trust solution will need to plug it into a larger ecosystem of tools used in their organization (of course hopefully using Caliptra as a good reference and role model).
+As part of the project, on top of the original Caliptra test suite we’re implementing more specific tests around the VeeR integration in cocotb, a co-simulation testbench library that enables connecting Python coroutines with your HDL simulator of choice. We’re currently working on a cocotb testbench that will be able to not only run programs from the generator, but also apply dedicated stimuli and monitor the results in a Python coroutine.
+Furthermore, for projects who prefer a more UVM-like testing methodology but need an open source option today, we also provide some example tests using pyuvm, a Pythonic library that mirrors the industry accepted SystemVerilog implementation. We have implemented a minimal UVM Agent for the programmable interrupt controller of the VeeR-EL2 Core, which will be used to verify handling of the interrupt service routines triggered by external or local-to-core timer interrupts. The verification environment is expected to grow as more test cases could be added, covering the DMA controller, close coupled memory buses or the debug interface.
+For system level tests we decided to connect to an interactive simulation of the complete design via JTAG with commonly used tools: Open On-Chip Debugger (OpenOCD) and the GNU Project Debugger (GDB). The simulation exposes a virtual JTAG port, which is used to establish a connection with OpenOCD. Then the OpenOCD instance connects to the GNU debugger. Finally, test scripts are run in GDB, which verify core registers content, memory access and peripheral accesses.
+With this testing methodology we exposed an actual problem in the design which prevented accessing system peripherals via JTAG. As it turned out the issue was caused by the side AHB bus of the debug core being disconnected.
+
Once a connection of the side bus had been made it became possible to access all the peripherals. A 2-to-1 AHB multiplexer was used to join the system and side AHB master ports and forward requests to the peripherals.
+To verify the effectiveness of all kinds of tests, both ISS and RTL level, and help ensure that all design states are properly tested, we use coverage analysis. While open source tools and frameworks have some support for gathering and presenting these metrics, e.g. Verilator supports line, toggle and functional coverage, some additional work needs to be done to integrate all of those and present them in a comprehensive, visual form, which will be part of our future efforts.
+In addition to the efforts described in this note, CHIPS Alliance community’s other work, including Antmicro’s improvements to Verilator to better handle large designs and verification tasks, help bring more open source-driven development and verification solutions to the Caliptra project and the entire open hardware ecosystem.
+To learn more about ideas and concepts of Caliptra and VeeR, join the next CHIPS Alliance Technology Update on July 13, either virtually or on-site at Google Spear Tower, San Francisco. You can also actively participate in expanding the Caliptra project by joining the CHIPS Alliance Caliptra Workgroup.
+If you’re interested in benefiting from this software-driven approach to silicon development or would like to find out how to develop and verify your next production-grade ASIC project using the constantly expanding open source tooling ecosystem, reach out at contact@antmicro.com.
+
+
+This post was originally published at Antmicro.
+Open source hardware is undeniably undergoing a renaissance whose origin can be traced to the establishment of RISC-V Foundation (later redubbed RISC-V International). The open ISA and ecosystem, in which Antmicro participated since the beginning as a Founding member, has sparked many open source CPU implementations but also new tooling, methodologies and trends which allow for more collaborative and software driven design.
+Many of those broader open hardware activities have been finding a home in CHIPS Alliance, an open source organization we participate in as a Platinum member alongside Google, Intel, Western Digital, SiFive and others, whose goals explicitly encompass:
+This is in perfect alignment with Antmicro’s mission, as we’ve been heavily involved with many of the projects inside of and related to CHIPS, providing commercial support and engineering services – and assistance in practical adoption for enterprise deployments.
+As of this time, a range of everyday design, development, testing and verification tasks are already possible using open source tools and components and are part of our and our customer’s everyday workflow. Other developments are within reach given a reasonable amount of development, which we can provide based on specific scenarios. Others still are much further away, but with dedicated efforts inside CHIPS in which we are involved together with partners like Google and Western Digital there is a pathway towards a completely open hardware design and verification ecosystem. This will eventually unlock incredible potential in new design methodologies, vertical integration capabilities, education and business opportunities – but until then, practical value can already be extracted today for many scenarios such as simulation, linting, formatting, synthesis, continuous integration and more, and Antmicro can help you do that.
+Some of the challenges towards practical adoption of open source in ASIC design have been related to the fact that a significant proportion of advanced ASIC design is done in SystemVerilog, a fairly complex and powerful language in its own right, which used to be poorly supported in the open source tooling ecosystem. Partial solutions like SystemVerilog to Verilog converters or paid plugins existed, but direct support lagged behind, making open source tools for SystemVerilog a difficult sell previously.
+This has been fortunately changing rapidly with a dedicated development effort spearheaded by Google and Antmicro. Projects in this space include Verible, Surelog, UHDM and sv-tests which we have been developing as well as integrating with existing tools like Yosys, Verilator under the umbrella of the SymbiFlow open source FPGA project, and which are now officially being transferred into the CHIPS Alliance to increase awareness and build a broader SystemVerilog ecosystem around them. In this note, we will walk you through the state of the art in new SystemVerilog capabilities in open source projects, and invite you to reach out to see how CHIPS Alliance’s SystemVerilog projects can be useful to you today or in the near future.
+
The Verible project originated at Google, and its main mission is to make SystemVerilog easily and quickly parsable for a wide variety of applications mostly focusing on developer tools.
+Verible is a set of tools based on a common SystemVerilog parsing engine, providing a command line interface which makes integration with other tools for daily usage or CI systems for automatic testing and deployment a breeze.
+Antmicro has been involved in the development of Verible since its initial open source release and we now provide a significant portion of current development efforts, helping adapt it for use in various open source projects or commercial environments that use SystemVerilog. One notable user is the security-focused OpenTitan project, which has driven many interesting developments and provides a good showcase of the capabilities, being completely open source, well documented, fairly complex and used in real applications.
+One of the most common use cases for Verible is linting. The linter analyzes code for patterns and constructs that are deemed undesirable according to the implemented lint rules. The rules follow authoritative style guides that can be enforced on a project or company level in various SystemVerilog projects.
+The rules range from simple ones like making sure the module name matches the file name to more sophisticated like checking variable naming conventions (all caps, snake case, specific prefix or suffix etc.) or making sure the labels after the begin and end statements match.
+A full list of rules can be found in the Verible lint documentation and is constantly growing. Usage is very simple:
+$ verible-verilog-lint --ruleset all core.sv
+core.sv:3:11: Interface names must use lower_snake_case naming convention and end with _if. [Style: interface-conventions] [interface-name-style]
+The output of the linter is easy to understand, as the way issues are reported to the user is modeled after popular programming language compilers.
+The linter is highly configurable. It is possible to select the rules for which the compliance will be checked, some rules allow for detailed configuration (e.g. max line length).
+Rules can also be selectively waived in specific files or at specific lines or even by regex matching. In addition, some rules can be automatically fixed by the linter itself.
+The Verible formatter is a complementary tool for the linter. It is used to automatically detect various formatting issues like improper indentation or alignment. As opposed to the linter, it only detects and fixes issues that have no lexical impact on the source code.
+The formatter also comes with useful helper scripts for selective and interactive reformatting (e.g. only format files that changed according to git, ask before applying changes to each chunk).
+A toolset that consists of both the linter and the formatter can effectively remove all the discussions about styling, preferences and conventions from all pull requests. Developers can then focus solely on the technical aspects of the proposed changes.
+$ cat sample.sv
+typedef struct {
+bit first;
+ bit second;
+bit
+ third
+ ;
+ bit fourth;
+bit fifth; bit sixth;
+}
+ foo_t;
+
+
+$ verible-verilog-format sample.sv
+typedef struct {
+ bit first;
+ bit second;
+ bit third;
+ bit fourth;
+ bit fifth;
+ bit sixth;
+} foo_t;
+The Verible parser itself can be relatively easily used to perform many other tasks. One of the interesting use cases is generating a Kythe compatible indexing database.
+Indexing a SystemVerilog project makes it very easy to collaborate on a project remotely. +It is possible to navigate through the source code using nothing else than just a web browser.
+The Kythe integration can be served on an arbitrary server, can be deployed after every commit in a project, etc. A showcase of the indexing mechanism can be found in our GitHub repository. The demo downloads the latest version of the Ibex core, indexes it, and deploys it to be viewed on a remote machine. +The results can be viewed on the example index webpage.
+
Indexing is widely adopted for many larger open source software projects.
+Thanks to Verible it is now possible to do the same in the world of open source HDL designs, and of course private, company-wide deployments like this are also possible.
+SystemVerilog is a powerful language, but it is also complex. That is why so far no open source tools have been able to support it in full. Implementing it separately for each project such as the Yosys synthesis tool or the Verilator simulator would take a colossal amount of time, and that’s where Surelog and UHDM come in.
+Surelog, originally created and led by Alain Dargelas, aims to be a fully-featured SystemVerilog 2017 preprocessor, parser, and elaborator. It’s a modern tool and thus follows the current version of the SV standard without unnecessary deviations or legacy baggage.
+What’s interesting is that Surelog is only a language frontend designed to integrate well with other tools – it outputs an elaborated design in an intermediate format called UHDM.
+UHDM stands for Universal Hardware Data Model, and it’s both a file format for storing hardware designs and a library able to manipulate this format. A client application can access the data using VPI, which is a standard programming interface for SystemVerilog.
+What this means is that the work required to create a SystemVerilog parser only needs to be done once, and other tools can use that parser via UHDM. This is much easier than implementing a full SystemVerilog parser within each tool. What’s more, any improvements in the unified parser will provide benefits for all client applications. Finally, any other parser is free to emit UHDM as well, so in the future we might see e.g. a UHDM backend for Verible.
+Just like in Verible’s case, both Surelog and UHDM have recently been contributed into CHIPS Alliance to drive a broader adoption. We are actively contributing to both projects, especially around the integrations with tooling such as Yosys and Verilator and practical use in open source and customer projects.
+Recent Antmicro contributions adding UHDM frontends for Yosys and Verilator enabled Ibex synthesis and simulation. The complete OpenTitan project is the next milestone.
+The Surelog/UHDM/Yosys flow enabling SystemVerilog synthesis without the necessity of converting the HDL code to Verilog is a great improvement for open source ASIC build flows such as OpenROAD’s OpenLane flow (which we also support commercially). Removing the code conversion step enables the developers to perform e.g. circuit equivalence validation to check the correctness of the design.
+More information about Surelog/UHDM and Verible can be found in a dedicated CHIPS Alliance presentation that was recently given by Henner Zeller, Google’s Verible lead.
+No open source ASIC design toolkit can be complete without support for Universal Verification Methodology, or UVM, which is one of the most widespread verification methodologies for large-scale ASIC design. This has also been an underrepresented area in open source tooling and changing that is an enormous undertaking, but working together with our customers, most notably Western Digital, we have been making progress on that front as well.
+Across the ASIC development landscape, UVM verification is currently performed with proprietary simulators, but a more easily distributable, collaborative and open ecosystem is needed to close the feedback loop between (emerging) open source design approaches and verification. Verilator is an extremely popular choice for other system development use cases but it has historically not focused on UVM-style verification. Other styles of verification, such as the very interesting and popular Python-based cocotb framework maintained by FOSSi Foundation have been enabled in Verilator – we write about our own work around that in a dedicated blog note. But support for UVM, partly due to the size and complexity of the methodology, has been a notably absent.
+One of the features missing from Verilator but needed for UVM is SystemVerilog stratified scheduling, which is a set of rules specified in the standard that govern the way time progresses in a simulation, as well as the order of operations. In short, a SystemVerilog simulation is divided into smaller steps called time slots, and each time slot is further divided into multiple regions. Specific events can only happen in certain regions, and some regions can reoccur in a single time slot.
+Until recently, Verilator had implemented only a small subset of these rules, as all scheduling was being done at compilation time. Spearheading a long-standing development effort within CHIPS Alliance, in collaboration with the maintainer of Verilator, Wilson Snyder, we have built is a proof-of-concept version of Verilator with a dynamic scheduler, which manages the occurrence of certain events at runtime, extending the stratified scheduling support. More details can be found in Antmicro’s presentation for the inaugural CHIPS Alliance Deep Dive Cafe Talk.
+Another feature required for UVM is constrained randomization, which allows generating random inputs to feed to a design in order to thoroughly test it. Unlike unconstrained randomization, which is already provided by Verilator, it allows the user to specify some rules for input generation, thus limiting the possible value space and making sure that the input makes sense. Work on adding this to Verilator has already started, although the feature is still in its infancy. There are many other features on the roadmap which will eventually enable practical UVM support – stay tuned with our CHIPS Alliance events to follow that development.
+Support for SystemVerilog parsers, for the intermediate format, and for their respective backends and integrations with various tooling as well as for UVM is now under heavy development. If you would like to see more effort put into a specific area, reach out to us at contact@antmicro.com. Antmicro offers commercial support services to extend the flows we’ve briefly presented here to various practical applications and designs, and to effectively integrate this approach into people’s workflows.
+Adding to this our cloud expertise, Antmicro customers can benefit from a complete and industry-proven methodology scalable between teams and across on-premise and cloud installations, transforming chip design workflows to be more software-driven and collaborative. To take advantage of open source solutions with tools like Verilator, Yosys, OpenROAD and others – tell us about your use case and we will see what can be done today.
+If you are interested in collaborating on the development SystemVerilog-focused and other open hardware tooling, join CHIPS Alliance and participate in our workgroups and help us push innovation in ASIC design forward.
+
+
+Note: the open source test suite will be demonstrated at the CHIPS Alliance booth at the RISC-V Summit 2019 – join us Dec 10-12 in the San Jose Convention Center!
+USB is often a daunting topic for developers, and implementing support for it from scratch is a time consuming task. When the expected result is more complicated than a USB-to-serial bridge, the solution would be to either use a hardware transceiver or, especially for older USB standards, use an open source core to implement one directly in the FPGA fabric. But which core to use?
+There are many different USB IP cores available, implemented in languages ranging from traditional HDLs like Verilog to modern alternatives like migen (or its new variant, nmigen). Most of them come with their own set of test cases, often checking their internal mechanisms and not corresponding directly to those in other projects. What was lacking is a unified test suite that would run each core through the same set of scenarios, providing a direct, apples-to-apples comparison of their behavior.
+A solution from Antmicro, a CHIPS Alliance Gold member, is an open source test suite for USB IP cores, available on their Github. It currently supports USB1.1 and will be extended for higher revisions in the future.
+In the test suite, Antmicro is making use of several open source technologies that they have come to appreciate through other projects. The tests are implemented using Cocotb and the low-level details are handled by the newly created cocotb_usb package. This means that even complicated tests, like those that verify the enumeration procedure under different OSes can be written with easy to understand, Python syntax.
+from cocotb_usb.harness import get_harness
+from cocotb_usb.device import UsbDevice
+from cocotb_usb.descriptors import Descriptor
+
+@cocotb.test()
+def test_enumeration(dut):
+ harness = get_harness(dut)
+ yield harness.reset()
+ yield harness.connect()
+
+ yield Timer(1e3, units="us")
+
+ yield harness.port_reset(1e3)
+ yield harness
+ .get_device_descriptor(response=model
+ .deviceDescriptor.get())
+
+ yield harness.set_device_address(DEVICE_ADDRESS)
+As the various IP cores often provide different interfaces towards the user, from different kinds of FIFOs to expected signals to drive the bidirectional USB pins, they are wrapped in a unified layer to create a simple SoC, also written in Python using LiteX. It provides various helper blocks and takes care of the bus infrastructure, clocking and reset logic, generating Verilog output for the whole system ready to be tested under any number of open source simulators. A minimalistic testbench file provides a unified interface as the top object for the simulation.
+
At the heart of the test suite is cocotb_usb, a Python package providing API for sending and receiving various USB packets, handling low-level bus states, verifying descriptor contents and checking timings. This is done by providing a UsbTest object that acts as a host and interacts with the device under test. Depending on your needs, you can output single packets, use whole transactions with e.g. automated retries upon receiving “not acknowledged” tokens, or just use high-level functions like get_config_descriptor() and let the library handle all the details. Meanwhile, the UsbDevice class provides means to store all of the descriptors that the core can report in an organized way.
The test results can be viewed in a standard Cocotb XML results file, the behavior of all signals in the system at all points can be checked in a VCD signal dump (to be viewed e.g. in GTKWave) and we use open source sigrok decoders to obtain packets and transactions, to be exported for viewing in Wireshark.
+
Currently tested cores are:
+So, what tests are supported? They range from a simple control packet handling with both single and multiple transfers, through handling SOF packets, validating clock recovery in the presence of an imperfect clock signal, to complex enumeration scenarios under Linux, Windows 10 and macOS. There are also some special cases, like testing the ValentyUSB core without a CPU by configuring it through a Wishbone bus, or verifying behavior of the TinyFPGA-Bootloader by using CDC transfers to send a boot command to the core.
+While full blown documentation is coming soon, there are ways to get involved right now:
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+Zvonimir Bandic wears lots of hats. He is the Senior Director of Hardware Platforms for Western Digital; he’s a Member of the Board of Directors for the RISC-V Foundation, and he’s the Chairman of the Chips Alliance. It’s that latter capacity that we discussed in this week’s Five Minutes With…discussion. The organization focuses on things like open source hardware, software tools, RTL development, and related topics. They will be holding their inaugural workshop in just a few weeks, so it was timely to understand the purpose of the Alliance. And now I do, as will you.
+ +
+
+Verilator is a shining example of a widely-accepted open source tool which provides state-of-the-art results in the ASIC design space. It is commonly used for simulation and testing, but originally, due to the lack of capability to run event-driven simulations, Verilator wasn’t even considered capable of handling UVM (Universal Verification Methodology) testbenches implemented in SystemVerilog which require scheduling and other features notably absent from the tool. For some time now, Antmicro, together with Western Digital, Google and others in the CHIPS Alliance, has been working on enabling fully open source support for SystemVerilog UVM testbenches in Verilator. This has already resulted in significant breakthroughs we have described in this blog, such as implementing event-driven simulation capabilities in Verilator which has enabled new and exciting use cases. Since then, on the road to proper UVM testbench support, Antmicro has been working on adding various SystemVerilog constructs and UVM-specific elements into Verilator, which bring us much closer to the goal - the current status and next goals will be described in more detail in this blog note.
+
In the usual CHIPS Alliance fashion, in order to track progress in this long-term project and catch potential regressions, a custom test suite and dashboard was created to provide a concise overview of the current status and some statistics for the tests being executed. This is both informative and motivating, as ticking off consecutive corner cases is a tangible measure of progress. Potentially, this also makes it easy to provide new input to the effort in the form of test cases (e.g. SystemVerilog constructs or elements of testbenches that are known not to work) that need to be addressed, without the necessity to touch the internals of Verilator itself.
+Thanks to a tight collaboration with Verilator maintainers, as well as a clean and traceable development methodology, many features and improvements outlined in this article, along with the event-driven simulation capability, are now part of Verilator 5.0, which opens the road to eventual mainline UVM support.
+
A significant part of Antmicro’s efforts involved expanding features that were implemented in Verilator to some extent, but missing specific corner cases or syntactic capabilities. That was the case for concurrent assertions, which are checked with each clock cycle and return true if a certain signal change/state happened. In addition to assertions themselves, we added value sampling. As all sampled value functions are defined in Verilator in terms of the $past function, we focused on this one first, and ultimately ended up adding support for the following keywords:
$rose$fell$changed$stable$pastAlong with sampling improvements, we also added support for the “not” keyword and named properties in assertions.
+Another improvement involved $test$plusargs: Verilator did not support expressions (e.g. arbitrary string concatenation) in the arguments of the $test$plusargs statement - it worked only for string literals for argument names, whereas now it works for arbitrary string-type expressions:
string bar = "bar";
+$test$plusargs({"foo",bar,"baz"});
+Previously, Verilator had only rudimentary support for classes, however many of the more specific features were not supported. In UVM, class constructors often end with the return keyword, and in those cases Verilator returned an error due to a missing return type. Antmicro provided a fix for that, along with an improvement to the way super.new() calls are handled - some of the UVM classes contained constructors with arguments and when a child class called this constructor explicitly using super.new(), Verilator reported an error. This improvement is necessary to make it possible to inherit from a base class that has a constructor with arguments.
We’ve also added the possibility to use a foreach loop with an object type of string, as shown in the example below:
function foo;
+ string bar;
+ foreach (bar[i])
+ $display(bar[i]);
+endfunction
+The do while loop was also lacking support for the break and continue keywords, which required changes to how this kind of loop was processed.
Although Verilator supported the unique method, it did not support it with the with keyword. This keyword is used for specifying lambda-like constructs and is now supported in unique, unique_index, min and max in queues. The with keyword is now also supported for queue methods in some contexts, namely when accessing members of complex types and passing queue elements to functions.
Lastly, Verilator had rudimentary support for randomization using the randomize method, there was no support for constrained randomization - constraint declarations were silently ignored. To support them, the CRAVE library was extended and heavily adapted to mainline Verilator as a common frontend for several solvers. This enabled support for several cases:
with clauses can be used to define dynamic constraints.Note that adding full support for constrained randomization is a significant effort and the partial support has not been mainlined yet. If you still want to give this feature a try before it’s fully ready, you can use our fork which includes it.
+On top of the improvements mentioned above, we have also identified and implemented new features that can benefit Verilator and its users. For designs and testbenches we are working with, there are specific signal types that were not supported by Verilator. For example, we’ve added support for wildcard associative arrays (using wildcard index).
+So far, Verilator only supported packed struts which cannot contain various types within them e.g. strings. We have now added support for unpacked structs and for the --structs-packed flag, allowing for their different memory layout as well as various types.
Another feature that we added to Verilator is support for virtual interfaces, which are required by UVM. Virtual interfaces are “pointers” to interfaces, their value represents an instance of the interface. That’s also the only way to access interfaces from within classes in SystemVerilog (an interface instance cannot be defined in class).
+UVM makes extensive use of built-in classes provided by the std package. Until recently, Verilator didn’t allow instantiating classes defined outside the current package. The example below shows usage of the “foo” class which is outside of the “bar” package, which would not work before our changes.
class foo;
+endclass
+
+package bar;
+ function foo get_foo;
+ foo baz = new;
+ return baz;
+ endfunction
+endpackage
+There were several outstanding issues in Verilator where the this keyword used as a reference or function argument was unsupported - they are now fixed. Verilator also lacked support for some of the classes present in the std package, namely std::semaphore and std::mailbox (parametrized variant), which are used in several places in the UVM library. Both classes are now supported.
Parameterized classes are the backbone of UVM. A significant portion of custom objects definitions in UVM is based on parameterized classes. Verilator did not support parameters in classes at all but thanks to the improvements introduced by Antmicro, the following parameterization features have been implemented:
+Signal strengths are used for so-called “conflict resolution”. Very basic signal strength support has been added to Verilator, including the following features:
+constp doesn’t have user1p().The improvements and additions described in this note, combined with Antmicro’s work on scaling Verilator even for very large designs and other efforts within CHIPS Alliance, are moving us one step closer to the next significant milestone, running the first SystemVerilog UVM testbench through Verilator. However, there are still some features that need to be added in order for some basic UVM testbenches to pass. These include the built-in process class, srandom class method, static local variables, recursive function/task calls, zero delays, constraint_mode method, more complete randomize(...) function support and more thorough type-parameterized classes support. You can watch Michael Gielda’s presentation from CHIPS Alliance Fall Technological Update 2022 in which he provides an overview of UVM support in Verilator. With upcoming new developments within this area, we will be posting more updates in the near future.
Antmicro’s other goals for the future include work with open source projects like Caliptra, which now has a dedicated CHIPS Alliance Workgroup, and further supporting instruction stream based verification frameworks like RISC-V DV.
+Reach out at contact@antmicro.com to learn more about Antmicro’s efforts related to open source tools for ASIC development and how they can be implemented into your workflow, whether it’s based on UVM or not.
+
+
+Originally issued by QuickLogic, the following press release announces the QORC initiative including the world’s first vendor-supported open FPGA toolchain using SymbiFlow, and describes the contribution of CHIPS Alliance members Antmicro and Google.
+San Jose, CA – June 16, 2020 – QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, today announced its ground breaking QORC (QuickLogic Open Reconfigurable Computing) initiative, making it the first programmable logic vendor to actively embrace a fully open source suite of development tools for its FPGA devices and eFPGA technology. This initiative engenders the emerging trend toward open source tooling, significantly broadens access to the company’s products, and enables both hardware and software developers with tools supported by both the user community and QuickLogic.
+
The company’s initial open source development tools, developed by Antmicro in collaboration with QuickLogic and Google, include complete support for its EOS S3 low power voice and sensor processing MCU with embedded FPGA, and its PolarPro 3E discrete FPGA family. Support for additional QuickLogic products, including QuickAI and support for its eFPGA IP offering will be added over the next few months.
+EOS S3 Open Source Development Tools:
+Traditionally, programmable logic vendors offered and supported only proprietary synthesis, place and route tools. Open source tools were relegated to hobbyists, academics, and independent consultants. However, the electronics industry is starting to see a shift toward open sourced hardware and software as it provides flexibility, vendor and community support, longevity, and adaptability to each engineer’s design flow. Google and Antmicro have been noteworthy influencers in this market, increasing the breadth of supported architectures and quality of results for the open source tools. They are now not only viable but desirable for the majority of the development community, including design teams at many of the industry’s largest companies.
+“QORC is QuickLogic’s initiative to embrace the rapidly growing open source FPGA tooling ecosystem, inspiring engineers to collaborate on the creation of exciting and innovative products,” said Brian Faith, QuickLogic’s president and CEO. “We believe that the wide adoption of open source tools represents a paradigm shift for the industry, and we’re proud to be at the leading edge.”
+“With its open source-centered approach, Antmicro has been moving the technological frontier, building whole ecosystems of non-proprietary solutions and overcoming the limitations inherent in closed technologies,” said Michael Gielda, Antmicro’s VP of Business Development. “We’ve been excited to participate in this historical first from QuickLogic, by contributing our expertise in software, hardware and tools to implement the necessary SymbiFlow, Renode and Zephyr support for their hardware platform – broadening their reach within the developer community.”
+SymbiFlow FPGA, Renode SoC Emulation, and Zephyr RTOS support are available now for QuickLogic’s EOS S3 voice and sensor processing platform and PolarPro 3E FPGA products, as well as the new QuickFeather Development Kit. Support for QuickLogic’s embedded FPGA technology will be added later this year. To learn more, please visit www.quicklogic.com/QORC.
+QuickLogic Corporation (NASDAQ: QUIK) is a fabless semiconductor company that develops low power, multi-core semiconductor platforms and Intellectual Property (IP) for Artificial Intelligence (AI), voice and sensor processing. The solutions include embedded FPGA IP (eFPGA) for hardware acceleration and pre-processing, and heterogeneous multi-core SoCs that integrate eFPGA with other processors and peripherals. The Analytics Toolkit from our recently acquired wholly-owned subsidiary, SensiML Corporation, completes the end-to-end solution with accurate sensor algorithms using AI technology. The full range of platforms, software tools and eFPGA IP enables the practical and efficient adoption of AI, voice, and sensor processing across mobile, wearable, hearable, consumer, industrial, edge and endpoint IoT. For more information, visit www.quicklogic.com and https://www.quicklogic.com/blog/.
+QuickLogic and logo are registered trademarks and EOS and SensiML are trademarks of QuickLogic. All other trademarks are the property of their respective holders and should be treated as such.
+Press Contact:
+Andrea Vedanayagam
+Veda Communications
+408.656.4494
+pr@quicklogic.com
+
+QuickLogic to present at the virtual CHIPS Alliance Workshop on Sept. 17
+SAN FRANCISCO, Aug. 11, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, has joined as its newest member.
+“Over the past few years the electronics industry has seen a big shift towards open source hardware and software, and we’re proud to be one of the companies at the forefront of that movement,” said Brian Faith, president and CEO at QuickLogic. “We have already been working closely with several CHIPS Alliance members to make FPGA tools and devices more accessible, and we look forward to continuing these efforts as an official member of the organization.”
+QuickLogic recently announced the QuickLogic Open Reconfigurable Computing (QORC) initiative to broaden access to open FPGA technology for embedded systems developers. QuickLogic’s initial open source development tools, developed in collaboration with CHIPS Alliance members Antmicro and Google, include complete support for QuickLogic’s EOS S3 low power voice and sensor processing MCU with an integrated embedded FPGA (eFPGA), and its PolarPro 3E discrete FPGA family.
+Additionally, QuickLogic and Antmicro launched the first fully open source ArmⓇ CortexⓇ M4 MCU + eFPGA SoC dev kit, QuickFeather™. Antmicro added support for the QuickFeather dev kit into the Zephyr Real Time Operating System (RTOS), as well as in its open source Renode simulation framework. This small form factor development board is ideal for low-power machine learning (ML) capable IoT devices.
+Said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance: “The CHIPS Alliance is continuing to focus on expanding its member base with organizations from a diverse set of industries. QuickLogic, a leader in open source eFPGA IP and FPGA tooling, will help us drive innovation in the FPGA sector and further our mission to remove barriers for open hardware design.”
+QuickLogic’s Brian Faith will present “Open Source FPGA Tooling, Our Journey from Resistance to Adoption” at the CHIPS Alliance Workshop, being held virtually on Thursday, September 17.
+To see the full CHIPS Alliance Workshop schedule and register for the event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
+
+We recently held our fall 2021 CHIPS Alliance workshop with nearly 160 attendees present for informative seminars covering a range of topics including porting Android to RISC-V, open source ASIC design and FPGA tooling, and OmniXtend. In case you missed the talks, a replay is available on the CHIPS Alliance YouTube channel.
+During the seminar, we had eight exciting technical presentations, including:
+Each of these talks provided informative, technical details of key aspects of the work underway by members of CHIPS Alliance who are working in an open, collaborative fashion. Of particular interest are the following topic areas:
+ +The presence of RISC-V is significantly growing, thanks in part to its applicability for the IoT, mobile market, and even the data center. Alibaba shared its experience porting the Android operating system to RISC-V, discussing their challenges and successes, and what is needed to help build out the ecosystem for the RISC-V ISA.
+Design Languages: Practical Adoption of Open Source SystemVerilog Tools, and Chisel and FIRRTL for Next Generation SoC Designs
+These two talks showcased the continuing efforts to build robust support for different design description languages.
+In the first talk, Antmicro provided an overview on the latest developments in open source SystemVerilog tooling, covering the construction of the ecosystem and efforts to support SystemVerilog more robustly, including the creation of a Universal Hardware Data Model (UHDM), continued support of two industry-grade SystemVerilog parsers – Surelog and Verible – as well as a set of tests and scoreboard to determine the quality of different SystemVerilog applications and work towards UVM support in Verilator.
+From CI-assisted linting and formatting to fully open source synthesis and simulation, the talk pointed out that adding SV support to open ASIC design flows is a way to make emerging ecosystems such as OpenLANE/OpenROAD work with the growing number of designs described in this language (e.g. OpenTitan’s Ibex/Earl Grey, OHG’s Core-V, University of Washington’s BlackParrot, or CHIPS Alliance’s SWeRV). The future of open ASIC design, as spearheaded by members of CHIPS, will be pluralistic.
+The talk on Chisel and FIRRTL updated the community on the progress with the Chisel design language, which is based upon Scala. For those who are unfamiliar, this introduces object oriented design concepts and expression to a hardware design language. Similar to what occurred in software, the introduction of object oriented concepts serves to increase the productivity of a hardware design engineer. FIRRTL provides a hardware compiler for a design described in Chisel. A key feature of this is the ability to natively embed formal verification as part of the design, which is typically a difficult task. FIRRTL also enables target output to different applications including Verilator for functional verification, OpenROAD for physical implementation, and for FPGA emulation.
+FPGA Tooling Interoperability with the FPGA Interchange Format
+Over the past few years, FPGAs have become a strategic component in the arsenal of different computational platforms, from labs and desktops to datacenters. Their flexibility to be dynamically reconfigured based upon updates to underlying changes in the hardware design and its emulation make them very helpful for rapid prototyping of new ideas and quickly moving into production. This has been a tremendous benefit for the rapid development and deployment of new machine learning algorithms and their usage in the datacenter.
+This talk discussed work to provide a common open device and design representation format, enabling various FPGA design toolchains (both open source and proprietary) to seamlessly interoperate in a design build task. With the Interchange format in place a designer can choose between tools available in different toolchains (e.g. place design with an open source flow, and later route it with a proprietary one).This will enable different companies, universities, and individuals to focus on research and development on a certain part of the flow, without the necessity of implementing the whole toolchain at once.
+ +This session highlighted the progress of the joint working group with RISC-V International on the cache coherency project, which is making the protocol extensible to a family of participant devices. The talk started with a brief tutorial on the nature of OmniXtend. This update specifically highlighted the extension of OmniXtend to be able to dynamically detect the addition or subtraction of devices to the shared bus between intelligent devices. This 1.1 version of the protocol will be fully released under the Apache 2.0 license in Github.
+Open Source NVME IP with AI Acceleration
+This talk discussed the need for machine learning accelerators in proximity to data storage. The talk covered the overall architecture of a data-centric, parallel processing system developed by Antmicro in collaboration with Western Digital, including FPGA implementation of the NVMe core and software architecture with Zephyr RTOS running on the Cortex-R5 RPU and Linux on the Cortex-A53 core of the Xilinx UltraScale MPSoC chip. Both systems use OpenAMP for asynchronous communication, allowing the RTOS to handle base NVMe commands and delegate the rest to the Linux application. To speed up ML algorithm inference, VTA (an open source FPGA AI accelerator) was employed. The ML algorithms were developed using TensorFlow Lite.
+Analog design automation: OpenFASOC and ALIGN
+Analog design is still considered magic to most of us. Unbeknownst to many, analog is a key part of many of the electronic devices we enjoy, not the least of which is the mighty smartphone. Analog design is typically the long pole in a chip design schedule, often performed by a select group of engineers and done primarily by manual means. Both of these talks discussed efforts to automate the analog design process, significantly improving the productivity of the design team, reducing the time to market, and also enabling technology migration from process node to node.
+Our next technical talk will be a CHIPS Deep Dive Cafe Talk on Tuesday, Nov. 9 at 8 a.m. PT entitled “Learning To Play the Game of Macro Placement with Deep Reinforcement” by Young-Joon Lee of Google. I hope you are able to join us for this exciting and informative talk. To register, please visit here.
+
+
+This post was originally published at Antmicro.
+Co-simulating HDL has been possible in Renode since the 1.7.1 release, but the functionality – critical for hardware/software co-development as well as FPGA use cases – is constantly evolving based on the needs of our customers like Google and Microchip as well as our work in open source groups including CHIPS Alliance and RISC-V International. To quickly recap, by co-simulation we mean a scenario where a part of the system is simulated in Renode but some specific peripheral or subsystem is simulated directly from HDL, e.g. Verilog. To achieve this, Renode integrates with Verilator, a fast and popular open source HDL simulator, which we are helping our customers adopt as well as expanding its capabilities to cover new use cases. Peripherals simulated directly from HDL are typically called Verilated peripherals.
+Co-simulation is a highly effective approach to testing IP cores in complex scenarios. HDL simulation is typically much slower than functional simulation, so to cut down on development turnaround time you can partition your design into a fixed part that you can simulate fast using Renode and the IP you are developing that you can co-simulate using Verilator. Renode offers a lot of ready-to-use components – for which you do not need to have a hardware description – which can be put together to provide a complete system to test new IP core designs.
+For more than a year now, Renode has supported using AXI4-Lite and Wishbone buses for the Verilated peripherals’ communication with the rest of the system. As can be seen with the Verilated UART examples included with Renode, these can be used not only to receive data from, but also to send data to the peripheral. Additionally, because Renode can simulate external interfaces, you can easily open a window for such a UART (with showAnalyzer command during simulation) and the whole interaction is driven by UART’s TX and RX signals.
The riscv_verilated_liteuart.resc script shows the interaction between the system based on the VexRiscv CPU implemented in Renode and the UART based on an HDL model simulated with Verilator that together enable users to work with Zephyr’s shell interactively.
In these examples, however, all the communication is initiated from Renode’s side by either reading from or writing to UART. There is no way for the peripheral to trigger the communication, which limited use-cases where the co-simulation could have been used.
+Thanks to our work with Microchip and Google, since Renode 1.12 new features are available in the VerilatorPlugin; the most important change is introducing the ability for a Verilated peripheral to trigger communication with other elements of the system. The Renode API was expanded to accommodate the new features. There are now two new actions in the co-simulating communication which enable a Verilated peripheral to initialize communication with Renode by sending data to or requesting data from the system bus.
+Support for the AXI4 bus was also added. This is different from the AXI4-Lite bus, which only implements a subset of AXI4 features. The Verilated peripheral can either act on AXI4 bus as a controller that requests accesses (therefore utilizing these new Renode API actions) or as a peripheral (in the AXI4 bus context) that is only requested to take some action.
+Creating a Renode agent (which handles an HDL model’s connection with Renode) with a role chosen for your peripheral is as simple as including an appropriate header and connecting signals. For example, FastVDMA acts as a controller on AXI4 bus with the following code in a file creating its Renode agent:
+
#include "src/buses/axi-slave.h"
+VDMATop *top;
+
+void Init() {
+ AxiSlave* slaveBus = new AxiSlave(32, 32);
+
+
+ slaveBus->aclk = &top->clock;
+ slaveBus->aresetn = &top->reset;
+
+ slaveBus->awid = &top->io_write_aw_awid;
+ slaveBus->awaddr = (uint32_t *)&top->io_write_aw_awaddr;
+
+ // Connecting the rest of the signals to the bus
+Another new feature is the ability to connect the Verilated peripheral through multiple buses. For example, now it’s possible to have a peripheral connected to both AXI4 and AXI4-Lite buses, which enables even more complex HDL models to be tested with Renode. This is the case of the FastVDMA, which is connected this way:
+#include "src/buses/axi-slave.h"
+#include "src/buses/axilite.h"
+
+RenodeAgent *fastvdma;
+
+void Init() {
+ AxiLite* bus = new AxiLite();
+ AxiSlave* slaveBus = new AxiSlave(32, 32);
+
+ // Initializing both buses’ signals
+
+ //=================================================
+ // Init eval function
+ //=================================================
+ bus->evaluateModel = &eval;
+ slaveBus->evaluateModel = &eval;
+
+ //=================================================
+ // Init peripheral
+ //=================================================
+ fastvdma = new RenodeAgent(bus);
+ fastvdma->addBus(slaveBus);
+
+ slaveBus->setAgent(fastvdma);
+}
+Fast Versatile DMA (FastVDMA) is a Direct Memory Access controller designed with portability and customizability in mind. It is an open source IP core developed by Antmicro in 2019 that is written in Chisel. It is a very versatile DMA controller because of the range of supported buses. It can be controlled through an AXI4-Lite or Wishbone bus while the data can be transmitted through either an AXI4, AXI4-Stream or Wishbone. Since its inception it has been used in a number of projects, e.g., bringing a GUI to krktl’s snickerdoodle. For more information it’s best to head to the original blog note about FastVDMA.
+Through Antmicro’s long-term partnership with Microchip, Renode is a vital part of the PolarFire SoC developer experience. Microchip customers are using the Renode integration with the vendor’s default SoftConsole IDE to develop software for the PolarFire SoC platform and it’s development board, the Icicle Kit.
+
With the latest co-simulation capabilities, developers are able to explore a combination of hard and soft IP, developing their FPGA payload and verifying it within Renode. This allows them to work on advanced projects, from graphic output support similar to the one we implemented for snickerdoodle with FastVDMA (possibly employing our open-hardware HDMI board for Icicle Kit), through advanced FPGA-based crypto solutions, to design-space exploration and pre-silicon development, with the debugging and testing capabilities native to Renode.
+To see how Renode allows you to simulate complex setups with multiple co-simulated IP blocks, see our tests of Verilated FastVDMA plus Verilated RAM.
+It’s worth noting that as these blocks are isolated and interconnected only via Renode, you can easily prepare setups in which peripherals use different busses to connect. This gives you an ability to focus on the interesting details and to prepare your systems from building blocks more easily.
+If you’d like to speed up the development of your ASIC or FPGA solution using the advantages of advanced co-simulation, Antmicro offers commercial support and engineering services around Renode, Verilator and other tools, as well as FPGA and ASIC design, hardware, software and cloud services. We work with organizations like CHIPS Alliance and RISC-V International enable a more software-driven hardware ecosystem based by open source. For a full list of our open source activity, head to our open source portal.
+
+
+New joint working group will enhance the OmniXtend Cache Coherency architecture
+SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), and CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced a joint collaboration to update the OmniXtend Cache Coherency specification and protocol, along with building out developer tools for OmniXtend.
+As part of this collaboration, RISC-V International and CHIPS Alliance have formed a new OmniXtend working group which will focus on creating an open, cache coherent, unified memory standard for multicore compute architectures. The group will update the OmniXtend specification and protocol, build out architectural simulation models and a reference register-transfer level (RTL) implementation, as well as create a verification workbench. These tools for an open, standard unified memory coherency bus leveraging OmniXtend will make it easier for designers to take advantage of OmniXtend for data-centric applications.
+“As RISC-V International develops implementation independent specifications and ecosystem components, it is an important priority for us to ensure that whatever we develop will work with emerging and established standards. The joint working group will interact with various RISC-V groups to review the OmniXtend protocol with an emphasis on cache management and paying close attention to coherency enablement for RISC-V members,” said Mark Himelstein, CTO at RISC-V International. “As a result of this joint effort, the RISC-V community will have the tools they need to leverage an open, coherent, unified memory standard for all types of data-centric applications.”
+“The newly formed OmniXtend working group will set the standard for open, coherent heterogeneous compute architectures. We plan to allow for a mixture of hardware IP blocks, giving developers more design flexibility so they can choose what works best for their specific application needs,” said Rob Mains, General Manager at CHIPS Alliance. “We encourage the RISC-V community to get involved in this important initiative which will open new design possibilities with OmniXtend.”
+Dejan Vucinic of Western Digital will be giving a talk on OmniXtend at the CHIPS Alliance Spring Workshop on March 30, 2021. The event will also cover the AIB chiplet ecosystem, SWeRV Core support, FPGA tooling and much more. To register for this free virtual event, please visit: https://events.linuxfoundation.org/chips-alliance-spring-workshop/register/.
+To learn more about the OmniXtend working group, please visit: https://lists.chipsalliance.org/g/riscv-omnixtend-wg.
+RISC-V is a free and open ISA enabling a new era of processor innovation through open collaboration. Founded in 2015, RISC-V International is composed of more than 1,300 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
+RISC-V International, a non-profit organization controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of RISC-V International have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
+
+This post was originally published at Antmicro.
+Real-world FPGAs designs often require high rate transmission protocols such as PCIe, USB and SATA which rely on high speed transceivers for external communication. These protocols are used to interface with various devices such as graphics cards and storage devices, and many of our clients reach out to us specifically because they need the flexibility, high-throughput and low-latency characteristics of FPGAs.
+In particular, for customers that deal with high data volumes (which is very common in video applications), implementing SATA to communicate and transfer data with e.g. an SSD hard drive is a must.
+Since Antmicro believes in an open source, vendor neutral approach to FPGAs, today we will describe how to build a SATA-enabled system using a completely open source flow, including the hardware platform, FPGA IP as well as, perhaps most importantly, tooling which we have been developing as part our bigger effort within CHIPS Alliance.
+Antmicro is a pioneer in a software-driven approach to developing FPGAs. On top of new hardware description languages, open source IP and software that have been gaining traction in the FPGA space, one necessary missing element has been open source tooling. Open tools allow a workflow more familiar to software developers, who are used to just downloading their toolchain without having to log in anywhere or managing licenses.
+Moreover, open tools provide the great advantage of easy to set up CI systems that keep track of regressions and allow more efficient and robust development.
+Some of our forward-looking customers such as Google require these kinds of workflows to take full control of their development toolchain, for various reasons: security, development productivity, scale. Others, like QuickLogic, who thanks to the cooperation with us are the first ever FPGA vendor company to fully embrace open source tools, are looking to deliver a more tailored experience to their own customers, which is easier to do based on open source.
+To prove the viability of open source FPGA tools, being able to implement high-speed interfaces to verify how the toolchain handles high-speed transceivers is key; thus, a fully open source SATA is a very good target, especially that an open source core, LiteSATA, was available in our favorite open source SoC generator for FPGAs, LiteX. What was missing was a hardware platform, putting it all together, and – of course – tools.
+The SATA design we developed is meant to run on top of a Nexys Video board from Digilent, featuring an Artix7 200T Xilinx FPGA, coupled with custom expansion board connected through the FMC connector and hosting an M.2 SSD module. Thanks to the FMC connector on the Nexys Video we achieved a relatively simple and modular hardware setup.
+The FMC expansion board, developed by Antmicro, is fully open-sourced and available on GithHub.
+
The FPGA design is generated with the LiteX SoC builder and the main components that we used are:
+Moreover, the software running in the SoC includes a simple BIOS that can perform SATA initialization and basic read and write operations of the sectors in the SSD drive.
+
The SATA setup proves that high speed protocols can be enabled on mainstream FPGAs such as Xilinx 7-series with an open source toolchain, with Yosys for synthesis and VPR for place and route. The LiteSATA IP core makes use of so-called GTP hard blocks, and in fact one of the main challenges we dealt with here was enabling these hard blocks in the Artix-7 architecture definition to get an end-to-end open source toolchain.
+Other than enabling more coverage of popular FPGAs, much of our current FPGA toolchain effort goes into increasing the interoperability of tools like VPR and nextpnr as well as their proprietary counterparts to enable a more collaborative ecosystem which would enable the community – including universities, commercial companies, FPGA vendors and individual developers – to tackle the ambitious goal of open source FPGAs together.
+For more information on the FPGA interchange and how much value it brings to the open source FPGA tooling refer to the dedicated Antmicro blog note. In the future, once that work is at a more advanced stage, LiteSATA will be one of the first example designs to be tested with the FPGA interchange-enabled tools.
+The FPGA SATA design is available in the symbiflow-examples repository and can be built with the open toolchain, and run on the hardware setup described above.
+After following the instructions to install the toolchain and preparing the environment, run the following to build the LiteX SATA design:
+cd xc7
+make TARGET=”nexys_video” -C litex_sata_demo
+When the bitstream is generated, you can find it in the build directory under litex_sata_demo/build/nexys_video.
To load the bitstream on the Nexys Video board you can use the OpenFPGALoader tool, which has support for the board.
+Once the bitstream is loaded on the FPGA, you can access the BIOS console through the UART connected to your host system and run the following (note that X depends on the assigned USB device):
+picocom --baud 115200 /dev/ttyUSBX
+When the LiteX BIOS gives you control, you need to perform the SATA initialization before being able to read and write sectors on the drive. See the output below:
+
The work on enabling the SATA protocol in a fully open source flow was one of the steps on the way towards supporting PCIe in the toolchain which will unlock even more advanced use cases. PCIe can be used for a variety of purposes, such as connecting external graphic cards or accelerators to an FPGA design, and generally enable even faster transmission rates from and to the FPGA chip.
+
+
+In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2?
+The SweRV Core EH1 was the first to be released through CHIPS Alliance and was a core aimed at high-end embedded applications including Western Digital’s flash controllers and SSDs. The core is a dual issue, superscalar, high-performance core with 9 pipeline stages. The EH2 is an exciting further development aimed at delivering even more performance for IoT, artificial intelligence and data-intensive embedded applications.
+To read more, please check out the article at Semiconductor Engineering written by Roddy Urquhart at Codasip: https://semiengineering.com/about-the-swerv-core-eh2/.
+
+
+SkyWater furthers collaboration with CHIPS Alliance members on open source shuttle projects
+SAN FRANCISCO, Sept. 16, 2021 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that SkyWater Technology (NASDAQ: SKYT) has become a member of the organization. SkyWater provides custom development, volume manufacturing and advanced packaging services for a wide range of silicon, including solutions based on the free and open RISC-V instruction set architecture (ISA).
+“The pace of open source hardware innovation is continuing to heat up. We are proud to have helped make it possible to design, verify and manufacture SoCs that have been entirely developed with open source technologies, from process technology to intellectual property and the automation environment,” said Ross Miller, Vice President, Strategic Marketing & Business Unit at SkyWater Technology. “CHIPS Alliance has already generated strong momentum with its work and we look forward to collaborating with the organization and its membership to take open source innovation to new heights.”
+In May 2021, SkyWater and fellow CHIPS Alliance member Efabless launched the chipIgnite program to bring chip design and fabrication to the masses. SkyWater’s open source 130 nm CMOS platform will be used to fabricate chips for the chipIgnite program. The automotive-grade mixed-signal platform is well suited for IoT and edge computing as it is designed to support both digital and analog circuits with embedded non-volatile memory for a wide range of SoC architectures. Open source designs and private commercial designs that include non-open source IP are both eligible to participate in the program.
+The chipIgnite program extends SkyWater’s work with Google, eFabless, Antmicro and the OpenROAD project, among other partners, on the Open MPW Shuttle Program. The multi-project wafer (MPW) program provides fabrication for fully open source projects using SkyWater’s Open Source PDK. Costs for fabrication, packaging, evaluation boards and shipping are covered by Google. During the first round of the shuttle run, called MPW-ONE, 40 open source designs were selected to be fabricated at no cost to designers; 60 percent of those designs were submitted by first-time ASIC designers. The second phase, MPW-TWO, is in progress now and the parts and assembled boards will be shipped to the project owners by the end of the year.
+“The chipIgnite and MPW programs that SkyWater has enabled perfectly align with CHIPS Alliance’s mission to make chip design more accessible, while significantly reducing the cost of creating and fabricating chips,” said Rob Mains, General Manager at CHIPS Alliance. “We are pleased to have SkyWater formally join CHIPS Alliance as we continue to collaborate to break down the barriers of chip design.”
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
+
+It’s great to learn that Google announced the expansion of its partnership with SkyWater Technology. They are working together to release an open source process design kit (PDK) for SKY90-FD, SkyWater’s commercial 90nm fully depleted silicon on insulator (FDSOI) CMOS process technology. SKY90-FD is based on MIT Lincoln Laboratory’s 90 nm commercial FDSOI technology, and enables designers to create complex integrated circuits for a diverse range of applications.
+You can read more @ https://opensource.googleblog.com/2022/07/SkyWater-and-Google-expand-open-source-program-to-new-90nm-technology.html
+
+
+This post was originally published at Antmicro.
+The growing cost and complexity of advanced nodes, supply chain issues and demand for silicon independence mean that the ASIC design process is in need of innovation. Antmicro believes the answer to those challenges is bound to come from the software-driven, open source approach which has shaped the Internet and gave rise to modern cloud computing. Applying the methodologies of software design to ASICs is however notoriously viewed as difficult, given the closed nature of many components needed to build chips – tools, IP and process design kits, or PDKs for short, as well as the slow turnaround of manufacturing.
+The open source, collaborative SkyWater PDK project, combined with the free ASIC manufacturing shuttles running every quarter from Google and efabless, has been filling one of those gaps. Add to it open source licensed ASIC design tools we are helping develop as part of CHIPS Alliance as well as massive parallelization capabilities offered by the cloud and what you get is an ASIC design ecosystem at the verge of a breakthrough. To effect this change, together with Google, efabless, SkyWater and others we are working on more developments, including letting the shuttle designs benefit from software-driven hardware productivity tools such as LiteX and Renode (which we are currently helping the SkyWater shuttle effort to adopt), as well as new and exciting developments in the process technology itself.
+If you want to participate in making ASIC design history, let us show you why and how the shuttle program is the way to do that. And by the end of this article, hopefully you will want to participate in the next, fourth shuttle with the submission deadline at the end of this year.
+
In May 2020 Google and SkyWater Technology Foundry released the first ASIC proven open source PDK. The PDK targets the 130 nm process which, while not state-of-the-art, is still in widespread practical use, especially in mixed-signal and specialized designs.
+The PDK release involved restructuring the original code and data and properly documenting all the available cells in the PDK. This operation was performed in a collaboration between a group of industrial and academic partners, with Antmicro’s effort focused mostly on developing tools for automatic PDK structuring and documentation.
+An open source PDK was a key missing piece in end-to-end open source ASIC development, but in itself would not allow the average developer to feel the change. To enable developers to work with the PDK in practice and build fully open source chips with fast turnaround that is necessary to breed the necessary innovation, Google funded the Open MPW Shuttle Program operated by efabless, a fellow CHIPS Alliance member. The program assumes the applying projects are fully open source and based on a permissive license, targets the 130 nm SkyWater process and uses open source ASIC toolchain. Projects accepted in the program are then manufactured and the authors receive their packaged ASICs without any additional costs – production, packaging, testing and delivery is all covered for.
+The program is a great opportunity for any developer wanting to develop open source ASICs and contribute to the emerging open source ASIC community. The first shuttle program attracted 37 projects, including:
+We have been assisting customers expressing the desire to participate in the SkyWater shuttle in assessing the feasibility of their designs, creating the necessary workflows and adapting the tools involved to their particular needs.
+Our engineering services can be used to enhance your development teams with the ability to use open source tools more effectively and integrate with your infrastructure in a way which allows you to benefit from the open source’s capabilities while not disrupting your internal workflows unnecessarily.
+In total, over 100 designs have been sent to fabrication so far, many authored by teams with a predominantly software background. With over 2500 users in the SkyWater open source PDK slack, this is truly a community in the making.
+Most of the designs in the shuttles use the Caravel harness design which implements a RISC-V CPU with some base peripherals, OpenRAM generated memory, an I/O ring and a user area where developers can place their designs. The harness design is meant to be a fixed block / starting point which significantly lowers the entry level for the ASIC developers, but as such is also subject to evolution to better answer the needs of the shuttle participants, which we will describe later in the note.
+The core part of the PDK shuttle process uses the OpenLane toolchain, a flow based on the OpenROAD project, also a part of CHIPS Alliance. The toolchain implements all the steps required to generate a production-ready ASIC layout (GDS) from an RTL design.
+
Since production is the most expensive and time consuming part of the process, testing and validation are key stages in need of innovation, and the experiences learned from the SkyWater shuttle effort are invaluable.
+Under the auspices of CHIPS Alliance, Google, Western Digital and Antmicro are leading the work on enabling fully open source SystemVerilog development, testing and validation. The work focuses on a number of design flow aspects, including:
+ +All these are meant to improve the development experience and benefit from the inherent scalability and reusability of open source tools to offer practical value for teams building new ASIC designs.
+Open source design tools constitute one aspect of fully open source ASIC design. The other aspect, just as important as tooling, is open source, high-quality, reusable IP cores, and indeed the very rules of the SkyWater shuttle program encourage developers to open source their design and reuse existing cores.
+At the core of the shuttles is the Caravel harness. To improve the shuttle’s user experience and let the community benefit from a wider array of off-the-shelf tools and cores, we are assisting with the ongoing effort of adopting the Caravel design to be based on LiteX.
+LiteX, a widely known open source SoC generator, will make it possible for more open source cores to be integrated with ASIC designs, ultimately lowering the entry barrier for software engineers. It comes with multiple ready to use cores, including an open source DRAM controller used in the Rowhammer test platform we described some time ago. This alternative harness, whose development you can track in a dedicated GitHub repository, will open the door to more contributions from the LiteX community and allow us to use a bunch of tools that we have already integrated, like our open source simulation framework, Renode.
+The LiteX framework provides developers with an easy way to experiment with various different CPU cores. Testing a system against many possible cores, often running complex software, makes validation no trivial task.
+Renode, Antmicro’s open source development framework, features advanced SW/HW/FPGA/ASIC co-simulation capabilities and has been directly integrated with LiteX to generate the necessary configurations that correspond to the hardware system. Renode supports a multitude of CPU, I/O IP, sensor and network building blocks, both native to LiteX and otherwise, allowing its users to simulate the entire platform design before implementation, i.e. in the pre-silicon stage.
+Renode addresses the profound challenge of testing complex software, running it on various CPUs and using custom peripheral cores at the same time. Developers can make use of Renode’s ability to co-simulate with Verilator or with physical hardware, reducing the simulation time of SoC systems that utilize custom IP cores.
+Back in September, Antmicro presented a case of co-simulating the popular Xilinx Zynq-7000 SoC running Linux with a verilated FastVDMA core, and of course co-simulation with platforms like the PolarFire SoC is something we have been steadily improving on with our partner Microchip.
+A similar kind of development methodology will be possible with the new Caravel harness.
+Taking that HW/SW co-design workflow to its natural consequence, as showcased by our work with Google, Dover Microsystems and others, Renode allows developers to build SW-oriented hardware faster than HDL and benefit from the flexibility known from software development cycles where iterations happen in a matter of days. Recently, Renode has been extended with support for RISC-V vector instructions which translates into a further improvement of the development process of machine learning algorithms in open source ASICs.
+Building and testing ASIC designs is often a time and resource intensive task. The open source tooling approach, endorsed by the SkyWater shuttle program, possesses an important advantage over any proprietary perspective – it allows for infinite scaling of compute resources as there are neither licensing costs nor other license related limitations involved.
+Developments around distributed and scalable cloud based CI/CD systems like self-hosted GitHub Actions runners in GCP, a collaboration between Antmicro and Google, are providing the ecosystem with new options for reliable, fast testing and deployment of ASIC designs. Cloud based CI systems can be built to combine both closed and open source solutions, providing hybrid solutions that fill the gaps of either approach. And on a more general level, scalable and accessible CI/CD systems facilitate collaboration between large and geographically distributed teams of developers.
+SkyWater PDK is being constantly improved, extending the possibilities for future designs. One of the recent add-ons to the PDK is a ReRAM library which can be used to develop non-volatile memories using the SkyWater 130nm technology.
+Further SkyWater PDK development plans include extending the PDK portfolio with 180nm, 90nm and 45nm technology processes – stay tuned for upcoming developments in that space!
+Three shuttle runs have already happened, and thanks to Google’s commitment as well as the overwhelming interest from business, research and government institutions, the project will continue through 2022 and most likely beyond. The 4th shuttle run is currently open and will be accepting submissions by December 31, 2021.
+For projects that, for any reason, cannot be open sourced or submitted within the timeline of the open shuttle, a private shuttle called ChipIgnite has been created.
+
+
+This post was originally published at Antmicro.
+Field Programmable Gate Arrays (FPGAs) have been around for several decades, but historically development of toolchains targeting specific platforms was done in separate ecosystems and driven by the vendors themselves. Only in recent years, the development of vendor-neutral open source toolchains has revealed the need of having an abstraction layer to describe and define an FPGA architecture through a standard format.
+FPGA toolchains are not trivial as they comprise several elements which themselves can be quite complex: roughly speaking, you can divide the process of “compiling” FPGA-targeted code in a Hardware Description Language (HDL) into three stages: synthesis, place and route, bitstream generation. A standard format could provide a common description of the various architectures and serve as a bridge between the multitude of open source and closed proprietary tools that deal with the entire process or parts thereof, including the open source Yosys for synthesis and VtR and nextpnr for place and route, to relevant vendor tooling from Xilinx, Intel, Lattice, QuickLogic, etc.
+The introduction of a common format enables a shared methodology where specific building blocks are simply interchangeable. With that in mind, together with Google we started the FPGA Interchange Format project within the SymbiFlow initiative, bringing forth a unified framework that, by lowering the entry barriers, lets developers swiftly move from one tool to another with virtually no effort. As part of our collaboration with Google, Antmicro is now developing the Interchange format definition and related tools which aim to become a development standard the FPGA industry has been in need of.
+The Interchange format provides three key descriptions to describe an FPGA and interact with the various tools involved:
+One of the main challenges behind the creation of a standard format, specifically for the device resources, lies in the definition of the line between generalization and specificity of an FPGA architecture, as each device architecture variant may have some individual features that can be difficult to generalize in the context of other variants.
+For this practical reason, the FPGA Interchange format in its current form focuses on the only architecture type in mainstream use on the market today, namely island-based (also called tile-based) FPGAs: two-dimensional arrays of reconfigurable logic blocks, hard blocks, switch blocks and input-output blocks.
+This allows the standard to reach a level of universality and conciseness which makes it easy to work with, adopt and implement.
+After determining what the Interchange format should describe, the next step was to define how to best implement the format itself. The choice fell on a well-supported, open source and fast serialization protocol – Cap’n Proto.
+Cap’n Proto allows a great efficiency in terms of run-time and on-disk memory occupation, given also the huge amount of elements that are present in an FPGA device, such as wires and connections, that need to be stored in the device database. The protocol enables a concise, well-defined and, if used correctly, a backward compatible architecture and netlist format description.
+The framework uses the Cap’n Proto schema language whose implementations exist in many of the most common programming languages such as C++, Python, Java and Rust. This gives a good chance of future interoperability with other tooling that will inevitably emerge if the standard is successful.
+On top of the FPGA Interchange schema definitions, a Python-based library was created to interface with the schema itself, and provides functionalities to read and write device databases, logical netlists and physical netlists, as well as utilities to convert from one representation to another. It is often the case where a physical netlist needs to be inspected and analyzed, and a Cap’n Proto serialized netlist can be easily converted to its YAML or JSON human-readable equivalents.
+As previously mentioned, the FPGA Interchange format aims at lowering the barriers and building bridges between different place and route tools that can read and write using the same convention.
+In this sense, the major milestone of the Interchange format was to have the production and exchange of the physical netlist between one place and route tool and another.
+To reach this milestone, nextpnr was chosen as the first place and route tool to adopt the Interchange format. In the past few months, we extended nextpnr with FPGA Interchange format capabilities and currently the tool is able to place and route basic designs for the Xilinx 7-series and Lattice Nexus FPGA families using the format.
+To achieve initial support for Xilinx devices, the vendor’s own extremely interesting RapidWright framework has also been introduced to the flow, and it is specifically used to write the device database in the Interchange format, consisting of all the device information.
+Additionally, RapidWright is able to read and write the physical netlists to generate design checkpoint files that can be opened in Xilinx’s Vivado tool.
+The default open source flow for Xilinx devices uses Yosys to synthesize the design and VPR or nextpnr for place and route. The last step – bitstream generation uses the FPGA Assembly FASM format to generate the file used for programming the FPGA. FASM is a textual format specifying which FPGA feature should be enabled or disabled. Its textual nature makes it easy to analyze and experiment with. VPR supported this format natively, and nextpnr has been extended to support it as a part of the interchange format support work.
+
Now, by using the interchange format, you can create your flow from building blocks, with the possibility to use a different tool (either open source or proprietary) for each step. +A sample, somewhat involved flow which illustrates this mix-and-match nature of interchange-capable tooling may look as described below.
+For processing any design, you need the FPGA device description files. These are generated in the following matter:
+The device description has to be generated only once, and will normally be distributed with the toolchain installation package so that the user will not have to bother with this part.
+With the device architecture in place, a digital design can be processed with the toolchain:
+Keep in mind this is just one of many possible flows. It is used to test the interchange format interoperability between different tools.
+This flow example shows how the Interchange creates a bridge between an open source flow with Yosys and nextpnr, and a closed source one using Vivado – demonstrating the possibility of interchanging tools thanks to a shared format.
+To ensure the Interchange format works as intended using all the various currently supported tools, we have developed an FPGA Interchange tests suite, which provides tests that expose device features and functionalities.
+To push forward the adoption of the format, the effort is being currently transferred from the SymbiFlow project into the CHIPS Alliance, whose goal is to build an open source ASIC/FPGA ecosystem – including cores, I/O IPs, interconnect standards as well as digital and analog tooling – to radically transform the ASIC/FPGA design landscape.
+Apart from allowing various existing tools to interoperate and share development efforts today, the Interchange format is a natural addition to the CHIPS Alliance in that it opens up smart ways to rapidly design and prototype new FPGA architectures, reduce the iteration times to implement, or add support to a place and route tool for a new architecture.
+Besides nextpnr, there are other open source place and route tools slated to adopt the Interchange format as well, such as the Versatile Place and Route (VPR) from the Verilog-to-Routing project (VtR).
+Originally intended to perform architectural design exploration to support research in the FPGA field, VtR – and specifically VPR – can be used to place and route designs on real devices as well, such as the Xilinx 7-series and QuickLogic architectures, but only using the VPR data model and device description, as it does not yet support the Interchange format.
+One of the next milestones in the development of the Interchange format is the full native support of the format within VPR, therefore enabling something that was previously impossible: performing place and route using different tools interchangeably; jumping, for instance, from VPR placement output to nextpnr routing, allowing for faster improvements in algorithms.
+Those benefits will extend to not only VPR and nextpnr, but to any other closed source tools, or new open source ones that adopt and implement the Interchange format.
+In fact, having a standard Interchange format at the tooling developers’ disposal lowers the barriers to developing new open source tools in this area and, as example use cases, enable new approaches to partial dynamic reconfiguration, or the exploration of different place and route algorithms.
+
+
+This post was originally published at Antmicro.
+Although new ASIC design methodologies and tools such as Chisel are on the rise, most ASIC projects still use SystemVerilog, the support of which in open source tools has traditionally lagged behind. This is unfortunate, as using proprietary alternatives with the CI systems of open source projects is neither scalable due to licensing costs and restrictions nor simple due to the need for license management and obfuscation.
+Antmicro, Google and the CHIPS Alliance, which we are members of, have been working together with the lowRISC project to address this issue by implementing relevant tools and useful integrations in the open source domain. One large milestone on this route is Verible, an open source Flex/YACC SystemVerilog parser, linter and formatter recently open sourced by our partner and customer, Google.
+Among other developments in that space, Antmicro has been helping to make Verible support some SystemVerilog features required for working with practical use cases, such as lowRISC’s ibex, a 32-bit RISC-V core used in the open source security project, OpenTitan. But to generate adoption, ease of use is just as important as features, which is why Verible was recently exposed to a wider audience by integrating it with FuseSoC.
+
One of the main advantages of an open source linter/formatter is how easy it is to integrate it with existing workflows of open source projects. As it happens, many open source FPGA/ASIC projects, including OpenTitan, are managed with FuseSoC, an open source tooling and IP package manager (from our fellow FOSSi veteran Olof Kindgren) which we also use and support. Thanks to the integration of Verible with FuseSoC, linting and formatting automation becomes much easier.
+Below you will find a simple example and explanation of how to use the integration The example contains an accompanying CI setup which you can mimic in your own project.
+We will use the following example repository to explain the usage of Verible with FuseSoC. +We will show how to build Verible binaries, download ibex – a small 32 bit RISC-V CPU core – and run FuseSoC to perform linting/formatting using Verible.
+Install the prerequisites (tested on Ubuntu 18.04):
+sudo apt update
+sudo apt install cmake ninja-build wget python3 python3-pip python3-setuptools make tar git
+sudo pip3 install fusesoc
+Verible can be built using the Bazel build system. +Bazel is not available in the debian/ubuntu apt repositories. To install Bazel you should add Bazel’s apt repository:
+curl https://bazel.build/bazel-release.pub.gpg | sudo apt-key add -
+echo "deb [arch=amd64] https://storage.googleapis.com/bazel-apt stable jdk1.8" | sudo tee /etc/apt/sources.list.d/bazel.list
+sudo apt update && sudo apt install bazel
+To build Verible, a C++11 compatible compiler is required. After the installation of bazel, Verible can be built and installed:
+git clone https://github.com/google/Verible
+cd Verible
+bazel build -c opt //...
+bazel run :install -c opt -- `pwd`/../Verible_bin
+export PATH=`pwd`/../Verible_bin/:$PATH
+Alternatively, you can download pre-built Verible binaries from the Verible release page. Refer to the Verible documentation and Bazel installation instructions for more details.
+FuseSoC uses tool backends available in edalize, which is another workflow automation project from the same author that we contribute to regularly. In order to use the Verible tools with FuseSoC you need to define a tool section in the FuseSoC core target file. Ibex already includes the integration, so you can use its ibex_core.core file as an example.
+
To perform linting in ibex_core, use:
git clone https://github.com/lowRISC/ibex
+cd ibex
+#add Verible lint rules
+sed -i '132i\ - "-generate-label"\n - "-unpacked-dimensions-range-ordering"\n - "-explicit-parameter-storage-type"\n - "-line-length"\n - "-module-filename"\n - "-no-trailing-spaces"\n - "-undersized-binary-literal"\n - "-struct-union-name-style"\n - "-case-missing-default"\n - "-explicit-task-lifetime"\n - "-explicit-function-lifetime"' ibex_core.core
+
+fusesoc --cores-root. run --target=lint --tool=veriblelint lowrisc:ibex:ibex_core:0.1
+To format the ibex_core with Verible:
#add Veribleformat rules
+sed -i '154i\ - "--max_search_states"\n - "10000000"' ibex_core.core
+fusesoc --cores-root . run --target=format --no-export lowrisc:ibex:ibex_core:0.1
+
The demo also shows how the Verible linter can be incorporated into CI pipelines for automatic detection of lint errors. To demonstrate that, a Pull Request containing an intentional lint error has been opened. An automatically executed CI pipeline was able to detect the issues with the code and inform the developers about the failed build status. The output of the lint command can provide useful information about a possible cause of the error. Early detection of lint errors can reduce the number of bugs and improve the overall code quality. Using a linter can accelerate development and reduce costs by finding errors at an early stage of the process. Moreover, incorporating the Verible formatter in CI can also ensure that incoming contributions automatically employ the project’s coding style.
+More detailed instructions regarding building and using Verible with FuseSoC can be found in the README file located in the demo repository.
+If you are involved in FPGA and ASIC development and want your project to be portable, modular and harness other benefits of a software-driven, open-source-based approach, Antmicro is there to help. As a key service provider in both RISC-V Foundation and CHIPS Alliance, we have lots of readily available SoC building blocks, tools and capabilities to assist you in developing your next product or platform.
+
+
+Mark your calendars! The CHIPS Alliance Workshop is coming up on Thursday, Sept. 17 from 11 a.m. to 2 p.m. PT. This free, virtual event will feature talks from industry leaders including Antmicro, Efabless, Google, Intel, Mentor, Metrics, OpenROAD, QuickLogic, SiFive, UC Berkeley and Western Digital.
+The CHIPS Alliance Workshop will fit 10 sessions into three hours for a jam-packed event covering a range of interesting topics in the open source community. You’ll hear about open source ASICs, chiplets, FPGAs and SoCs, in addition to open source design verification, FPGA tooling, machine learning accelerators and more. Read on for additional details, and make sure to register before it’s too late.
+Check out the schedule below to learn more about what the sessions will cover:
+For more information about the CHIPS Alliance and our activities over the past year, check out our 2020 Annual Report and our recent news. We look forward to seeing you at the Workshop!
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+This post was originally published at Antmicro.
+Verilator is a popular open source SystemVerilog simulator and one of the key tools in the ASIC and FPGA ecosystem, which Antmicro is actively using and developing, e.g. by enabling co-simulation with Renode or Cocotb integration. It’s also one of the fastest available HDL simulators, including proprietary alternatives. It achieves that speed by generating highly optimized C++ code from a given hardware design. Verilator does a lot of work at compile-time to make the generated (‘verilated’) code extremely fast, such as ordering statements in an optimal way.
+
This static ordering of code also means that support for some SystemVerilog features has been sacrificed to make Verilator so performant. Namely, Verilator does not support what is known as the stratified scheduler, an algorithm that specifies the correct order of execution of SystemVerilog designs. This algorithm is dynamic by nature, and does not fit with Verilator’s static approach.
+Because of this, it doesn’t support UVM, a widely-used framework for testing hardware design. Testbenches for Verilator have to be written using C++, which is not ideal – you shouldn’t have to know how to program in C++ in order to use a SystemVerilog simulator. Many ASIC projects out there are not able to take advantage of Verilator, because verification in this space is very often done with UVM. This is a gap that together with Western Digital, Google and the entire CHIPS Alliance we have been working to close, to enable fully open source, cloud-scalable verification usable by the broad ASIC industry.
+Some of the key features UVM requires are dynamically-triggered event variables and delays. To support them, we introduced to Verilator what we call a dynamic scheduler with a proof-of-concept implementation which we described in more detail in a previous blog note earlier this year. Essentially, it enabled us to suspend execution of SystemVerilog processes when waiting for delays to finish or events to be triggered, thus postponing some of the scheduling from compile-time to runtime.
+initial forever begin
+ @ping;
+ #1 ->pong;
+end
+
+initial forever begin
+ #1 ->ping;
+ @pong;
+end
+That thread-based implementation worked, but it required us to run each process in a design in a separate thread, using mutexes and condition variables to facilitate communication. With a working solution in hand, which proved that what we set out to do was possible, we started thinking about a different approach which would allow us to avoid the significant performance overhead introduced by threads and hopefully also simplify the implementation. That’s when coroutines came up as a possible solution.
+The concept of coroutines has been around for decades. Arguably, most programmers have used them, knowingly or not. They are available in some form for most modern programming languages, and now they are also included in the newest C++20 standard. But what are they exactly?
+Normally, when a function or procedure is called, it needs to finish execution in order for the control flow to go back to a previously executed function. This is reflected in the way the call stack works. A coroutine is a generalization of the concept of a function, but it differs in that its execution can be paused at any point, and resumed from any other point in the program, even from a different thread. Implementations vary, but often this is achieved by allocating coroutine state on the heap.
+
Unlike threads which are commonly used in desktop operating systems, coroutines are a form of cooperative multitasking, meaning that they have to yield control by themselves – there is no scheduler controlling them from the outside. A programmer needs to specify when and where a coroutine should resume execution.
+A popular use case for coroutines is writing generators. As the name suggests, a generator is used for generating some set of values, but instead of returning them all at once, it yields them one by one to the function that called the generator.
+generator<uint64_t> fib(int n) {
+ uint64_t a = 0, b = 1;
+ for (int i = 0; i < n; i++) {
+ b = b + exchange(a, b);
+ co_yield a;
+ }
+}
+for (uint64_t n : fib(40))
+ printf("%d\n", n);
+Coroutines are also useful for asynchronous programming, for writing functions that start their execution on one thread, but continue on another (i.e. a background thread intended for heavy computation).
+ui_task click_compute() {
+ label = "Computing...";
+ co_await compute();
+ label = "Finished!";
+}
+Currently, coroutines are supported by many C++ compilers, including GCC 11 and Clang 13 (which offers experimental support). It’s worth mentioning that Clang is excellent at optimizing them: if a coroutine does not outlive the calling function’s stack frame, and its state object’s size is known at compile time, the heap allocation can be elided. Coroutine state is then simply stored on the stack. This gives Clang a significant performance edge over GCC in some cases, such as when using generators.
+From the get-go, coroutines seemed like a good fit for dynamic scheduling of SystemVerilog in Verilator. As previously mentioned, they follow the cooperative model of multitasking, which is sufficient for handling delays and events in SV processes. Preemption is not necessary, as there is no danger of starving a task. That is because all SystemVerilog processes should yield in a given time slot either after they finish or when they’re awaiting an event.
+A significant drawback of threads, which was what the initial implementation was based on, is that it’s not possible to spawn thousands of them, one for each process in a design. However, it is possible to spawn thousands of coroutines, and that number is only bound by the amount of RAM available to the user. Also, with coroutines, one does not have to worry about multithreading problems like data races. All multitasking can be done on one thread.
+The only issue with coroutines is the allocation of coroutine state. However, there are ways to mitigate that by using a custom allocator, as well as only using coroutines for the parts of a design that actually require it. After all, dynamic scheduling is not relevant to the synthesizable subset of SystemVerilog.
+Thus, we decided to go ahead and replace threads with coroutines in our implementation. The new approach immediately proved to be easier to work with, and development pace increased significantly. The new version already surpassed the thread-based implementation in completeness as well as performance, and is available here. Let’s take a closer look at how it works.
+initial forever begin
+ @ping;
+ #1;
+ ->pong;
+end
+while (true) {
+ co_await ping;
+ co_await 1;
+ resume(pong);
+}
+The general idea for the implementation was to reflect the behavior of SystemVerilog delay and event trigger statements in the co_await statement in C++20. This statement is responsible for suspending coroutines, and we use it to suspend SystemVerilog processes represented by coroutines in a verilated design.
When a delay is encountered, the current coroutine (or process) is suspended and put into a queue. When the awaited time comes, the corresponding coroutine is removed from the queue and resumed.
+
Event variables work in a similar way. When we are awaiting an event, we suspend the current coroutine and put it in what we call an event dispatcher. If the event is triggered at a later point, we inform the event dispatcher which resumes the corresponding coroutine.
+
With all this, the C++ code that Verilator generates for delays and event statements is very similar to the original SystemVerilog source code.
+initial forever begin
+ @ping;
+ #10;
+ ->pong;
+end
+This SystemVerilog corresponds to the following C++ code. The snippet shown here is simplified for readability, but the structure of the verilated code is preserved.
+Coroutine initial() {
+ while (true) {
+ co_await eventDispatcher[&ping];
+ co_await delayedQueue[TIME() + 10];
+ eventDispatcher.trigger(&pong);
+ }
+}
+As mentioned before, one of the main reasons for the switch to coroutines is performance. The original, thread-based implementation was hundreds of times slower than vanilla Verilator when simulating CHIPS Alliance’s SweRV EH1 core. Just replacing threads with coroutines resulted in 3-time speedup in SWeRV. Further optimization, the most crucial part being detecting which parts of a design need dynamic scheduling, resulted in indistinguishable performance between vanilla Verilator and our version when using Clang for verilated code compilation.
+Next steps and future goals +There is still more work to be done. We are continuously working on improving the dynamic scheduler in the following areas:
+working out some remaining edge cases, +making it work with Verilator’s built-in multithreading solution, +adding new test cases to push these new features to their limits. +Our goal is to provide the dynamic scheduler in Verilator as an optional scheduler that users can enable if they want more SystemVerilog compatibility. Of course users should bear in mind that it is not as well-tested as Verilator’s default behavior, but this will most likely improve as we find more practical use cases to make use of the solution.
+Naturally, many more features are needed to provide full UVM support. This, among others, includes:
+process class, which is used for controlling the behavior of a SystemVerilog process,The dynamic scheduler is part of a bigger undertaking driven by Antmicro within the CHIPS Alliance to create fully open source toolchains and flows for FPGA and ASIC development. Together with Surelog/UHDM, a project aiming at providing a complete SystemVerilog parsing and elaboration solution, this brings us closer to being able to simulate, test and verify designs which use UVM with entirely open source tools.
+
+
+Verilator can boast the status of one of the most widely used free and open source digital design tools for ASIC and FPGA development. To stay on top of the ever-increasing complexity of ASIC and FPGA devices, as users and contributors, Antmicro, a CHIPS Alliance member and part of the Tools Workgroup, has been actively working on improving the tool and its ecosystem, including adding co-simulation capabilities with Renode, adding support for SystemVerilog UVM testbenches to Verilator, or improving scalability for very large designs.
+Even though Verilator is most likely already the fastest open source Verilog/SystemVerilog simulator out there, generating and compiling simulation models for large designs can still be very time-consuming. This note presents the improvements Antmicro has introduced to model generation (aka verilation) in terms of memory usage and execution time optimizations, as well as an ongoing effort aimed at parallelizing Verilator passes by enabling multithreading in the verilation process.
+In the recent months, Antmicro added multiple assorted optimizations across Verilator’s codebase that reduced execution times and memory usage for model generation which we list below along with tables containing data presenting the improvements brought on by each of them.
+m_name field was removed from AstVarRef (“variable reference”), one of the most commonly recurring AST nodes. Now it references a variable’s name directly, since the name in AstVarRef’ was always identical to it, making the field redundant. Dropping this single field allowed the Antmicro team to reduce memory usage by 8-12% and reduce verilation time by 4-5% for the test designs:
dynamic_cast for checking graph types. This type info is used for downcasting generic graph vertices/edges to concrete types. Similarly to what was already done for the AST and data-flow graphs. It shows a significant performance boost over dynamic_cast. On top of this change, for graph vertices or edges where the desired downcast type is obvious, they have removed typechecks, resulting in further performance improvements for our test designs:
m_selfPointer field in AstVarRef and AstCCall (C/C++ function call). This field contains a string that needs to be put before a given variable reference or function call, and represents a reference to a “self” object, such as this. Each instance of these nodes contained a copy of such a “self pointer” string. After this change, these strings are shared across multiple instances of these nodes. Apart from bringing slight memory usage and performance benefits, it cleans up the code a bit by limiting the number of ad-hoc string operations:
VN_AS typecast in child node getters with C++’s reinterpret_cast in release builds (this remains unchanged for debug builds for error checking purposes). The type assertion is unnecessary in this particular case, as most of the time the pointers can only be set through properly typed setters. This resulted in 4-5% time improvements for the test designs:
While all the changes listed above offer tangible speed and memory usage improvements to the model generation process, the most significant potential for gains lies in introducing multithreading to the currently single-threaded process. Model generation in Verilator consists of multiple stages that mutate a Verilog/SystemVerilog Abstract Syntax Tree (AST) that represents the simulated design and then outputs the model as C++ code, ready to be compiled. The branches of the AST that are independent of each other can, in theory, be processed in-parallel but since Verilator is a very extensive project, introducing multithreading to the entirety of the verilation process at once is not feasible, the team is set on introducing the changes incrementally.
+As far as Verilator’s functions go, they can be divided into thread-safe and non thread-safe. Each function needs to be thoroughly investigated and appropriately marked by hand, which may lead to human errors detrimental to the overall functioning of the tool. To make sure thread-safe functions only call other thread-safe functions, Antmicro introduced a CI check that uses clang annotations and verifies this assumption.
+As spawning threads is a relatively slow process, and controlling the number of threads is crucial in this scenario, Antmicro introduced a thread pool that accepts jobs and queues them up for execution, so that the CPU doesn’t context switch between them unnecessarily, leading to performance loss.
+Since multithreaded programming is complex and sometimes unstable (especially at the development phase), it was crucial that we made sure single threaded verilation is unaffected. To ensure there is no time increase or deadlock while generating models using a single thread, the team introduced a switch that can disable thread synchronization if not needed.
+Error reporting also needed refactoring to make it thread-safe. It is responsible for error reporting, is used in every part of Verilator and can be called recursively. This change reduced total C++ emit time in our large-core based test design from 144 s to 80 s. Error reporting makes for an interesting example of the type of obstacles one meets when refactoring code to be thread-safe, as reporting cannot be parallelized since it can only have one output to which we need to print in-order (e.g. the terminal).
+With the changes listed above already part of mainline Verilator, we can now proceed to focus on the next steps towards making multithreaded verilation reality. Antmicro has identified numerous other areas we need to optimize for full parallelization, e.g. the ability to disable multithreading locally so that thread-safe functions can be called only when they are necessary, or analysis and adjustment of subsequent passes for multithreading optimization purposes. CHIPS will be reporting on this progress in future blog posts.
+While the efforts within the CHIPS Alliance to enable multithreading across Verilator along with other improvements are ongoing, Antmicro can help you adopt, adapt, and extend Verilator to integrate it into a workflow tailored to your particular project, including scaling it for very large designs and co-simulation of entire systems with the open source Renode simulation framework.
+To learn more about the Tools Workgroup’s contributions to Verilator, you can watch a talk by Antmicro from ORConf 2023 in which they discuss the current status of non-synthesizable SystemVerilog support in the Verilator open source simulator and progress toward full UVM support.
+With years of experience in commercial and R&D FPGA and ASIC-based projects, as well as leading theCHIPS Alliance’s Tools Workgroup, Antmicro offers comprehensive engineering support that can help you make the most of the flexibility and approachability of open source solutions. Do not hesitate to reach out at contact@antmicro.com.
+
+
+Verilator is a high performance, open source functional simulator that has gained tremendous popularity in its usage and adoption in the verification of chip design. The ASIC development community has widely embraced Verilator as an effective, often even superior alternative to proprietary solutions, and it is now the standard approach in RISC-V CPU design as the community has worked to provide Verilator simulation capabilities out of the box. CHIPS Alliance and RISC-V leaders Antmicro and Western Digital have been collaborating to make Verilator even more useful for ASIC design purposes, working towards supporting industry-standard verification methods in a completely open source flow.
+On June 15 at the inaugural CHIPS Alliance Deep Dive Cafe Talk, Karol Gugala, an engineering manager with Antmicro, provided an excellent in-depth technical talk on extending Verilator towards supporting universal verification methodology, UVM. The event was well attended, and is now also available on YouTube.
+ +Karol started the talk by providing motivation for the improvement and expansion of the System Verilog design environment, and in particular the importance of UVM to offer a common verification framework. He covered the current limitations of Verilator relative to its handling of UVM, and the goal of the community to more robustly support UVM and also System-Verilog as a design language, both of which are efforts Antmicro is deeply involved with as part of its work within CHIPS Alliance with other CHIPS partners. In the talk, Karol provided in-depth details of work that has been done to handle UVM.
+The focus of the work summarized by Karol’s talk was the comparison of static event scheduling already existent in Verilator to dynamic scheduling which is required for event driven simulation, specifically event and time awareness. This necessitated a new event scheduling approach in Verilator to be implemented. The new scheduler is an option that the user can activate as a runtime switch. Future work includes: clocking blocks, assertions, assertions, class parameters, integration with UHDM, and further runtime optimization. Full UVM support for the SweRV RISC-V cores and OpenTitan – also based on a RISC-V implementation, Ibex – are two key goals. A detailed overview of how System Verilog statements are evaluated as members of different processes was provided. As an initial implementation, each process now runs in a separate thread, with processes and threads communicating via standard IPC synchronization protocols. Scheduling of the threads / processes is left to the OS scheduler, and further work in the project will include more involved scheduling techniques.
+You can read more about dynamic scheduling in Verilator at Antmicro’s blog, and test all the new features of Verilator with examples of designs and some GitHub Actions-based CI simulations (based on Antmicro’s public repo).
+The next talk in the CHIPS Deep Dive Cafe Series is the AIB Deep Dive + Opportunities Presented By Intel on Tuesday, Aug. 10 at 8 a.m. PT. You can register for the event here.
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+
+Xilinx to continue to drive forward open source FPGA innovation
+SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud.
+“Xilinx has long been an advocate of open standards and open source,” said Tomas Evensen, CTO Open Source at Xilinx. “As a member of the CHIPS Alliance, we look forward to continuing to spearhead open FPGA initiatives to give everyone the opportunity to innovate faster and do more with their designs.”
+Xilinx collaborated with longstanding CHIPS Alliance members Antmicro and Google to develop the FPGA Interchange Format, which helps to lower design barriers by enabling interoperability between open and closed source FPGA toolchains. Xilinx designed its RapidWright open source platform to work with the Interchange Format. RapidWright enables users to customize implementations to their unique challenges and provides a design methodology using pre-implemented modules with a gateway to back-end tools in Vivado.
+“As the inventor of the FPGA, Xilinx is one of the key companies driving forward innovation in this market,” said Rob Mains, General Manager at CHIPS Alliance. “Xilinx has already been working closely with several CHIPS Alliance members around open source efforts, so it’s great to have them under the CHIPS Alliance umbrella as we plan to boost our FPGA efforts this year.”
+To learn more about Xilinx, please visit: www.xilinx.com.
+The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The primary focus is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
+The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.
+
+CHIPS Alliance hosts many open source projects at various stages of their maturity lifecycle.
+
+
++
+
+Free and open source toolchain for FPGA devices
+
+
+The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust
+
+
+FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.
+
+
+Framework for automatic FPGA toolchains benchmarking
+
+
+Open source SystemC to SystemVerilog translation tool and SingleSource library.
+
+
+Cache coherence framework for RISC-V based on TileLink
+
+
+Fully Open Source Automated Analog Block Generation built on top of OpenROAD, Magic, Netgen, Klayout and Ngspice
+
+
+RISCV-DV is an open source verification tool for RISC-V processors. RISCV-DV is a SystemVerilog based random RISC-V instruction generator that checks the execution against an industry standard ISS for correction and compliance.
+
+
+The SoC generator instantiates the RISC-V Rocket Core and relevant component.
+
+
+SureLog is a SystemVerilog 2017 Pre-processor, Parser, UHDM Compiler providing IEEE Design/TB VPI and Python AST API. UHDM is the underlying Hardware Data Model framework. More info: https://woset-workshop.github.io/WOSET2020.html#article-10
+
+
+SystemVerilog test framework for checking SV spec support coverage in various open source tools - parsers, linters, formatters etc.
+
+
+Parse SystemVerilog (IEEE 1800-2017) with a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
+
+
+Support the Chisel Hardware Construction Language and related projects
+