BoringUtils can create illegal input probes

[seldridge]

Consider the following:

//> using scala "2.13.15"
//> using repository sonatype-s01:snapshots
//> using dep "org.chipsalliance::chisel::7.0.0-M2+243-4aaefff4-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin::7.0.0-M2+243-4aaefff4-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.layer.{Layer, LayerConfig}
import chisel3.probe.{Probe, ProbeValue, define}
import chisel3.util.experimental.BoringUtils
import circt.stage.ChiselStage

object A extends Layer(LayerConfig.Extract())

class Bar extends RawModule {

  val a_probe = IO(Output(Probe(Bool(), A)))

  layer.block(A) {
    val a = dontTouch(WireInit(false.B))
    define(a_probe, ProbeValue(a))
  }

}

class Foo extends RawModule {

  val bar = Module(new Bar)

  class Baz extends RawModule {
    layer.block(A) {
      val b = dontTouch(WireInit(BoringUtils.tapAndRead(bar.a_probe)))
    }
  }

  val baz = Module(new Baz)
}

object Main extends App {
  println(
    ChiselStage.emitCHIRRTL(new Foo)
  )
  println(
    ChiselStage.emitSystemVerilog(
      gen = new Foo,
      firtoolOpts = Array(
        "-disable-all-randomization",
        "-strip-debug-info",
        "-enable-layers=Verification,Verification.Assert,Verification.Assume,Verification.Cover"
      )
    )
  )
}

This creates a FIRRTL module Baz that contains has an input probe. This will then fail FIRRTL compilation.

This should be creating a non-probe port for any inputs.

This produces the following FIRRTL:

FIRRTL version 4.1.0
circuit Foo :%[[
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Bar>a"
  },
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~Foo|Baz>b"
  }
]]
  layer A, bind, "A" :
  layer Verification, bind, "verification" :
    layer Assert, bind, "verification/assert" :
    layer Assume, bind, "verification/assume" :
    layer Cover, bind, "verification/cover" :
  module Bar :
    output a_probe : Probe<UInt<1>, A>

    layerblock A :
      wire a : UInt<1>
      connect a, UInt<1>(0h0)
      define a_probe = probe(a)


  module Baz :
    input b_bore : Probe<UInt<1>, A>

    layerblock A :
      wire b : UInt<1>
      connect b, read(b_bore)


  public module Foo :

    inst bar of Bar
    inst baz of Baz
    define baz.b_bore = bar.a_probe

The error produced during FIRRTL compilation is:

Exception in thread "main" circt.stage.phases.Exceptions$FirtoolNonZeroExitCode: /Users/schuylereldridge/Library/Caches/org.chipsalliance.llvm-firtool/1.99.2/bin/firtool returned a non-zero exit code. Note that this version of Chisel (7.0.0-M2+243-4aaefff4-SNAPSHOT) was published against firtool version 1.99.2.
------------------------------------------------------------------------------
ExitCode:
1
STDOUT:

STDERR:
Users/schuylereldridge/repos/github.com/seldridge/scala-snippets/BoringUtils.scala:32:56: error: input probe not allowed

[seldridge]

There's a more fundamental problem here where the input port would need to be colored to compile this and this isn't something that we intend to support. (There are alternative ways to represent this like instantiating Baz under a layer which would work, however.)