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Originally in RocketChip, we use SBT to generate jar and execute it to generate Verilog, which was a nightmare to maintain, thus we eventually switch to mill for managing this build system.
However, since mill doesn't support remote build and remote cache, for large scale build for DSE or testing in T1, building and test machines spent to much duplicated effort to elaborate Verilog and verilating and compiling RTLs.
I finally understand why SiFive designed the wake build system for large scale RTL designing. However, introducing it to T1 will consume too much engineering burden for learning a new language just for yet another nix...
I think this is the reason that we are going to switch to NIX to handle the entire build system and only use mill to elaborate a fat jar as generator.
The text was updated successfully, but these errors were encountered:
Originally in RocketChip, we use SBT to generate jar and execute it to generate Verilog, which was a nightmare to maintain, thus we eventually switch to mill for managing this build system.
However, since mill doesn't support remote build and remote cache, for large scale build for DSE or testing in T1, building and test machines spent to much duplicated effort to elaborate Verilog and verilating and compiling RTLs.
I finally understand why SiFive designed the wake build system for large scale RTL designing. However, introducing it to T1 will consume too much engineering burden for learning a new language just for yet another nix...
I think this is the reason that we are going to switch to NIX to handle the entire build system and only use mill to elaborate a fat jar as generator.
The text was updated successfully, but these errors were encountered: