From 4c51f050fc9dbd1e404266f2d34339c87907a4c5 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sun, 28 Jul 2024 23:49:17 +0800 Subject: [PATCH 1/4] [ipemu] workaround xprop for DPI --- ipemu/src/TestBench.scala | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala index c38d5f9c9..facb858b6 100644 --- a/ipemu/src/TestBench.scala +++ b/ipemu/src/TestBench.scala @@ -109,18 +109,25 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) val writeRd: UInt = UInt(32.W) val vxsat: UInt = UInt(32.W) } + // X gated by didIssue val issue = WireDefault(0.U.asTypeOf(new Issue)) val fence = RegInit(false.B) val outstanding = RegInit(0.U(4.W)) val doIssue: Bool = dut.io.issue.ready && !fence outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.issue.valid + // used to gate Xprop when DPI hasn't issued yet. + val didIssue = RegInit(false.B) + didIssue := doIssue || didIssue // TODO: refactor driver to spawn 3 scoreboards for record different retirement. val t1Probe = probe.read(dut.io.t1Probe) fence := Mux(doIssue, issue.meta === 2.U, fence && !t1Probe.retireValid && !(outstanding === 0.U)) - issue := RawClockedNonVoidFunctionCall("issue_vector_instruction", new Issue)( - clock, - doIssue + issue := Mux(didIssue || doIssue, + RawClockedNonVoidFunctionCall("issue_vector_instruction", new Issue)( + clock, + doIssue, + ), + 0.U.asTypeOf(new Issue) ) dut.io.issue.bits.instruction := issue.instruction dut.io.issue.bits.rs1Data := issue.src1Data From 1feda4c08a891e83c0a73b2b0a7ae6787373f151 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sun, 28 Jul 2024 16:52:21 +0800 Subject: [PATCH 2/4] [ipemu] gate dpi call with !reset to work around verilator scheduling bug --- ipemu/src/TestBench.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala index facb858b6..898fb3c13 100644 --- a/ipemu/src/TestBench.scala +++ b/ipemu/src/TestBench.scala @@ -113,7 +113,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) val issue = WireDefault(0.U.asTypeOf(new Issue)) val fence = RegInit(false.B) val outstanding = RegInit(0.U(4.W)) - val doIssue: Bool = dut.io.issue.ready && !fence + val doIssue: Bool = dut.io.issue.ready && !fence && !reset outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.issue.valid // used to gate Xprop when DPI hasn't issued yet. val didIssue = RegInit(false.B) From 234ba3848f603101090725539da3ba03cc4e7e6a Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Tue, 30 Jul 2024 22:15:58 +0800 Subject: [PATCH 3/4] [difftest] set mcycle to 0 to avoid driver/offline mcycle misalign --- difftest/test_common/src/spike_runner.rs | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/difftest/test_common/src/spike_runner.rs b/difftest/test_common/src/spike_runner.rs index 2d69d4642..b9339be7a 100644 --- a/difftest/test_common/src/spike_runner.rs +++ b/difftest/test_common/src/spike_runner.rs @@ -89,11 +89,8 @@ impl SpikeRunner { let proc = self.spike.get_proc(); let state = proc.get_state(); - state.set_mcycle((self.cycle + self.spike_cycle) as usize); - - let pc = state.get_pc(); - let disasm = proc.disassemble(); - let insn_bits = proc.get_insn(); + let mcycle = (self.cycle + self.spike_cycle) as usize; + state.set_mcycle(0); let mut event = SpikeEvent::new(spike, self.do_log_vrf); state.clear(); @@ -101,9 +98,8 @@ impl SpikeRunner { let new_pc = if event.is_v() || event.is_exit() { // inst is v / quit debug!( - "SpikeStep: spike run vector insn ({}), is_vfence={}", + "SpikeStep: spike run vector insn ({}), mcycle={mcycle}", event.describe_insn(), - event.is_vfence(), ); event.pre_log_arch_changes(spike, self.vlen).unwrap(); let new_pc_ = proc.func(); @@ -112,8 +108,8 @@ impl SpikeRunner { } else { // inst is scalar debug!( - "SpikeStep: spike run scalar insn (pc={:#x}, disasm={}, bits={:#x})", - pc, disasm, insn_bits, + "SpikeStep: spike run scalar insn ({}), mcycle={mcycle}", + event.describe_insn(), ); let new_pc_ = proc.func(); event.log_mem_write(spike).unwrap(); From 5927fd7134b413db3e650c7af93beb657487da2a Mon Sep 17 00:00:00 2001 From: github-actions Date: Tue, 30 Jul 2024 08:36:45 +0000 Subject: [PATCH 4/4] [ci] update test case cycle data --- .github/cases/blastoise/default.json | 24 ++++++++++++------------ .github/cases/machamp/default.json | 26 +++++++++++++------------- .github/cases/sandslash/default.json | 26 +++++++++++++------------- 3 files changed, 38 insertions(+), 38 deletions(-) diff --git a/.github/cases/blastoise/default.json b/.github/cases/blastoise/default.json index dbb766530..89fbbdba0 100644 --- a/.github/cases/blastoise/default.json +++ b/.github/cases/blastoise/default.json @@ -273,9 +273,9 @@ "codegen.vse16_v": 4013, "codegen.vse32_v": 3403, "codegen.vse8_v": 4623, - "codegen.vsetivli": 469, - "codegen.vsetvl": 469, - "codegen.vsetvli": 469, + "codegen.vsetivli": 468, + "codegen.vsetvl": 468, + "codegen.vsetvli": 468, "codegen.vsext_vf2": 23212, "codegen.vsext_vf4": 4241, "codegen.vslide1down_vx": 866515, @@ -499,15 +499,15 @@ "codegen.vfredusum_vs": 122332, "codegen.vfredmax_vs": 122332, "codegen.vfredmin_vs": 122332, - "rvv_bench.ascii_to_utf16": 1583519, - "rvv_bench.ascii_to_utf32": 704038, + "rvv_bench.ascii_to_utf16": 1583627, + "rvv_bench.ascii_to_utf32": 704056, "rvv_bench.byteswap": 3353190, - "rvv_bench.chacha20": 2, + "rvv_bench.chacha20": 3, "rvv_bench.mandelbrot": 4056017, - "rvv_bench.memcpy": 2072895, - "rvv_bench.memset": 438920, - "rvv_bench.mergelines": 3347920, - "rvv_bench.poly1305": 2, - "rvv_bench.strlen": 877645, - "rvv_bench.utf8_count": 6339104 + "rvv_bench.memcpy": 2103216, + "rvv_bench.memset": 438703, + "rvv_bench.mergelines": 3351737, + "rvv_bench.poly1305": 3, + "rvv_bench.strlen": 877754, + "rvv_bench.utf8_count": 6340467 } \ No newline at end of file diff --git a/.github/cases/machamp/default.json b/.github/cases/machamp/default.json index 22c4486e5..4ba0c0fb7 100644 --- a/.github/cases/machamp/default.json +++ b/.github/cases/machamp/default.json @@ -1,6 +1,6 @@ { "mlir.rvv_vp_intrinsic_add": 422, - "mlir.rvv_vp_intrinsic_add_scalable": 575, + "mlir.rvv_vp_intrinsic_add_scalable": 576, "mlir.hello": 113, "mlir.stripmining": 13447, "asm.mmm": 91467, @@ -271,9 +271,9 @@ "codegen.vse16_v": 3981, "codegen.vse32_v": 3371, "codegen.vse8_v": 4591, - "codegen.vsetivli": 437, - "codegen.vsetvl": 437, - "codegen.vsetvli": 437, + "codegen.vsetivli": 436, + "codegen.vsetvl": 436, + "codegen.vsetvli": 436, "codegen.vsext_vf2": 39423, "codegen.vsext_vf4": 6444, "codegen.vslide1down_vx": 1631043, @@ -435,14 +435,14 @@ "codegen.vxor_vx": 63114, "codegen.vzext_vf2": 39423, "codegen.vzext_vf4": 6444, - "rvv_bench.ascii_to_utf16": 1460027, - "rvv_bench.ascii_to_utf32": 631198, + "rvv_bench.ascii_to_utf16": 1460089, + "rvv_bench.ascii_to_utf32": 631174, "rvv_bench.byteswap": 3259012, - "rvv_bench.chacha20": 2, - "rvv_bench.memcpy": 1816404, - "rvv_bench.memset": 244393, - "rvv_bench.mergelines": 3170081, - "rvv_bench.poly1305": 2, - "rvv_bench.strlen": 710643, - "rvv_bench.utf8_count": 5727933 + "rvv_bench.chacha20": 3, + "rvv_bench.memcpy": 1846662, + "rvv_bench.memset": 244374, + "rvv_bench.mergelines": 3145593, + "rvv_bench.poly1305": 3, + "rvv_bench.strlen": 710137, + "rvv_bench.utf8_count": 5729458 } \ No newline at end of file diff --git a/.github/cases/sandslash/default.json b/.github/cases/sandslash/default.json index 6d0bdddb9..ad434f288 100644 --- a/.github/cases/sandslash/default.json +++ b/.github/cases/sandslash/default.json @@ -1,6 +1,6 @@ { "mlir.rvv_vp_intrinsic_add": 428, - "mlir.rvv_vp_intrinsic_add_scalable": 648, + "mlir.rvv_vp_intrinsic_add_scalable": 649, "mlir.hello": 115, "mlir.stripmining": 3598, "asm.mmm": 91467, @@ -271,9 +271,9 @@ "codegen.vse16_v": 5523, "codegen.vse32_v": 4817, "codegen.vse8_v": 6229, - "codegen.vsetivli": 821, - "codegen.vsetvl": 821, - "codegen.vsetvli": 821, + "codegen.vsetivli": 820, + "codegen.vsetvl": 820, + "codegen.vsetvli": 820, "codegen.vsext_vf2": 134897, "codegen.vsext_vf4": 19825, "codegen.vslide1down_vx": 6151901, @@ -435,14 +435,14 @@ "codegen.vxor_vx": 84861, "codegen.vzext_vf2": 134897, "codegen.vzext_vf4": 19825, - "rvv_bench.ascii_to_utf16": 1371567, - "rvv_bench.ascii_to_utf32": 583336, + "rvv_bench.ascii_to_utf16": 1371586, + "rvv_bench.ascii_to_utf32": 583329, "rvv_bench.byteswap": 3556325, - "rvv_bench.chacha20": 2, - "rvv_bench.memcpy": 1645508, - "rvv_bench.memset": 130492, - "rvv_bench.mergelines": 3095029, - "rvv_bench.poly1305": 2, - "rvv_bench.strlen": 715282, - "rvv_bench.utf8_count": 4795393 + "rvv_bench.chacha20": 3, + "rvv_bench.memcpy": 1675944, + "rvv_bench.memset": 130527, + "rvv_bench.mergelines": 3048326, + "rvv_bench.poly1305": 3, + "rvv_bench.strlen": 715092, + "rvv_bench.utf8_count": 4797064 } \ No newline at end of file