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biemsterbiemster
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simplify and #define sys_safe_access_..., abolish by #define GPIO ModeCfg
1 parent 7f7cfd2 commit 5cd65cc

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3 files changed

+89
-193
lines changed

3 files changed

+89
-193
lines changed

‎ch32fun/ch32fun.c

+29-140
Original file line numberDiff line numberDiff line change
@@ -1501,144 +1501,6 @@ void DelaySysTick( uint32_t n )
15011501
#endif
15021502
}
15031503

1504-
#if defined(CH59x)
1505-
/**
1506-
* @brief Enter safe access mode.
1507-
*
1508-
* @NOTE: After enter safe access mode, about 16 system frequency cycles
1509-
* are in safe mode, and one or more secure registers can be rewritten
1510-
* within the valid period. The safe mode will be automatically
1511-
* terminated after the above validity period is exceeded.
1512-
*/
1513-
vu32 IRQ_STA = 0;
1514-
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void sys_safe_access_enable(void)
1515-
{
1516-
if(read_csr(0x800) & 0x08)
1517-
{
1518-
IRQ_STA = read_csr(0x800);
1519-
write_csr(0x800, (IRQ_STA&(~0x08)));
1520-
}
1521-
ADD_N_NOPS(2);
1522-
R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG1;
1523-
R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG2;
1524-
ADD_N_NOPS(2);
1525-
}
1526-
1527-
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void sys_safe_access_disable(void)
1528-
{
1529-
R8_SAFE_ACCESS_SIG = 0;
1530-
write_csr(0x800, read_csr(0x800) | (IRQ_STA & 0x08));
1531-
IRQ_STA = 0;
1532-
ADD_N_NOPS(2);
1533-
}
1534-
1535-
void SetSysClock(SYS_CLKTypeDef sc)
1536-
{
1537-
sys_safe_access_enable();
1538-
R8_PLL_CONFIG &= ~(1 << 5); //
1539-
sys_safe_access_disable();
1540-
if(sc & 0x20) // HSE div
1541-
{
1542-
sys_safe_access_enable();
1543-
R32_CLK_SYS_CFG = (0 << 6) | (sc & 0x1f) | RB_TX_32M_PWR_EN | RB_PLL_PWR_EN;
1544-
ADD_N_NOPS(4);
1545-
sys_safe_access_disable();
1546-
sys_safe_access_enable();
1547-
ADD_N_NOPS(2);
1548-
R8_FLASH_CFG = 0X51;
1549-
sys_safe_access_disable();
1550-
}
1551-
1552-
else if(sc & 0x40) // PLL div
1553-
{
1554-
sys_safe_access_enable();
1555-
R32_CLK_SYS_CFG = (1 << 6) | (sc & 0x1f) | RB_TX_32M_PWR_EN | RB_PLL_PWR_EN;
1556-
ADD_N_NOPS(4);
1557-
sys_safe_access_disable();
1558-
sys_safe_access_enable();
1559-
R8_FLASH_CFG = 0X52;
1560-
sys_safe_access_disable();
1561-
}
1562-
else
1563-
{
1564-
sys_safe_access_enable();
1565-
R32_CLK_SYS_CFG |= RB_CLK_SYS_MOD;
1566-
sys_safe_access_disable();
1567-
}
1568-
sys_safe_access_enable();
1569-
R8_PLL_CONFIG |= 1 << 7;
1570-
sys_safe_access_disable();
1571-
}
1572-
void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode)
1573-
{
1574-
switch(mode)
1575-
{
1576-
case GPIO_ModeIN_Floating:
1577-
R32_PA_PD_DRV &= ~pin;
1578-
R32_PA_PU &= ~pin;
1579-
R32_PA_DIR &= ~pin;
1580-
break;
1581-
case GPIO_ModeIN_PU:
1582-
R32_PA_PD_DRV &= ~pin;
1583-
R32_PA_PU |= pin;
1584-
R32_PA_DIR &= ~pin;
1585-
break;
1586-
case GPIO_ModeIN_PD:
1587-
R32_PA_PD_DRV |= pin;
1588-
R32_PA_PU &= ~pin;
1589-
R32_PA_DIR &= ~pin;
1590-
break;
1591-
case GPIO_ModeOut_PP_5mA:
1592-
R32_PA_PD_DRV &= ~pin;
1593-
R32_PA_DIR |= pin;
1594-
break;
1595-
case GPIO_ModeOut_PP_20mA:
1596-
R32_PA_PD_DRV |= pin;
1597-
R32_PA_DIR |= pin;
1598-
break;
1599-
default:
1600-
break;
1601-
}
1602-
}
1603-
1604-
void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode)
1605-
{
1606-
switch(mode)
1607-
{
1608-
case GPIO_ModeIN_Floating:
1609-
R32_PB_PD_DRV &= ~pin;
1610-
R32_PB_PU &= ~pin;
1611-
R32_PB_DIR &= ~pin;
1612-
break;
1613-
1614-
case GPIO_ModeIN_PU:
1615-
R32_PB_PD_DRV &= ~pin;
1616-
R32_PB_PU |= pin;
1617-
R32_PB_DIR &= ~pin;
1618-
break;
1619-
1620-
case GPIO_ModeIN_PD:
1621-
R32_PB_PD_DRV |= pin;
1622-
R32_PB_PU &= ~pin;
1623-
R32_PB_DIR &= ~pin;
1624-
break;
1625-
1626-
case GPIO_ModeOut_PP_5mA:
1627-
R32_PB_PD_DRV &= ~pin;
1628-
R32_PB_DIR |= pin;
1629-
break;
1630-
1631-
case GPIO_ModeOut_PP_20mA:
1632-
R32_PB_PD_DRV |= pin;
1633-
R32_PB_DIR |= pin;
1634-
break;
1635-
1636-
default:
1637-
break;
1638-
}
1639-
}
1640-
#endif
1641-
16421504
void SystemInit( void )
16431505
{
16441506
#if defined(CH32V30x) && defined(TARGET_MCU_MEMORY_SPLIT)
@@ -1697,8 +1559,35 @@ void SystemInit( void )
16971559
#endif
16981560
#endif
16991561

1700-
#if defined(CH59x)
1701-
SetSysClock(CLK_SOURCE_PLL_60MHz);
1562+
#if defined(CH59x) // has no HSI
1563+
// SYS_SAFE_ACCESS for writing RWA and WA registers
1564+
#define SYS_SAFE_ACCESS_ENABLE { R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG1; R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG2; ADD_N_NOPS(2); }
1565+
#define SYS_SAFE_ACCESS_DISABLE { R8_SAFE_ACCESS_SIG = SAFE_ACCESS_SIG0; ADD_N_NOPS(2); }
1566+
#ifndef CLK_SOURCE_CH59X
1567+
#define CLK_SOURCE_CH59X CLK_SOURCE_PLL_60MHz
1568+
#endif
1569+
SYS_SAFE_ACCESS_ENABLE
1570+
R8_PLL_CONFIG &= ~(1 << 5);
1571+
SYS_CLKTypeDef sc = CLK_SOURCE_CH59X;
1572+
if(sc & 0x20) // HSE div
1573+
{
1574+
R32_CLK_SYS_CFG = (0 << 6) | (sc & 0x1f) | RB_TX_32M_PWR_EN | RB_PLL_PWR_EN;
1575+
ADD_N_NOPS(4);
1576+
R8_FLASH_CFG = 0X51;
1577+
}
1578+
1579+
else if(sc & 0x40) // PLL div
1580+
{
1581+
R32_CLK_SYS_CFG = (1 << 6) | (sc & 0x1f) | RB_TX_32M_PWR_EN | RB_PLL_PWR_EN;
1582+
ADD_N_NOPS(4);
1583+
R8_FLASH_CFG = 0X52;
1584+
}
1585+
else
1586+
{
1587+
R32_CLK_SYS_CFG |= RB_CLK_SYS_MOD;
1588+
}
1589+
R8_PLL_CONFIG |= 1 << 7;
1590+
SYS_SAFE_ACCESS_DISABLE
17021591
#elif defined(FUNCONF_USE_HSI) && FUNCONF_USE_HSI
17031592
#if defined(CH32V30x) || defined(CH32V20x) || defined(CH32V10x)
17041593
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;

‎ch32fun/ch32fun.h

+33-3
Original file line numberDiff line numberDiff line change
@@ -828,9 +828,39 @@ extern "C" {
828828
#define FUN_HIGH 0x1
829829
#define FUN_LOW 0x0
830830
#if defined(CH59x)
831-
#define funDigitalWrite( pin, value ) { if(value==FUN_HIGH){GPIOA_SetBits(pin);} else if(value==FUN_LOW){GPIOA_ResetBits(pin);} }
832-
void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode);
833-
#define funPinMode( pin, mode ) GPIOA_ModeCfg(pin, mode)
831+
#define GPIOA_ResetBits(pin) (R32_PA_CLR |= pin)
832+
#define GPIOA_SetBits(pin) (R32_PA_OUT |= pin)
833+
#define GPIOA_InverseBits(pin) (R32_PA_OUT ^= pin)
834+
#define GPIOB_ResetBits(pin) (R32_PB_CLR |= pin)
835+
#define GPIOB_SetBits(pin) (R32_PB_OUT |= pin)
836+
#define GPIOB_InverseBits(pin) (R32_PB_OUT ^= pin)
837+
#define GPIO_ResetBits(pin) { if(pin & PB) GPIOB_ResetBits(pin); else GPIOA_ResetBits(pin); }
838+
#define GPIO_SetBits(pin) { if(pin & PB) GPIOB_SetBits(pin); else GPIOA_SetBits(pin); }
839+
#define GPIO_InverseBits(pin) { if(pin & PB) GPIOB_InverseBits(pin); else GPIOA_InverseBits(pin); }
840+
#define funDigitalWrite( pin, value ) { if(value==FUN_HIGH){GPIO_SetBits(pin);} else if(value==FUN_LOW){GPIO_ResetBits(pin);} }
841+
typedef enum
842+
{
843+
GPIO_ModeIN_Floating,
844+
GPIO_ModeIN_PU,
845+
GPIO_ModeIN_PD,
846+
GPIO_ModeOut_PP_5mA,
847+
GPIO_ModeOut_PP_20mA,
848+
849+
} GPIOModeTypeDef;
850+
#define GPIO_ModeCfg(pd_drv, pu, dir, pin, mode) { switch(mode) { \
851+
case GPIO_ModeIN_Floating: \
852+
pd_drv &= ~pin; pu &= ~pin; dir &= ~pin; break; \
853+
case GPIO_ModeIN_PU: \
854+
pd_drv &= ~pin; pu |= pin; dir &= ~pin; break; \
855+
case GPIO_ModeIN_PD: \
856+
pd_drv |= pin; pu &= ~pin; dir &= ~pin; break; \
857+
case GPIO_ModeOut_PP_5mA: \
858+
pd_drv &= ~pin; dir |= pin; break; \
859+
case GPIO_ModeOut_PP_20mA: \
860+
pd_drv |= pin; dir |= pin; break; \
861+
} }
862+
#define funPinMode( pin, mode ) { if(pin & PB) GPIO_ModeCfg(R32_PB_PD_DRV, R32_PB_PU, R32_PB_DIR, pin, mode) \
863+
else GPIO_ModeCfg(R32_PA_PD_DRV, R32_PA_PU, R32_PA_DIR, pin, mode) }
834864
#else
835865
// Arduino-like GPIO Functionality
836866
#define GpioOf( pin ) ((GPIO_TypeDef *)(GPIOA_BASE + 0x400 * ((pin)>>4)))

‎ch32fun/ch59xhw.h

+27-50
Original file line numberDiff line numberDiff line change
@@ -185,7 +185,7 @@ typedef enum
185185
#define SAFE_ACCESS_SIG1 0x57 // WO: safe accessing sign value step 1
186186
#define SAFE_ACCESS_SIG2 0xA8 // WO: safe accessing sign value step 2
187187
#define SAFE_ACCESS_SIG0 0x00 // WO: safe accessing sign value for disable
188-
#define R8_CHIP_ID (*((vu8*)0x40001041)) // RF, chip ID register, always is ID_CH58*
188+
#define R8_CHIP_ID (*((vu8*)0x40001041)) // RF, chip ID register, always is ID_CH59*
189189

190190
/*System: Miscellaneous Control register */
191191
#define R32_MISC_CTRL (*((vu32*)0x40001048)) // RWA, miscellaneous control register
@@ -199,13 +199,6 @@ typedef enum
199199
#define R8_FLASH_CTRL (*((vu8*)0x40001806)) // RW, flash ROM access control
200200
#define R8_FLASH_CFG (*((vu8*)0x40001807)) // RW, flash ROM access config, SAM
201201

202-
#define read_csr(reg) ({unsigned long __tmp; __asm__ volatile ("csrr %0, " #reg : "=r"(__tmp)); __tmp; })
203-
#define write_csr(reg, val) ({ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
204-
__asm__ volatile ("csrw " #reg ", %0" :: "i"(val)); \
205-
else \
206-
__asm__ volatile ("csrw " #reg ", %0" :: "r"(val)); \
207-
})
208-
209202

210203
/* GPIO PA register */
211204
#define R32_PA_DIR (*((vu32*)0x400010A0)) // RW, GPIO PA I/O direction: 0=in, 1=out
@@ -270,48 +263,32 @@ typedef enum
270263
#define PA14 (0x00004000) /*!< Pin 14 selected */
271264
#define PA15 (0x00008000) /*!< Pin 15 selected */
272265

273-
#define PB0 (0x00000001) /*!< Pin 0 selected */
274-
#define PB1 (0x00000002) /*!< Pin 1 selected */
275-
#define PB2 (0x00000004) /*!< Pin 2 selected */
276-
#define PB3 (0x00000008) /*!< Pin 3 selected */
277-
#define PB4 (0x00000010) /*!< Pin 4 selected */
278-
#define PB5 (0x00000020) /*!< Pin 5 selected */
279-
#define PB6 (0x00000040) /*!< Pin 6 selected */
280-
#define PB7 (0x00000080) /*!< Pin 7 selected */
281-
#define PB8 (0x00000100) /*!< Pin 8 selected */
282-
#define PB9 (0x00000200) /*!< Pin 9 selected */
283-
#define PB10 (0x00000400) /*!< Pin 10 selected */
284-
#define PB11 (0x00000800) /*!< Pin 11 selected */
285-
#define PB12 (0x00001000) /*!< Pin 12 selected */
286-
#define PB13 (0x00002000) /*!< Pin 13 selected */
287-
#define PB14 (0x00004000) /*!< Pin 14 selected */
288-
#define PB15 (0x00008000) /*!< Pin 15 selected */
289-
#define PB16 (0x00010000) /*!< Pin 16 selected */
290-
#define PB17 (0x00020000) /*!< Pin 17 selected */
291-
#define PB18 (0x00040000) /*!< Pin 18 selected */
292-
#define PB19 (0x00080000) /*!< Pin 19 selected */
293-
#define PB20 (0x00100000) /*!< Pin 20 selected */
294-
#define PB21 (0x00200000) /*!< Pin 21 selected */
295-
#define PB22 (0x00400000) /*!< Pin 22 selected */
296-
#define PB23 (0x00800000) /*!< Pin 23 selected */
297-
#define PA_All (0xFFFFFFFF) /*!< All pins selected */
298-
299-
typedef enum
300-
{
301-
GPIO_ModeIN_Floating,
302-
GPIO_ModeIN_PU,
303-
GPIO_ModeIN_PD,
304-
GPIO_ModeOut_PP_5mA,
305-
GPIO_ModeOut_PP_20mA,
306-
307-
} GPIOModeTypeDef;
308-
309-
#define GPIOA_ResetBits(pin) (R32_PA_CLR |= pin)
310-
#define GPIOA_SetBits(pin) (R32_PA_OUT |= pin)
311-
#define GPIOA_InverseBits(pin) (R32_PA_OUT ^= pin)
312-
#define GPIOB_ResetBits(pin) (R32_PB_CLR |= pin)
313-
#define GPIOB_SetBits(pin) (R32_PB_OUT |= pin)
314-
#define GPIOB_InverseBits(pin) (R32_PB_OUT ^= pin)
266+
#define PB (0x10000000) /*!< Pin 0 selected */
267+
#define PB0 (0x10000001) /*!< Pin 0 selected */
268+
#define PB1 (0x10000002) /*!< Pin 1 selected */
269+
#define PB2 (0x10000004) /*!< Pin 2 selected */
270+
#define PB3 (0x10000008) /*!< Pin 3 selected */
271+
#define PB4 (0x10000010) /*!< Pin 4 selected */
272+
#define PB5 (0x10000020) /*!< Pin 5 selected */
273+
#define PB6 (0x10000040) /*!< Pin 6 selected */
274+
#define PB7 (0x10000080) /*!< Pin 7 selected */
275+
#define PB8 (0x10000100) /*!< Pin 8 selected */
276+
#define PB9 (0x10000200) /*!< Pin 9 selected */
277+
#define PB10 (0x10000400) /*!< Pin 10 selected */
278+
#define PB11 (0x10000800) /*!< Pin 11 selected */
279+
#define PB12 (0x10001000) /*!< Pin 12 selected */
280+
#define PB13 (0x10002000) /*!< Pin 13 selected */
281+
#define PB14 (0x10004000) /*!< Pin 14 selected */
282+
#define PB15 (0x10008000) /*!< Pin 15 selected */
283+
#define PB16 (0x10010000) /*!< Pin 16 selected */
284+
#define PB17 (0x10020000) /*!< Pin 17 selected */
285+
#define PB18 (0x10040000) /*!< Pin 18 selected */
286+
#define PB19 (0x10080000) /*!< Pin 19 selected */
287+
#define PB20 (0x10100000) /*!< Pin 20 selected */
288+
#define PB21 (0x10200000) /*!< Pin 21 selected */
289+
#define PB22 (0x10400000) /*!< Pin 22 selected */
290+
#define PB23 (0x10800000) /*!< Pin 23 selected */
291+
#define P_All (0xFFFFFFFF) /*!< All pins selected */
315292

316293

317294
#define HardFault_IRQn EXC_IRQn

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