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cnlohrcnlohr
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Merge pull request #519 from markusdd/master
Fix naming bug in DMA CFGR header for channels 4 to 7
2 parents 8f7517e + 23350f9 commit ac7f5f9

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-570
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6 files changed

+570
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‎ch32fun/ch32v003hw.h

+95-95
Original file line numberDiff line numberDiff line change
@@ -1249,101 +1249,101 @@ typedef struct
12491249

12501250
#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
12511251

1252-
/******************* Bit definition for DMA_CFG4 register *******************/
1253-
#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */
1254-
#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
1255-
#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
1256-
#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
1257-
#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */
1258-
#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */
1259-
#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
1260-
#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */
1261-
1262-
#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
1263-
#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
1264-
#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
1265-
1266-
#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
1267-
#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
1268-
#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
1269-
1270-
#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
1271-
#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */
1272-
#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */
1273-
1274-
#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
1275-
1276-
/****************** Bit definition for DMA_CFG5 register *******************/
1277-
#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */
1278-
#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
1279-
#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
1280-
#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
1281-
#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */
1282-
#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */
1283-
#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
1284-
#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */
1285-
1286-
#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
1287-
#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
1288-
#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
1289-
1290-
#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
1291-
#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
1292-
#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
1293-
1294-
#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
1295-
#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */
1296-
#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */
1297-
1298-
#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */
1299-
1300-
/******************* Bit definition for DMA_CFG6 register *******************/
1301-
#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */
1302-
#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
1303-
#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
1304-
#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
1305-
#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */
1306-
#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */
1307-
#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
1308-
#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */
1309-
1310-
#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
1311-
#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
1312-
#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
1313-
1314-
#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
1315-
#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
1316-
#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
1317-
1318-
#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
1319-
#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */
1320-
#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */
1321-
1322-
#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
1323-
1324-
/******************* Bit definition for DMA_CFG7 register *******************/
1325-
#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */
1326-
#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
1327-
#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
1328-
#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
1329-
#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */
1330-
#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */
1331-
#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
1332-
#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */
1333-
1334-
#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
1335-
#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
1336-
#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
1337-
1338-
#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
1339-
#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
1340-
#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
1341-
1342-
#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
1343-
#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */
1344-
#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */
1345-
1346-
#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */
1252+
/******************* Bit definition for DMA_CFGR4 register *******************/
1253+
#define DMA_CFGR4_EN ((uint16_t)0x0001) /* Channel enable */
1254+
#define DMA_CFGR4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
1255+
#define DMA_CFGR4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
1256+
#define DMA_CFGR4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
1257+
#define DMA_CFGR4_DIR ((uint16_t)0x0010) /* Data transfer direction */
1258+
#define DMA_CFGR4_CIRC ((uint16_t)0x0020) /* Circular mode */
1259+
#define DMA_CFGR4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
1260+
#define DMA_CFGR4_MINC ((uint16_t)0x0080) /* Memory increment mode */
1261+
1262+
#define DMA_CFGR4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
1263+
#define DMA_CFGR4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
1264+
#define DMA_CFGR4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
1265+
1266+
#define DMA_CFGR4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
1267+
#define DMA_CFGR4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
1268+
#define DMA_CFGR4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
1269+
1270+
#define DMA_CFGR4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
1271+
#define DMA_CFGR4_PL_0 ((uint16_t)0x1000) /* Bit 0 */
1272+
#define DMA_CFGR4_PL_1 ((uint16_t)0x2000) /* Bit 1 */
1273+
1274+
#define DMA_CFGR4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
1275+
1276+
/****************** Bit definition for DMA_CFGR5 register *******************/
1277+
#define DMA_CFGR5_EN ((uint16_t)0x0001) /* Channel enable */
1278+
#define DMA_CFGR5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
1279+
#define DMA_CFGR5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
1280+
#define DMA_CFGR5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
1281+
#define DMA_CFGR5_DIR ((uint16_t)0x0010) /* Data transfer direction */
1282+
#define DMA_CFGR5_CIRC ((uint16_t)0x0020) /* Circular mode */
1283+
#define DMA_CFGR5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
1284+
#define DMA_CFGR5_MINC ((uint16_t)0x0080) /* Memory increment mode */
1285+
1286+
#define DMA_CFGR5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
1287+
#define DMA_CFGR5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
1288+
#define DMA_CFGR5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
1289+
1290+
#define DMA_CFGR5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
1291+
#define DMA_CFGR5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
1292+
#define DMA_CFGR5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
1293+
1294+
#define DMA_CFGR5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
1295+
#define DMA_CFGR5_PL_0 ((uint16_t)0x1000) /* Bit 0 */
1296+
#define DMA_CFGR5_PL_1 ((uint16_t)0x2000) /* Bit 1 */
1297+
1298+
#define DMA_CFGR5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */
1299+
1300+
/******************* Bit definition for DMA_CFGR6 register *******************/
1301+
#define DMA_CFGR6_EN ((uint16_t)0x0001) /* Channel enable */
1302+
#define DMA_CFGR6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
1303+
#define DMA_CFGR6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
1304+
#define DMA_CFGR6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
1305+
#define DMA_CFGR6_DIR ((uint16_t)0x0010) /* Data transfer direction */
1306+
#define DMA_CFGR6_CIRC ((uint16_t)0x0020) /* Circular mode */
1307+
#define DMA_CFGR6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
1308+
#define DMA_CFGR6_MINC ((uint16_t)0x0080) /* Memory increment mode */
1309+
1310+
#define DMA_CFGR6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
1311+
#define DMA_CFGR6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
1312+
#define DMA_CFGR6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
1313+
1314+
#define DMA_CFGR6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
1315+
#define DMA_CFGR6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
1316+
#define DMA_CFGR6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
1317+
1318+
#define DMA_CFGR6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
1319+
#define DMA_CFGR6_PL_0 ((uint16_t)0x1000) /* Bit 0 */
1320+
#define DMA_CFGR6_PL_1 ((uint16_t)0x2000) /* Bit 1 */
1321+
1322+
#define DMA_CFGR6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
1323+
1324+
/******************* Bit definition for DMA_CFGR7 register *******************/
1325+
#define DMA_CFGR7_EN ((uint16_t)0x0001) /* Channel enable */
1326+
#define DMA_CFGR7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
1327+
#define DMA_CFGR7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
1328+
#define DMA_CFGR7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
1329+
#define DMA_CFGR7_DIR ((uint16_t)0x0010) /* Data transfer direction */
1330+
#define DMA_CFGR7_CIRC ((uint16_t)0x0020) /* Circular mode */
1331+
#define DMA_CFGR7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
1332+
#define DMA_CFGR7_MINC ((uint16_t)0x0080) /* Memory increment mode */
1333+
1334+
#define DMA_CFGR7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
1335+
#define DMA_CFGR7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
1336+
#define DMA_CFGR7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
1337+
1338+
#define DMA_CFGR7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
1339+
#define DMA_CFGR7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
1340+
#define DMA_CFGR7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
1341+
1342+
#define DMA_CFGR7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
1343+
#define DMA_CFGR7_PL_0 ((uint16_t)0x1000) /* Bit 0 */
1344+
#define DMA_CFGR7_PL_1 ((uint16_t)0x2000) /* Bit 1 */
1345+
1346+
#define DMA_CFGR7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */
13471347

13481348
/****************** Bit definition for DMA_CNTR1 register ******************/
13491349
#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */

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